pl18x.h File Reference

#include "ultibo/mmc.h"

Go to the source code of this file.

Data Structures
struct	_PL18X_VERSIONID
struct	_PL18X_VERSIONDATA
struct	_PL18X_MMCIREGISTERS
struct	_PL18X_SDHCIHOST

Macros
#define	PL180_MMCI_DESCRIPTION   "ARM PrimeCell PL180 MMCI Host"
	Description of PL180 device.
#define	PL181_MMCI_DESCRIPTION   "ARM PrimeCell PL181 MMCI Host"
	Description of PL181 device.
#define	PL18X_MMCI_POWER   0x000
#define	PL18X_MMCI_POWER_OFF   0x00
	Power-off.
#define	PL18X_MMCI_POWER_UP   0x02
	Power-up.
#define	PL18X_MMCI_POWER_ON   0x03
	Power-on.
#define	PL18X_MMCI_POWER_OD   (1 << 6)
	MCICMD output control.
#define	PL18X_MMCI_POWER_ROD   (1 << 7)
	Rod control.
#define	PL18X_MMCI_POWER_ST_DATA2DIREN   (1 << 2)
#define	PL18X_MMCI_POWER_ST_CMDDIREN   (1 << 3)
#define	PL18X_MMCI_POWER_ST_DATA0DIREN   (1 << 4)
#define	PL18X_MMCI_POWER_ST_DATA31DIREN   (1 << 5)
#define	PL18X_MMCI_POWER_ST_FBCLKEN   (1 << 7)
#define	PL18X_MMCI_POWER_ST_DATA74DIREN   (1 << 8)
#define	PL18X_MMCI_CLOCK   0x004
#define	PL18X_MMCI_CLOCK_ENABLE   (1 << 8)
	Enable MCI bus clock: 0 = Clock disabled / 1 = Clock enabled.
#define	PL18X_MMCI_CLOCK_PWRSAVE   (1 << 9)
	Disable MCI clock output when bus is idle: 0 = Always enabled / 1 = Clock enabled when bus is active.
#define	PL18X_MMCI_CLOCK_BYPASS   (1 << 10)
	Enable bypass of clock divide logic: 0 = Disable bypass / 1 = Enable bypass.
#define	PL18X_MMCI_CLOCK_4BIT_BUS   (1 << 11)
	Enable wide bus mode: 0 = Standard bus mode (only MCIDAT0 used) / 1 = Wide bus mode (MCIDAT3:0 used).
#define	PL18X_MMCI_CLOCK_ST_8BIT_BUS   (1 << 12)
#define	PL18X_MMCI_CLOCK_ST_U300_HWFCEN   (1 << 13)
#define	PL18X_MMCI_CLOCK_ST_UX500_NEG_EDGE   (1 << 13)
#define	PL18X_MMCI_CLOCK_ST_UX500_HWFCEN   (1 << 14)
#define	PL18X_MMCI_CLOCK_ST_UX500_CLK_INV   (1 << 15)
#define	PL18X_MMCI_CLOCK_ARM_HWFCEN   (1 << 12)
#define	PL18X_MMCI_CLOCK_QCOM_WIDEBUS_8   (1 << 10) | (1 << 11)
#define	PL18X_MMCI_CLOCK_QCOM_FLOWENA   (1 << 12)
#define	PL18X_MMCI_CLOCK_QCOM_INVERTOUT   (1 << 13)
#define	PL18X_MMCI_CLOCK_QCOM_SELECT_IN_FBCLK   (1 << 15)
#define	PL18X_MMCI_CLOCK_QCOM_SELECT_IN_DDR_MODE   (1 << 14) | (1 << 15)
#define	PL18X_MMCI_ARGUMENT   0x008
#define	PL18X_MMCI_COMMAND   0x00c
#define	PL18X_MMCI_CPSM_RESPONSE   (1 << 6)
	If set, CPSM waits for a response.
#define	PL18X_MMCI_CPSM_LONGRSP   (1 << 7)
	If set, CPSM receives a 136-bit long response.
#define	PL18X_MMCI_CPSM_INTERRUPT   (1 << 8)
	If set, CPSM disables command timer and waits for interrupt request.
#define	PL18X_MMCI_CPSM_PENDING   (1 << 9)
	If set, CPSM waits for CmdPend before it starts sending a command.
#define	PL18X_MMCI_CPSM_ENABLE   (1 << 10)
	If set, CPSM is enabled.
#define	PL18X_MMCI_CPSM_ST_SDIO_SUSP   (1 << 11)
#define	PL18X_MMCI_CPSM_ST_ENCMD_COMPL   (1 << 12)
#define	PL18X_MMCI_CPSM_ST_NIEN   (1 << 13)
#define	PL18X_MMCI_CPSM_ST_CE_ATACMD   (1 << 14)
#define	PL18X_MMCI_CPSM_QCOM_DATCMD   (1 << 12)
#define	PL18X_MMCI_CPSM_QCOM_MCIABORT   (1 << 13)
#define	PL18X_MMCI_CPSM_QCOM_CCSENABLE   (1 << 14)
#define	PL18X_MMCI_CPSM_QCOM_CCSDISABLE   (1 << 15)
#define	PL18X_MMCI_CPSM_QCOM_AUTO_CMD19   (1 << 16)
#define	PL18X_MMCI_CPSM_QCOM_AUTO_CMD21   (1 << 21)
#define	PL18X_MMCI_RESPCMD   0x010
#define	PL18X_MMCI_RESPONSE0   0x014
#define	PL18X_MMCI_RESPONSE1   0x018
#define	PL18X_MMCI_RESPONSE2   0x01c
#define	PL18X_MMCI_RESPONSE3   0x020
#define	PL18X_MMCI_DATATIMER   0x024
#define	PL18X_MMCI_DATALENGTH   0x028
#define	PL18X_MMCI_DATACTRL   0x02c
#define	PL18X_MMCI_DPSM_ENABLE   (1 << 0)
	Data transfer enabled.
#define	PL18X_MMCI_DPSM_DIRECTION   (1 << 1)
	Data transfer direction: 0 = From controller to card / 1 = From card to controller.
#define	PL18X_MMCI_DPSM_MODE   (1 << 2)
	Data transfer mode: 0 = Block data transfer / 1 = Stream data transfer.
#define	PL18X_MMCI_DPSM_DMAENABLE   (1 << 3)
	Enable DMA: 0 = DMA disabled / 1 = DMA enabled.
#define	PL18X_MMCI_DPSM_BLOCKSIZE   (1 << 4)
	Data block length.
#define	PL18X_MMCI_ST_DPSM_RWSTART   (1 << 8)
#define	PL18X_MMCI_ST_DPSM_RWSTOP   (1 << 9)
#define	PL18X_MMCI_ST_DPSM_RWMOD   (1 << 10)
#define	PL18X_MMCI_ST_DPSM_SDIOEN   (1 << 11)
#define	PL18X_MMCI_ST_DPSM_DMAREQCTL   (1 << 12)
#define	PL18X_MMCI_ST_DPSM_DBOOTMODEEN   (1 << 13)
#define	PL18X_MMCI_ST_DPSM_BUSYMODE   (1 << 14)
#define	PL18X_MMCI_ST_DPSM_DDRMODE   (1 << 15)
#define	PL18X_MMCI_DATACNT   0x030
#define	PL18X_MMCI_STATUS   0x034
#define	PL18X_MMCI_CMDCRCFAIL   (1 << 0)
#define	PL18X_MMCI_DATACRCFAIL   (1 << 1)
#define	PL18X_MMCI_CMDTIMEOUT   (1 << 2)
#define	PL18X_MMCI_DATATIMEOUT   (1 << 3)
#define	PL18X_MMCI_TXUNDERRUN   (1 << 4)
#define	PL18X_MMCI_RXOVERRUN   (1 << 5)
#define	PL18X_MMCI_CMDRESPEND   (1 << 6)
#define	PL18X_MMCI_CMDSENT   (1 << 7)
#define	PL18X_MMCI_DATAEND   (1 << 8)
#define	PL18X_MMCI_STARTBITERR   (1 << 9)
#define	PL18X_MMCI_DATABLOCKEND   (1 << 10)
#define	PL18X_MMCI_CMDACTIVE   (1 << 11)
#define	PL18X_MMCI_TXACTIVE   (1 << 12)
#define	PL18X_MMCI_RXACTIVE   (1 << 13)
#define	PL18X_MMCI_TXFIFOHALFEMPTY   (1 << 14)
#define	PL18X_MMCI_RXFIFOHALFFULL   (1 << 15)
#define	PL18X_MMCI_TXFIFOFULL   (1 << 16)
#define	PL18X_MMCI_RXFIFOFULL   (1 << 17)
#define	PL18X_MMCI_TXFIFOEMPTY   (1 << 18)
#define	PL18X_MMCI_RXFIFOEMPTY   (1 << 19)
#define	PL18X_MMCI_TXDATAAVLBL   (1 << 20)
#define	PL18X_MMCI_RXDATAAVLBL   (1 << 21)
#define	PL18X_MMCI_ST_SDIOIT   (1 << 22)
#define	PL18X_MMCI_ST_CEATAEND   (1 << 23)
#define	PL18X_MMCI_ST_CARDBUSY   (1 << 24)
#define	PL18X_MMCI_CLEAR   0x038
#define	PL18X_MMCI_CMDCRCFAILCLR   (1 << 0)
#define	PL18X_MMCI_DATACRCFAILCLR   (1 << 1)
#define	PL18X_MMCI_CMDTIMEOUTCLR   (1 << 2)
#define	PL18X_MMCI_DATATIMEOUTCLR   (1 << 3)
#define	PL18X_MMCI_TXUNDERRUNCLR   (1 << 4)
#define	PL18X_MMCI_RXOVERRUNCLR   (1 << 5)
#define	PL18X_MMCI_CMDRESPENDCLR   (1 << 6)
#define	PL18X_MMCI_CMDSENTCLR   (1 << 7)
#define	PL18X_MMCI_DATAENDCLR   (1 << 8)
#define	PL18X_MMCI_STARTBITERRCLR   (1 << 9)
#define	PL18X_MMCI_DATABLOCKENDCLR   (1 << 10)
#define	PL18X_MMCI_ST_SDIOITC   (1 << 22)
#define	PL18X_MMCI_ST_CEATAENDC   (1 << 23)
#define	PL18X_MMCI_ST_BUSYENDC   (1 << 24)
#define	PL18X_MMCI_MASK0   0x03c
#define	PL18X_MMCI_MASK1   0x040
#define	PL18X_MMCI_CMDCRCFAILMASK   (1 << 0)
#define	PL18X_MMCI_DATACRCFAILMASK   (1 << 1)
#define	PL18X_MMCI_CMDTIMEOUTMASK   (1 << 2)
#define	PL18X_MMCI_DATATIMEOUTMASK   (1 << 3)
#define	PL18X_MMCI_TXUNDERRUNMASK   (1 << 4)
#define	PL18X_MMCI_RXOVERRUNMASK   (1 << 5)
#define	PL18X_MMCI_CMDRESPENDMASK   (1 << 6)
#define	PL18X_MMCI_CMDSENTMASK   (1 << 7)
#define	PL18X_MMCI_DATAENDMASK   (1 << 8)
#define	PL18X_MMCI_STARTBITERRMASK   (1 << 9)
#define	PL18X_MMCI_DATABLOCKENDMASK   (1 << 10)
#define	PL18X_MMCI_CMDACTIVEMASK   (1 << 11)
#define	PL18X_MMCI_TXACTIVEMASK   (1 << 12)
#define	PL18X_MMCI_RXACTIVEMASK   (1 << 13)
#define	PL18X_MMCI_TXFIFOHALFEMPTYMASK   (1 << 14)
#define	PL18X_MMCI_RXFIFOHALFFULLMASK   (1 << 15)
#define	PL18X_MMCI_TXFIFOFULLMASK   (1 << 16)
#define	PL18X_MMCI_RXFIFOFULLMASK   (1 << 17)
#define	PL18X_MMCI_TXFIFOEMPTYMASK   (1 << 18)
#define	PL18X_MMCI_RXFIFOEMPTYMASK   (1 << 19)
#define	PL18X_MMCI_TXDATAAVLBLMASK   (1 << 20)
#define	PL18X_MMCI_RXDATAAVLBLMASK   (1 << 21)
#define	PL18X_MMCI_ST_SDIOITMASK   (1 << 22)
#define	PL18X_MMCI_ST_CEATAENDMASK   (1 << 23)
#define	PL18X_MMCI_ST_BUSYEND   (1 << 24)
#define	PL18X_MMCI_SELECT   0x044
#define	PL18X_MMCI_FIFOCNT   0x048
#define	PL18X_MMCI_FIFO   0x080
	To 0x0bc.
#define	PL18X_MMCI_PERIPHID   0xFE0
#define	PL18X_MMCI_PCELLID   0xFF0
#define	PL18X_MMCI_IRQENABLE   (PL18X_MMCI_CMDCRCFAILMASK | PL18X_MMCI_DATACRCFAILMASK | PL18X_MMCI_CMDTIMEOUTMASK | PL18X_MMCI_DATATIMEOUTMASK | PL18X_MMCI_TXUNDERRUNMASK | PL18X_MMCI_RXOVERRUNMASK | PL18X_MMCI_CMDRESPENDMASK | PL18X_MMCI_CMDSENTMASK | PL18X_MMCI_STARTBITERRMASK)
#define	PL18X_MMCI_IRQ1MASK   (PL18X_MMCI_RXFIFOHALFFULLMASK | PL18X_MMCI_RXDATAAVLBLMASK | PL18X_MMCI_TXFIFOHALFEMPTYMASK)

Typedefs
typedef struct _PL18X_VERSIONDATA	PL18X_VERSIONDATA
typedef struct _PL18X_VERSIONID	PL18X_VERSIONID
typedef struct _PL18X_MMCIREGISTERS	PL18X_MMCIREGISTERS
typedef struct _PL18X_SDHCIHOST	PL18X_SDHCIHOST
typedef uint32_t STDCALL(*	pl18xsdhci_get_rxfifo_count_proc) (PL18X_SDHCIHOST *sdhci, uint32_t status, uint32_t remain)

Functions
void STDCALL	pl18x_init (void)
SDHCI_HOST *STDCALL	pl180sdhci_create (size_t address, char *name, uint32_t irq0, uint32_t irq1, uint32_t clockminimum, uint32_t clockmaximum, mmc_device_get_card_detect_proc carddetect, mmc_device_get_write_protect_proc writeprotect)
	Create and register a new PL180 SDHCI device which can be accessed using the SDHCI API.
SDHCI_HOST *STDCALL	pl181sdhci_create (size_t address, char *name, uint32_t irq0, uint32_t irq1, uint32_t clockminimum, uint32_t clockmaximum, mmc_device_get_card_detect_proc carddetect, mmc_device_get_write_protect_proc writeprotect)
	Create and register a new PL181 SDHCI device which can be accessed using the SDHCI API.
uint32_t STDCALL	pl18xsdhci_destroy (SDHCI_HOST *sdhci)
	Stop, deregister and destroy a PL18X SDHCI device created by this driver.

Macro Definition Documentation

PL180_MMCI_DESCRIPTION

#define PL180_MMCI_DESCRIPTION   "ARM PrimeCell PL180 MMCI Host"

Description of PL180 device.

PL18X specific constants

PL181_MMCI_DESCRIPTION

#define PL181_MMCI_DESCRIPTION   "ARM PrimeCell PL181 MMCI Host"

Description of PL181 device.

PL18X_MMCI_POWER

#define PL18X_MMCI_POWER   0x000

PL18X Power control register

PL18X_MMCI_POWER_OFF

#define PL18X_MMCI_POWER_OFF   0x00

Power-off.

PL18X_MMCI_POWER_UP

#define PL18X_MMCI_POWER_UP   0x02

Power-up.

Bits 1:0 - 0x01 Reserved

PL18X_MMCI_POWER_ON

#define PL18X_MMCI_POWER_ON   0x03

Power-on.

PL18X_MMCI_POWER_OD

#define PL18X_MMCI_POWER_OD   (1 << 6)

MCICMD output control.

Bits 5:2 - Output Voltage

PL18X_MMCI_POWER_ROD

#define PL18X_MMCI_POWER_ROD   (1 << 7)

Rod control.

PL18X_MMCI_POWER_ST_DATA2DIREN

#define PL18X_MMCI_POWER_ST_DATA2DIREN   (1 << 2)

The ST Micro version does not have ROD and reuses the voltage registers for direction settings

PL18X_MMCI_POWER_ST_CMDDIREN

#define PL18X_MMCI_POWER_ST_CMDDIREN   (1 << 3)

PL18X_MMCI_POWER_ST_DATA0DIREN

#define PL18X_MMCI_POWER_ST_DATA0DIREN   (1 << 4)

PL18X_MMCI_POWER_ST_DATA31DIREN

#define PL18X_MMCI_POWER_ST_DATA31DIREN   (1 << 5)

PL18X_MMCI_POWER_ST_FBCLKEN

#define PL18X_MMCI_POWER_ST_FBCLKEN   (1 << 7)

PL18X_MMCI_POWER_ST_DATA74DIREN

#define PL18X_MMCI_POWER_ST_DATA74DIREN   (1 << 8)

PL18X_MMCI_CLOCK

#define PL18X_MMCI_CLOCK   0x004

PL18X Clock control register

PL18X_MMCI_CLOCK_ENABLE

#define PL18X_MMCI_CLOCK_ENABLE   (1 << 8)

Enable MCI bus clock: 0 = Clock disabled / 1 = Clock enabled.

PL18X_MMCI_CLOCK_PWRSAVE

#define PL18X_MMCI_CLOCK_PWRSAVE   (1 << 9)

Disable MCI clock output when bus is idle: 0 = Always enabled / 1 = Clock enabled when bus is active.

PL18X_MMCI_CLOCK_BYPASS

#define PL18X_MMCI_CLOCK_BYPASS   (1 << 10)

Enable bypass of clock divide logic: 0 = Disable bypass / 1 = Enable bypass.

PL18X_MMCI_CLOCK_4BIT_BUS

#define PL18X_MMCI_CLOCK_4BIT_BUS   (1 << 11)

Enable wide bus mode: 0 = Standard bus mode (only MCIDAT0 used) / 1 = Wide bus mode (MCIDAT3:0 used).

PL18X_MMCI_CLOCK_ST_8BIT_BUS

#define PL18X_MMCI_CLOCK_ST_8BIT_BUS   (1 << 12)

8bit wide buses, hardware flow contronl, negative edges and clock inversion supported in ST Micro U300 and Ux500 versions

PL18X_MMCI_CLOCK_ST_U300_HWFCEN

#define PL18X_MMCI_CLOCK_ST_U300_HWFCEN   (1 << 13)

PL18X_MMCI_CLOCK_ST_UX500_NEG_EDGE

#define PL18X_MMCI_CLOCK_ST_UX500_NEG_EDGE   (1 << 13)

PL18X_MMCI_CLOCK_ST_UX500_HWFCEN

#define PL18X_MMCI_CLOCK_ST_UX500_HWFCEN   (1 << 14)

PL18X_MMCI_CLOCK_ST_UX500_CLK_INV

#define PL18X_MMCI_CLOCK_ST_UX500_CLK_INV   (1 << 15)

PL18X_MMCI_CLOCK_ARM_HWFCEN

#define PL18X_MMCI_CLOCK_ARM_HWFCEN   (1 << 12)

Modified PL180 on Versatile Express platform

PL18X_MMCI_CLOCK_QCOM_WIDEBUS_8

#define PL18X_MMCI_CLOCK_QCOM_WIDEBUS_8   (1 << 10) | (1 << 11)

Modified on Qualcomm Integrations

PL18X_MMCI_CLOCK_QCOM_FLOWENA

#define PL18X_MMCI_CLOCK_QCOM_FLOWENA   (1 << 12)

PL18X_MMCI_CLOCK_QCOM_INVERTOUT

#define PL18X_MMCI_CLOCK_QCOM_INVERTOUT   (1 << 13)

PL18X_MMCI_CLOCK_QCOM_SELECT_IN_FBCLK

#define PL18X_MMCI_CLOCK_QCOM_SELECT_IN_FBCLK   (1 << 15)

Select in latch data and command in

PL18X_MMCI_CLOCK_QCOM_SELECT_IN_DDR_MODE

#define PL18X_MMCI_CLOCK_QCOM_SELECT_IN_DDR_MODE   (1 << 14) | (1 << 15)

PL18X_MMCI_ARGUMENT

#define PL18X_MMCI_ARGUMENT   0x008

PL18X Argument register

PL18X_MMCI_COMMAND

#define PL18X_MMCI_COMMAND   0x00c

Bits 31:0 Command Argument PL18X Command register

PL18X_MMCI_CPSM_RESPONSE

#define PL18X_MMCI_CPSM_RESPONSE   (1 << 6)

If set, CPSM waits for a response.

Bits 5:0 Command Index

PL18X_MMCI_CPSM_LONGRSP

#define PL18X_MMCI_CPSM_LONGRSP   (1 << 7)

If set, CPSM receives a 136-bit long response.

PL18X_MMCI_CPSM_INTERRUPT

#define PL18X_MMCI_CPSM_INTERRUPT   (1 << 8)

If set, CPSM disables command timer and waits for interrupt request.

PL18X_MMCI_CPSM_PENDING

#define PL18X_MMCI_CPSM_PENDING   (1 << 9)

If set, CPSM waits for CmdPend before it starts sending a command.

PL18X_MMCI_CPSM_ENABLE

#define PL18X_MMCI_CPSM_ENABLE   (1 << 10)

If set, CPSM is enabled.

PL18X_MMCI_CPSM_ST_SDIO_SUSP

#define PL18X_MMCI_CPSM_ST_SDIO_SUSP   (1 << 11)

Argument flag extenstions in the ST Micro versions

PL18X_MMCI_CPSM_ST_ENCMD_COMPL

#define PL18X_MMCI_CPSM_ST_ENCMD_COMPL   (1 << 12)

PL18X_MMCI_CPSM_ST_NIEN

#define PL18X_MMCI_CPSM_ST_NIEN   (1 << 13)

PL18X_MMCI_CPSM_ST_CE_ATACMD

#define PL18X_MMCI_CPSM_ST_CE_ATACMD   (1 << 14)

PL18X_MMCI_CPSM_QCOM_DATCMD

#define PL18X_MMCI_CPSM_QCOM_DATCMD   (1 << 12)

Modified on Qualcomm Integrations

PL18X_MMCI_CPSM_QCOM_MCIABORT

#define PL18X_MMCI_CPSM_QCOM_MCIABORT   (1 << 13)

PL18X_MMCI_CPSM_QCOM_CCSENABLE

#define PL18X_MMCI_CPSM_QCOM_CCSENABLE   (1 << 14)

PL18X_MMCI_CPSM_QCOM_CCSDISABLE

#define PL18X_MMCI_CPSM_QCOM_CCSDISABLE   (1 << 15)

PL18X_MMCI_CPSM_QCOM_AUTO_CMD19

#define PL18X_MMCI_CPSM_QCOM_AUTO_CMD19   (1 << 16)

PL18X_MMCI_CPSM_QCOM_AUTO_CMD21

#define PL18X_MMCI_CPSM_QCOM_AUTO_CMD21   (1 << 21)

PL18X_MMCI_RESPCMD

#define PL18X_MMCI_RESPCMD   0x010

PL18X Command response register

PL18X_MMCI_RESPONSE0

#define PL18X_MMCI_RESPONSE0   0x014

Bits 5:0 Response command index Bits 31:6 Reserved PL18X Response registers

PL18X_MMCI_RESPONSE1

#define PL18X_MMCI_RESPONSE1   0x018

PL18X_MMCI_RESPONSE2

#define PL18X_MMCI_RESPONSE2   0x01c

PL18X_MMCI_RESPONSE3

#define PL18X_MMCI_RESPONSE3   0x020

PL18X_MMCI_DATATIMER

#define PL18X_MMCI_DATATIMER   0x024

Bits 31:0 Card Status PL18X Data timer register

PL18X_MMCI_DATALENGTH

#define PL18X_MMCI_DATALENGTH   0x028

Bits 31:0 Data Timeout Period PL18X Data length register

PL18X_MMCI_DATACTRL

#define PL18X_MMCI_DATACTRL   0x02c

Bits 15:0 Data Length Value Bits 31:16 Reserved PL18X Data control register

PL18X_MMCI_DPSM_ENABLE

#define PL18X_MMCI_DPSM_ENABLE   (1 << 0)

Data transfer enabled.

PL18X_MMCI_DPSM_DIRECTION

#define PL18X_MMCI_DPSM_DIRECTION   (1 << 1)

Data transfer direction: 0 = From controller to card / 1 = From card to controller.

PL18X_MMCI_DPSM_MODE

#define PL18X_MMCI_DPSM_MODE   (1 << 2)

Data transfer mode: 0 = Block data transfer / 1 = Stream data transfer.

PL18X_MMCI_DPSM_DMAENABLE

#define PL18X_MMCI_DPSM_DMAENABLE   (1 << 3)

Enable DMA: 0 = DMA disabled / 1 = DMA enabled.

PL18X_MMCI_DPSM_BLOCKSIZE

#define PL18X_MMCI_DPSM_BLOCKSIZE   (1 << 4)

Data block length.

PL18X_MMCI_ST_DPSM_RWSTART

#define PL18X_MMCI_ST_DPSM_RWSTART   (1 << 8)

Control register extensions in the ST Micro U300 and Ux500 versions

PL18X_MMCI_ST_DPSM_RWSTOP

#define PL18X_MMCI_ST_DPSM_RWSTOP   (1 << 9)

PL18X_MMCI_ST_DPSM_RWMOD

#define PL18X_MMCI_ST_DPSM_RWMOD   (1 << 10)

PL18X_MMCI_ST_DPSM_SDIOEN

#define PL18X_MMCI_ST_DPSM_SDIOEN   (1 << 11)

PL18X_MMCI_ST_DPSM_DMAREQCTL

#define PL18X_MMCI_ST_DPSM_DMAREQCTL   (1 << 12)

Control register extensions in the ST Micro Ux500 versions

PL18X_MMCI_ST_DPSM_DBOOTMODEEN

#define PL18X_MMCI_ST_DPSM_DBOOTMODEEN   (1 << 13)

PL18X_MMCI_ST_DPSM_BUSYMODE

#define PL18X_MMCI_ST_DPSM_BUSYMODE   (1 << 14)

PL18X_MMCI_ST_DPSM_DDRMODE

#define PL18X_MMCI_ST_DPSM_DDRMODE   (1 << 15)

PL18X_MMCI_DATACNT

#define PL18X_MMCI_DATACNT   0x030

PL18X Data counter register

PL18X_MMCI_STATUS

#define PL18X_MMCI_STATUS   0x034

Bits 15:0 Remaining Data Bits 31:16 Reserved PL18X Status register

PL18X_MMCI_CMDCRCFAIL

#define PL18X_MMCI_CMDCRCFAIL   (1 << 0)

PL18X_MMCI_DATACRCFAIL

#define PL18X_MMCI_DATACRCFAIL   (1 << 1)

PL18X_MMCI_CMDTIMEOUT

#define PL18X_MMCI_CMDTIMEOUT   (1 << 2)

PL18X_MMCI_DATATIMEOUT

#define PL18X_MMCI_DATATIMEOUT   (1 << 3)

PL18X_MMCI_TXUNDERRUN

#define PL18X_MMCI_TXUNDERRUN   (1 << 4)

PL18X_MMCI_RXOVERRUN

#define PL18X_MMCI_RXOVERRUN   (1 << 5)

PL18X_MMCI_CMDRESPEND

#define PL18X_MMCI_CMDRESPEND   (1 << 6)

PL18X_MMCI_CMDSENT

#define PL18X_MMCI_CMDSENT   (1 << 7)

PL18X_MMCI_DATAEND

#define PL18X_MMCI_DATAEND   (1 << 8)

PL18X_MMCI_STARTBITERR

#define PL18X_MMCI_STARTBITERR   (1 << 9)

PL18X_MMCI_DATABLOCKEND

#define PL18X_MMCI_DATABLOCKEND   (1 << 10)

PL18X_MMCI_CMDACTIVE

#define PL18X_MMCI_CMDACTIVE   (1 << 11)

PL18X_MMCI_TXACTIVE

#define PL18X_MMCI_TXACTIVE   (1 << 12)

PL18X_MMCI_RXACTIVE

#define PL18X_MMCI_RXACTIVE   (1 << 13)

PL18X_MMCI_TXFIFOHALFEMPTY

#define PL18X_MMCI_TXFIFOHALFEMPTY   (1 << 14)

PL18X_MMCI_RXFIFOHALFFULL

#define PL18X_MMCI_RXFIFOHALFFULL   (1 << 15)

PL18X_MMCI_TXFIFOFULL

#define PL18X_MMCI_TXFIFOFULL   (1 << 16)

PL18X_MMCI_RXFIFOFULL

#define PL18X_MMCI_RXFIFOFULL   (1 << 17)

PL18X_MMCI_TXFIFOEMPTY

#define PL18X_MMCI_TXFIFOEMPTY   (1 << 18)

PL18X_MMCI_RXFIFOEMPTY

#define PL18X_MMCI_RXFIFOEMPTY   (1 << 19)

PL18X_MMCI_TXDATAAVLBL

#define PL18X_MMCI_TXDATAAVLBL   (1 << 20)

PL18X_MMCI_RXDATAAVLBL

#define PL18X_MMCI_RXDATAAVLBL   (1 << 21)

PL18X_MMCI_ST_SDIOIT

#define PL18X_MMCI_ST_SDIOIT   (1 << 22)

Extended status bits for the ST Micro variants

PL18X_MMCI_ST_CEATAEND

#define PL18X_MMCI_ST_CEATAEND   (1 << 23)

PL18X_MMCI_ST_CARDBUSY

#define PL18X_MMCI_ST_CARDBUSY   (1 << 24)

PL18X_MMCI_CLEAR

#define PL18X_MMCI_CLEAR   0x038

PL18X Clear register

PL18X_MMCI_CMDCRCFAILCLR

#define PL18X_MMCI_CMDCRCFAILCLR   (1 << 0)

PL18X_MMCI_DATACRCFAILCLR

#define PL18X_MMCI_DATACRCFAILCLR   (1 << 1)

PL18X_MMCI_CMDTIMEOUTCLR

#define PL18X_MMCI_CMDTIMEOUTCLR   (1 << 2)

PL18X_MMCI_DATATIMEOUTCLR

#define PL18X_MMCI_DATATIMEOUTCLR   (1 << 3)

PL18X_MMCI_TXUNDERRUNCLR

#define PL18X_MMCI_TXUNDERRUNCLR   (1 << 4)

PL18X_MMCI_RXOVERRUNCLR

#define PL18X_MMCI_RXOVERRUNCLR   (1 << 5)

PL18X_MMCI_CMDRESPENDCLR

#define PL18X_MMCI_CMDRESPENDCLR   (1 << 6)

PL18X_MMCI_CMDSENTCLR

#define PL18X_MMCI_CMDSENTCLR   (1 << 7)

PL18X_MMCI_DATAENDCLR

#define PL18X_MMCI_DATAENDCLR   (1 << 8)

PL18X_MMCI_STARTBITERRCLR

#define PL18X_MMCI_STARTBITERRCLR   (1 << 9)

PL18X_MMCI_DATABLOCKENDCLR

#define PL18X_MMCI_DATABLOCKENDCLR   (1 << 10)

PL18X_MMCI_ST_SDIOITC

#define PL18X_MMCI_ST_SDIOITC   (1 << 22)

Extended status bits for the ST Micro variants

PL18X_MMCI_ST_CEATAENDC

#define PL18X_MMCI_ST_CEATAENDC   (1 << 23)

PL18X_MMCI_ST_BUSYENDC

#define PL18X_MMCI_ST_BUSYENDC   (1 << 24)

PL18X_MMCI_MASK0

#define PL18X_MMCI_MASK0   0x03c

PL18X Interrupt mask registers

PL18X_MMCI_MASK1

#define PL18X_MMCI_MASK1   0x040

PL18X_MMCI_CMDCRCFAILMASK

#define PL18X_MMCI_CMDCRCFAILMASK   (1 << 0)

PL18X_MMCI_DATACRCFAILMASK

#define PL18X_MMCI_DATACRCFAILMASK   (1 << 1)

PL18X_MMCI_CMDTIMEOUTMASK

#define PL18X_MMCI_CMDTIMEOUTMASK   (1 << 2)

PL18X_MMCI_DATATIMEOUTMASK

#define PL18X_MMCI_DATATIMEOUTMASK   (1 << 3)

PL18X_MMCI_TXUNDERRUNMASK

#define PL18X_MMCI_TXUNDERRUNMASK   (1 << 4)

PL18X_MMCI_RXOVERRUNMASK

#define PL18X_MMCI_RXOVERRUNMASK   (1 << 5)

PL18X_MMCI_CMDRESPENDMASK

#define PL18X_MMCI_CMDRESPENDMASK   (1 << 6)

PL18X_MMCI_CMDSENTMASK

#define PL18X_MMCI_CMDSENTMASK   (1 << 7)

PL18X_MMCI_DATAENDMASK

#define PL18X_MMCI_DATAENDMASK   (1 << 8)

PL18X_MMCI_STARTBITERRMASK

#define PL18X_MMCI_STARTBITERRMASK   (1 << 9)

PL18X_MMCI_DATABLOCKENDMASK

#define PL18X_MMCI_DATABLOCKENDMASK   (1 << 10)

PL18X_MMCI_CMDACTIVEMASK

#define PL18X_MMCI_CMDACTIVEMASK   (1 << 11)

PL18X_MMCI_TXACTIVEMASK

#define PL18X_MMCI_TXACTIVEMASK   (1 << 12)

PL18X_MMCI_RXACTIVEMASK

#define PL18X_MMCI_RXACTIVEMASK   (1 << 13)

PL18X_MMCI_TXFIFOHALFEMPTYMASK

#define PL18X_MMCI_TXFIFOHALFEMPTYMASK   (1 << 14)

PL18X_MMCI_RXFIFOHALFFULLMASK

#define PL18X_MMCI_RXFIFOHALFFULLMASK   (1 << 15)

PL18X_MMCI_TXFIFOFULLMASK

#define PL18X_MMCI_TXFIFOFULLMASK   (1 << 16)

PL18X_MMCI_RXFIFOFULLMASK

#define PL18X_MMCI_RXFIFOFULLMASK   (1 << 17)

PL18X_MMCI_TXFIFOEMPTYMASK

#define PL18X_MMCI_TXFIFOEMPTYMASK   (1 << 18)

PL18X_MMCI_RXFIFOEMPTYMASK

#define PL18X_MMCI_RXFIFOEMPTYMASK   (1 << 19)

PL18X_MMCI_TXDATAAVLBLMASK

#define PL18X_MMCI_TXDATAAVLBLMASK   (1 << 20)

PL18X_MMCI_RXDATAAVLBLMASK

#define PL18X_MMCI_RXDATAAVLBLMASK   (1 << 21)

PL18X_MMCI_ST_SDIOITMASK

#define PL18X_MMCI_ST_SDIOITMASK   (1 << 22)

Extended status bits for the ST Micro variants

PL18X_MMCI_ST_CEATAENDMASK

#define PL18X_MMCI_ST_CEATAENDMASK   (1 << 23)

PL18X_MMCI_ST_BUSYEND

#define PL18X_MMCI_ST_BUSYEND   (1 << 24)

PL18X_MMCI_SELECT

#define PL18X_MMCI_SELECT   0x044

PL18X SD card select register

PL18X_MMCI_FIFOCNT

#define PL18X_MMCI_FIFOCNT   0x048

PL18X FIFO counter register

PL18X_MMCI_FIFO

#define PL18X_MMCI_FIFO   0x080

To 0x0bc.

PL18X Data FIFO register

PL18X_MMCI_PERIPHID

#define PL18X_MMCI_PERIPHID   0xFE0

PL18X Peripheral identification register

PL18X_MMCI_PCELLID

#define PL18X_MMCI_PCELLID   0xFF0

PL18X PrimeCell identification register

PL18X_MMCI_IRQENABLE

#define PL18X_MMCI_IRQENABLE   (PL18X_MMCI_CMDCRCFAILMASK | PL18X_MMCI_DATACRCFAILMASK | PL18X_MMCI_CMDTIMEOUTMASK | PL18X_MMCI_DATATIMEOUTMASK | PL18X_MMCI_TXUNDERRUNMASK | PL18X_MMCI_RXOVERRUNMASK | PL18X_MMCI_CMDRESPENDMASK | PL18X_MMCI_CMDSENTMASK | PL18X_MMCI_STARTBITERRMASK)

PL18X_MMCI_IRQ1MASK

#define PL18X_MMCI_IRQ1MASK   (PL18X_MMCI_RXFIFOHALFFULLMASK | PL18X_MMCI_RXDATAAVLBLMASK | PL18X_MMCI_TXFIFOHALFEMPTYMASK)

These interrupts are directed to IRQ1 when two IRQ lines are available

Typedef Documentation

PL18X_VERSIONDATA

typedef struct _PL18X_VERSIONDATA PL18X_VERSIONDATA

PL18X specific types

PL18X_VERSIONID

typedef struct _PL18X_VERSIONID PL18X_VERSIONID

PL18X_MMCIREGISTERS

typedef struct _PL18X_MMCIREGISTERS PL18X_MMCIREGISTERS

Layout of the PL18X registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0172a/i1006458.html)

PL18X_SDHCIHOST

typedef struct _PL18X_SDHCIHOST PL18X_SDHCIHOST

PL18X SDHCI types

pl18xsdhci_get_rxfifo_count_proc

typedef uint32_t STDCALL(* pl18xsdhci_get_rxfifo_count_proc) (PL18X_SDHCIHOST *sdhci, uint32_t status, uint32_t remain)

PL18X SDHCI Host Methods

Function Documentation

pl18x_init()

void STDCALL pl18x_init

(

void

)

Initialization Functions

pl180sdhci_create()

SDHCI_HOST *STDCALL pl180sdhci_create	(	size_t	address,
		char *	name,
		uint32_t	irq0,
		uint32_t	irq1,
		uint32_t	clockminimum,
		uint32_t	clockmaximum,
		mmc_device_get_card_detect_proc	carddetect,
		mmc_device_get_write_protect_proc	writeprotect )

Create and register a new PL180 SDHCI device which can be accessed using the SDHCI API.

PL18X Functions

Parameters

Address	The address of the PL180 registers
Name	The text description of this device which will show in the device list (Optional)
IRQ0	The interrupt 0 number for the PL180
IRQ1	The interrupt 1 number for the PL180
ClockMinimum	The minimum frequency for the Pl180 clock
ClockMaximum	The maximum frequency for the Pl180 clock

Returns

Pointer to the new SDHCI device or nil if the SDHCI device could not be created

pl181sdhci_create()

SDHCI_HOST *STDCALL pl181sdhci_create	(	size_t	address,
		char *	name,
		uint32_t	irq0,
		uint32_t	irq1,
		uint32_t	clockminimum,
		uint32_t	clockmaximum,
		mmc_device_get_card_detect_proc	carddetect,
		mmc_device_get_write_protect_proc	writeprotect )

Create and register a new PL181 SDHCI device which can be accessed using the SDHCI API.

Parameters

Address	The address of the PL181 registers
Name	The text description of this device which will show in the device list (Optional)
IRQ0	The interrupt 0 number for the PL181
IRQ1	The interrupt 1 number for the PL181
ClockMinimum	The minimum frequency for the Pl181 clock
ClockMaximum	The maximum frequency for the Pl181 clock

Returns

Pointer to the new SDHCI device or nil if the SDHCI device could not be created

pl18xsdhci_destroy()

uint32_t STDCALL pl18xsdhci_destroy

(

SDHCI_HOST *

sdhci

)

Stop, deregister and destroy a PL18X SDHCI device created by this driver.

Parameters

SDHCI

The SDHCI device to destroy

Returns

ERROR_SUCCESS if completed or another error code on failure