#include "ultibo/globaltypes.h"
#include "ultibo/globalconst.h"
#include "ultibo/devices.h"
#include "ultibo/storage.h"
#include "ultibo/dma.h"

Data Structures
struct	_MMC_COMMAND
struct	_MMC_DATA
struct	_MMC_CARD_IDENTIFICATION_DATA
struct	_MMC_CARD_SPECIFIC_SD_ERASE_DATA
struct	_MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA
struct	_MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA
union	_MMC_CARD_SPECIFIC_ERASE_DATA
struct	_MMC_CARD_SPECIFIC_DATA
struct	_MMC_EXTENDED_CARD_SPECIFIC_DATA
struct	_SD_STATUS_DATA
struct	_SD_SWITCH_DATA
struct	_SD_CONFIGURATION_DATA
struct	_MMC_DEVICE
struct	_SDIO_CCCR
struct	_SDIO_CIS
struct	_SDIO_TUPLE
struct	_SDIO_FUNCTION
struct	_SDIO_DRIVER
struct	_SDHCI_ADMA2_DESCRIPTOR32
struct	_SDHCI_ADMA2_DESCRIPTOR64
struct	_SDHCI_ADMA2_DESCRIPTOR64_V4
struct	_SDHCI_HOST

Macros
#define	MMC_NAME_PREFIX "MMC"
	Name prefix for MMC Devices.
#define	MMC_DEVICE_DESCRIPTION "MMC/SD Device"
	Description of MMC/SD device.
#define	MMC_STORAGE_DESCRIPTION "MMC/SD Storage Device"
	Description of MMC/SD storage device.
#define	MMC_STATUS_TIMER_INTERVAL 1000
#define	MMC_DEFAULT_BLOCKSIZE 512
#define	MMC_DEFAULT_BLOCKSHIFT 9
#define	MMC_TYPE_NONE 0
#define	MMC_TYPE_MMC 1
	An MMC specification card.
#define	MMC_TYPE_SD 2
	An SD specification card.
#define	MMC_TYPE_SDIO 3
	An SDIO specification card.
#define	MMC_TYPE_SD_COMBO 4
	An SD/SDIO combination card.
#define	MMC_TYPE_MAX 4
#define	MMC_STATE_EJECTED 0
#define	MMC_STATE_INSERTED 1
#define	MMC_STATE_MAX 1
#define	MMC_FLAG_NONE 0x00000000
#define	MMC_FLAG_CARD_PRESENT 0x00000001
	Card is present.
#define	MMC_FLAG_WRITE_PROTECT 0x00000002
	Card is write protected.
#define	MMC_FLAG_HIGH_CAPACITY 0x00000004
	High Capacity (SDHC).
#define	MMC_FLAG_EXT_CAPACITY 0x00000008
	Extended Capacity (SDXC).
#define	MMC_FLAG_UHS_I 0x00000010
	Ultra High Speed (UHS-I).
#define	MMC_FLAG_UHS_II 0x00000020
	Ultra High Speed (UHS-II).
#define	MMC_FLAG_BLOCK_ADDRESSED 0x00000040
	Block Addressed (SDHC/SDXC and others).
#define	MMC_FLAG_AUTO_BLOCK_COUNT 0x00000080
	Controller supports Auto CMD23 (Set Block Count).
#define	MMC_FLAG_AUTO_COMMAND_STOP 0x00000100
	Controller supports Auto CMD12 (Stop Transmission).
#define	MMC_FLAG_DDR_MODE 0x00000200
	Device supports DDR mode.
#define	MMC_FLAG_NON_REMOVABLE 0x00000400
	Device is non removable, only check for presence once.
#define	MMC_FLAG_SET_BLOCK_COUNT 0x00000800
	Device supports CMD23 (Set Block Count).
#define	MMC_STATUS_SUCCESS 0
	Function successful.
#define	MMC_STATUS_TIMEOUT 1
	The operation timed out.
#define	MMC_STATUS_NO_MEDIA 2
	No media present in device.
#define	MMC_STATUS_HARDWARE_ERROR 3
	Hardware error of some form occurred.
#define	MMC_STATUS_INVALID_DATA 4
	Invalid data was received.
#define	MMC_STATUS_INVALID_PARAMETER 5
	An invalid parameter was passed to the function.
#define	MMC_STATUS_INVALID_SEQUENCE 6
	Invalid sequence encountered.
#define	MMC_STATUS_OUT_OF_MEMORY 7
	No memory available for operation.
#define	MMC_STATUS_UNSUPPORTED_REQUEST 8
	The request is unsupported.
#define	MMC_STATUS_NOT_PROCESSED 9
	The MMC transfer has not yet been processed.
#define	MMC_STATUS_OPERATION_FAILED 10
	The operation was not able to be completed.
#define	MMC_STATUS_DEVICE_DETACHED 11
	SDIO device was detached.
#define	MMC_STATUS_DEVICE_UNSUPPORTED 12
	SDIO device is unsupported by the driver.
#define	MMC_STATUS_NOT_BOUND 13
	SDIO device is not bound to a driver.
#define	MMC_STATUS_ALREADY_BOUND 14
	SDIO device is already bound to a driver.
#define	MMC_STATUS_NOT_READY 15
	The device is not ready yet, retry again later.
#define	SDIO_VERSION_SDIO 0x00040000
#define	SDIO_VERSION_1_00 (SDIO_VERSION_SDIO \| 0x0100)
#define	SDIO_VERSION_1_10 (SDIO_VERSION_SDIO \| 0x010a)
#define	SDIO_VERSION_1_20 (SDIO_VERSION_SDIO \| 0x0114)
#define	SDIO_VERSION_2_00 (SDIO_VERSION_SDIO \| 0x0200)
#define	SDIO_VERSION_3_00 (SDIO_VERSION_SDIO \| 0x0300)
#define	SD_VERSION_SD 0x00020000
#define	SD_VERSION_1_0 (SD_VERSION_SD \| 0x0100)
#define	SD_VERSION_1_10 (SD_VERSION_SD \| 0x010a)
#define	SD_VERSION_2 (SD_VERSION_SD \| 0x0200)
#define	SD_VERSION_3 (SD_VERSION_SD \| 0x0300)
#define	SD_VERSION_4 (SD_VERSION_SD \| 0x0400)
#define	MMC_VERSION_MMC 0x00010000
#define	MMC_VERSION_1_2 (MMC_VERSION_MMC \| 0x0102)
#define	MMC_VERSION_1_4 (MMC_VERSION_MMC \| 0x0104)
#define	MMC_VERSION_2_2 (MMC_VERSION_MMC \| 0x0202)
#define	MMC_VERSION_3 (MMC_VERSION_MMC \| 0x0300)
#define	MMC_VERSION_4 (MMC_VERSION_MMC \| 0x0400)
#define	MMC_VERSION_4_1 (MMC_VERSION_MMC \| 0x0401)
#define	MMC_VERSION_4_2 (MMC_VERSION_MMC \| 0x0402)
#define	MMC_VERSION_4_3 (MMC_VERSION_MMC \| 0x0403)
#define	MMC_VERSION_4_41 (MMC_VERSION_MMC \| 0x0429)
#define	MMC_VERSION_4_5 (MMC_VERSION_MMC \| 0x0405)
#define	MMC_VERSION_5_0 (MMC_VERSION_MMC \| 0x0500)
#define	MMC_VERSION_5_1 (MMC_VERSION_MMC \| 0x0501)
#define	MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
#define	MMC_CAP_4_BIT_DATA (1 << 0)
	Can the host do 4 bit transfers.
#define	MMC_CAP_MMC_HIGHSPEED (1 << 1)
	Can do MMC high-speed timing.
#define	MMC_CAP_SD_HIGHSPEED (1 << 2)
	Can do SD high-speed timing.
#define	MMC_CAP_SDIO_IRQ (1 << 3)
	Can signal pending SDIO IRQs.
#define	MMC_CAP_SPI (1 << 4)
	Talks only SPI protocols.
#define	MMC_CAP_NEEDS_POLL (1 << 5)
	Needs polling for card-detection.
#define	MMC_CAP_8_BIT_DATA (1 << 6)
	Can the host do 8 bit transfers.
#define	MMC_CAP_AGGRESSIVE_PM (1 << 7)
	Suspend = (e)MMC/SD at idle.
#define	MMC_CAP_NONREMOVABLE (1 << 8)
	Nonremovable eg. eMMC.
#define	MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
	Waits while card is busy.
#define	MMC_CAP_3_3V_DDR (1 << 11)
	Host supports eMMC DDR 3.3V.
#define	MMC_CAP_1_8V_DDR (1 << 12)
	Host supports eMMC DDR 1.8V.
#define	MMC_CAP_1_2V_DDR (1 << 13)
	Host supports eMMC DDR 1.2V.
#define	MMC_CAP_DDR (MMC_CAP_3_3V_DDR \| MMC_CAP_1_8V_DDR \| MMC_CAP_1_2V_DDR)
#define	MMC_CAP_POWER_OFF_CARD (1 << 14)
	Can power off after boot.
#define	MMC_CAP_BUS_WIDTH_TEST (1 << 15)
	CMD14/CMD19 bus width ok.
#define	MMC_CAP_UHS_SDR12 (1 << 16)
	Host supports UHS SDR12 mode.
#define	MMC_CAP_UHS_SDR25 (1 << 17)
	Host supports UHS SDR25 mode.
#define	MMC_CAP_UHS_SDR50 (1 << 18)
	Host supports UHS SDR50 mode.
#define	MMC_CAP_UHS_SDR104 (1 << 19)
	Host supports UHS SDR104 mode.
#define	MMC_CAP_UHS_DDR50 (1 << 20)
	Host supports UHS DDR50 mode.
#define	MMC_CAP_UHS (MMC_CAP_UHS_SDR12 \| MMC_CAP_UHS_SDR25 \| MMC_CAP_UHS_SDR50 \| MMC_CAP_UHS_SDR104 \| MMC_CAP_UHS_DDR50)
#define	MMC_CAP_SYNC_RUNTIME_PM (1 << 21)
	Synced runtime PM suspends.
#define	MMC_CAP_NEED_RSP_BUSY (1 << 22)
	Commands with R1B can't use R1.
#define	MMC_CAP_DRIVER_TYPE_A (1 << 23)
	Host supports Driver Type A.
#define	MMC_CAP_DRIVER_TYPE_C (1 << 24)
	Host supports Driver Type C.
#define	MMC_CAP_DRIVER_TYPE_D (1 << 25)
	Host supports Driver Type D.
#define	MMC_CAP_DONE_COMPLETE (1 << 27)
	RW reqs can be completed within mmc_request_done().
#define	MMC_CAP_CD_WAKE (1 << 28)
	Enable card detect wake.
#define	MMC_CAP_CMD_DURING_TFR (1 << 29)
	Commands during data transfer.
#define	MMC_CAP_CMD23 (1 << 30)
	CMD23 supported.
#define	MMC_CAP_HW_RESET (1 << 31)
	Reset the eMMC card via RST_n.
#define	MMC_CAP2_BOOTPART_NOACC (1 << 0)
	Boot partition no access.
#define	MMC_CAP2_FULL_PWR_CYCLE (1 << 2)
	Can do full power cycle.
#define	MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3)
	Can do full power cycle in suspend.
#define	MMC_CAP2_HS200_1_8V_SDR (1 << 5)
	Can support HS200 1.8V.
#define	MMC_CAP2_HS200_1_2V_SDR (1 << 6)
	Can support HS200 1.2V.
#define	MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR \| MMC_CAP2_HS200_1_2V_SDR)
#define	MMC_CAP2_CD_ACTIVE_HIGH (1 << 10)
	Card-detect signal active high.
#define	MMC_CAP2_RO_ACTIVE_HIGH (1 << 11)
	Write-protect signal active high.
#define	MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14)
	Don't power up before scan.
#define	MMC_CAP2_HS400_1_8V (1 << 15)
	Can support HS400 1.8V.
#define	MMC_CAP2_HS400_1_2V (1 << 16)
	Can support HS400 1.2V.
#define	MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V \| MMC_CAP2_HS400_1_2V)
#define	MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR \| MMC_CAP2_HS400_1_8V)
#define	MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR \| MMC_CAP2_HS400_1_2V)
#define	MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
	Don't create a thread to poll for SDIO IRQ.
#define	MMC_CAP2_NO_WRITE_PROTECT (1 << 18)
	No physical write protect pin, assume that card is always read-write.
#define	MMC_CAP2_NO_SDIO (1 << 19)
	Do not send SDIO commands during initialization.
#define	MMC_CAP2_HS400_ES (1 << 20)
	Host supports enhanced strobe.
#define	MMC_CAP2_NO_SD (1 << 21)
	Do not send SD commands during initialization.
#define	MMC_CAP2_NO_MMC (1 << 22)
	Do not send = (e)MMC commands during initialization.
#define	MMC_CAP2_CQE (1 << 23)
	Has eMMC command queue engine.
#define	MMC_CAP2_CQE_DCMD (1 << 24)
	CQE can issue a direct command.
#define	MMC_CAP2_AVOID_3_3V (1 << 25)
	Host must negotiate down from 3.3V.
#define	MMC_CAP2_MERGE_CAPABLE (1 << 26)
	Host can merge a segment over the segment size.
#define	MMC_DATA_READ 1
#define	MMC_DATA_WRITE 2
#define	MMC_BUS_WIDTH_1 0
#define	MMC_BUS_WIDTH_4 2
#define	MMC_BUS_WIDTH_8 3
#define	MMC_BUS_SPEED_DEFAULT 0
#define	MMC_BUS_SPEED_HS26 26000000
#define	MMC_BUS_SPEED_HS52 52000000
#define	MMC_BUS_SPEED_DDR 52000000
#define	MMC_BUS_SPEED_HS200 200000000
#define	MMC_TIMING_LEGACY 0
#define	MMC_TIMING_MMC_HS 1
#define	MMC_TIMING_SD_HS 2
#define	MMC_TIMING_UHS_SDR12 3
#define	MMC_TIMING_UHS_SDR25 4
#define	MMC_TIMING_UHS_SDR50 5
#define	MMC_TIMING_UHS_SDR104 6
#define	MMC_TIMING_UHS_DDR50 7
#define	MMC_TIMING_MMC_DDR52 8
#define	MMC_TIMING_MMC_HS200 9
#define	MMC_TIMING_MMC_HS400 10
#define	MMC_SIGNAL_VOLTAGE_330 0
#define	MMC_SIGNAL_VOLTAGE_180 1
#define	MMC_SIGNAL_VOLTAGE_120 2
#define	MMC_SET_DRIVER_TYPE_B 0
#define	MMC_SET_DRIVER_TYPE_A 1
#define	MMC_SET_DRIVER_TYPE_C 2
#define	MMC_SET_DRIVER_TYPE_D 3
#define	MMC_CMD_GO_IDLE_STATE 0
#define	MMC_CMD_SEND_OP_COND 1
#define	MMC_CMD_ALL_SEND_CID 2
#define	MMC_CMD_SET_RELATIVE_ADDR 3
#define	MMC_CMD_SET_DSR 4
#define	MMC_CMD_SLEEP_AWAKE 5
#define	MMC_CMD_SWITCH 6
#define	MMC_CMD_SELECT_CARD 7
#define	MMC_CMD_SEND_EXT_CSD 8
#define	MMC_CMD_SEND_CSD 9
#define	MMC_CMD_SEND_CID 10
#define	MMC_CMD_READ_DAT_UNTIL_STOP 11
#define	MMC_CMD_STOP_TRANSMISSION 12
#define	MMC_CMD_SEND_STATUS 13
#define	MMC_CMD_BUS_TEST_R 14
#define	MMC_CMD_GO_INACTIVE_STATE 15
#define	MMC_CMD_BUS_TEST_W 19
#define	MMC_CMD_SPI_READ_OCR 58
#define	MMC_CMD_SPI_CRC_ON_OFF 59
#define	MMC_CMD_SET_BLOCKLEN 16
#define	MMC_CMD_READ_SINGLE_BLOCK 17
#define	MMC_CMD_READ_MULTIPLE_BLOCK 18
#define	MMC_CMD_SEND_TUNING_BLOCK 19
#define	MMC_CMD_SEND_TUNING_BLOCK_HS200 21
#define	MMC_CMD_WRITE_DAT_UNTIL_STOP 20
#define	MMC_CMD_SET_BLOCK_COUNT 23
#define	MMC_CMD_WRITE_SINGLE_BLOCK 24
#define	MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define	MMC_CMD_PROGRAM_CID 26
#define	MMC_CMD_PROGRAM_CSD 27
#define	MMC_CMD_SET_WRITE_PROT 28
#define	MMC_CMD_CLR_WRITE_PROT 29
#define	MMC_CMD_SEND_WRITE_PROT 30
#define	MMC_CMD_ERASE_GROUP_START 35
#define	MMC_CMD_ERASE_GROUP_END 36
#define	MMC_CMD_ERASE 38
#define	MMC_CMD_FAST_IO 39
#define	MMC_CMD_GO_IRQ_STATE 40
#define	MMC_CMD_LOCK_UNLOCK 42
#define	MMC_CMD_APP_CMD 55
#define	MMC_CMD_GEN_CMD 56
#define	MMC_CMD_RES_MAN 62
#define	MMC_CMD62_ARG1 0xEFAC62EC
#define	MMC_CMD62_ARG2 0x00CBAEA7
#define	MMC_RSP_PRESENT (1 << 0)
#define	MMC_RSP_136 (1 << 1)
	136 bit response
#define	MMC_RSP_CRC (1 << 2)
	Expect valid crc.
#define	MMC_RSP_BUSY (1 << 3)
	Card may send busy.
#define	MMC_RSP_OPCODE (1 << 4)
	Response contains opcode.
#define	MMC_RSP_NONE (0)
#define	MMC_RSP_R1 (MMC_RSP_PRESENT \| MMC_RSP_CRC \| MMC_RSP_OPCODE)
#define	MMC_RSP_R1B (MMC_RSP_PRESENT \| MMC_RSP_CRC \| MMC_RSP_OPCODE \| MMC_RSP_BUSY)
#define	MMC_RSP_R2 (MMC_RSP_PRESENT \| MMC_RSP_136 \| MMC_RSP_CRC)
#define	MMC_RSP_R3 (MMC_RSP_PRESENT)
#define	MMC_RSP_R4 (MMC_RSP_PRESENT)
#define	MMC_RSP_R5 (MMC_RSP_PRESENT \| MMC_RSP_CRC \| MMC_RSP_OPCODE)
#define	MMC_RSP_R6 (MMC_RSP_PRESENT \| MMC_RSP_CRC \| MMC_RSP_OPCODE)
#define	MMC_RSP_R7 (MMC_RSP_PRESENT \| MMC_RSP_CRC \| MMC_RSP_OPCODE)
#define	MMC_CMD_MASK (3 << 5)
#define	MMC_CMD_AC (0 << 5)
	Addressed Command, no Data.
#define	MMC_CMD_ADTC (1 << 5)
	Addressed Data Transfer Command.
#define	MMC_CMD_BC (2 << 5)
	Broadcast Command, no Response.
#define	MMC_CMD_BCR (3 << 5)
	Broadcast Command with Response.
#define	MMC_RSP_SPI_S1 (1 << 7)
	One status byte.
#define	MMC_RSP_SPI_S2 (1 << 8)
	Second byte.
#define	MMC_RSP_SPI_B4 (1 << 9)
	Four data bytes.
#define	MMC_RSP_SPI_BUSY (1 << 10)
	Card may send busy.
#define	MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
#define	MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_BUSY)
#define	MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_S2)
#define	MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_B4)
#define	MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_B4)
#define	MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_S2)
#define	MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1 \| MMC_RSP_SPI_B4)
#define	MMC_RSP_R1_OUT_OF_RANGE (1 << 31)
#define	MMC_RSP_R1_ADDRESS_ERROR (1 << 30)
#define	MMC_RSP_R1_BLOCK_LEN_ERROR (1 << 29)
#define	MMC_RSP_R1_ERASE_SEQ_ERROR (1 << 28)
#define	MMC_RSP_R1_ERASE_PARAM (1 << 27)
#define	MMC_RSP_R1_WP_VIOLATION (1 << 26)
#define	MMC_RSP_R1_CARD_IS_LOCKED (1 << 25)
#define	MMC_RSP_R1_LOCK_UNLOCK_FAILED (1 << 24)
#define	MMC_RSP_R1_COM_CRC_ERROR (1 << 23)
#define	MMC_RSP_R1_ILLEGAL_COMMAND (1 << 22)
#define	MMC_RSP_R1_CARD_ECC_FAILED (1 << 21)
#define	MMC_RSP_R1_CC_ERROR (1 << 20)
#define	MMC_RSP_R1_ERROR (1 << 19)
#define	MMC_RSP_R1_UNDERRUN (1 << 18)
#define	MMC_RSP_R1_OVERRUN (1 << 17)
#define	MMC_RSP_R1_CID_CSD_OVERWRITE (1 << 16)
#define	MMC_RSP_R1_WP_ERASE_SKIP (1 << 15)
#define	MMC_RSP_R1_CARD_ECC_DISABLED (1 << 14)
#define	MMC_RSP_R1_ERASE_RESET (1 << 13)
#define	MMC_RSP_R1_READY_FOR_DATA (1 << 8)
#define	MMC_RSP_R1_SWITCH_ERROR (1 << 7)
#define	MMC_RSP_R1_EXCEPTION_EVENT (1 << 6)
#define	MMC_RSP_R1_APP_CMD (1 << 5)
#define	MMC_RSP_R1_AKE_SEQ_ERROR (1 << 3)
#define	MMC_RSP_R1_SPI_IDLE (1 << 0)
#define	MMC_RSP_R1_SPI_ERASE_RESET (1 << 1)
#define	MMC_RSP_R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define	MMC_RSP_R1_SPI_COM_CRC (1 << 3)
#define	MMC_RSP_R1_SPI_ERASE_SEQ (1 << 4)
#define	MMC_RSP_R1_SPI_ADDRESS (1 << 5)
#define	MMC_RSP_R1_SPI_PARAMETER (1 << 6)
#define	MMC_RSP_R2_SPI_CARD_LOCKED (1 << 8)
#define	MMC_RSP_R2_SPI_WP_ERASE_SKIP (1 << 9)
	Or lock/unlock fail.
#define	MMC_RSP_R2_SPI_LOCK_UNLOCK_FAIL MMC_RSP_R2_SPI_WP_ERASE_SKIP
#define	MMC_RSP_R2_SPI_ERROR (1 << 10)
#define	MMC_RSP_R2_SPI_CC_ERROR (1 << 11)
#define	MMC_RSP_R2_SPI_CARD_ECC_ERROR (1 << 12)
#define	MMC_RSP_R2_SPI_WP_VIOLATION (1 << 13)
#define	MMC_RSP_R2_SPI_ERASE_PARAM (1 << 14)
#define	MMC_RSP_R2_SPI_OUT_OF_RANGE (1 << 15)
	Or CSD overwrite.
#define	MMC_RSP_R2_SPI_CSD_OVERWRITE MMC_RSP_R2_SPI_OUT_OF_RANGE
#define	MMC_OCR_BUSY 0x80000000
	Busy Status - 0 = Initializing / 1 = Initialization Complete.
#define	MMC_OCR_HCS 0x40000000
	Card Capacity Status - 0 = SDSC / 1 = SDHC or SDXC.
#define	MMC_OCR_UHS_II 0x20000000
	UHS-II Card Status - 0 = Non UHS-II Card / 1 = UHS-II Card.
#define	MMC_OCR_S18A 0x01000000
	Switching to 1.8V Accepted - 0 = Continue current voltage signaling / 1 = Ready for switching signal voltage.
#define	MMC_OCR_VOLTAGE_MASK 0x007FFF80
#define	MMC_OCR_ACCESS_MODE 0x60000000
#define	MMC_CARD_STATUS_MASK (~0x0206BF7F)
#define	MMC_CARD_STATUS_ERROR (1 << 19)
#define	MMC_CARD_STATUS_CURRENT_STATE (0x0F << 9)
	See MMC_CURRENT_STATE_ definitions below.
#define	MMC_CARD_STATUS_READY_FOR_DATA (1 << 8)
#define	MMC_CARD_STATUS_SWITCH_ERROR (1 << 7)
#define	MMC_CURRENT_STATE_IDLE (0 << 9)
#define	MMC_CURRENT_STATE_READY (1 << 9)
#define	MMC_CURRENT_STATE_IDENT (2 << 9)
#define	MMC_CURRENT_STATE_STBY (3 << 9)
#define	MMC_CURRENT_STATE_TRAN (4 << 9)
#define	MMC_CURRENT_STATE_DATA (5 << 9)
#define	MMC_CURRENT_STATE_RCV (6 << 9)
#define	MMC_CURRENT_STATE_PRG (7 << 9)
#define	MMC_CURRENT_STATE_DIS (8 << 9)
#define	MMC_CID_MID 1
	Manufacturer ID.
#define	MMC_CID_OID 2
	OEM/Application ID.
#define	MMC_CID_PNM0 3
	Product name (Byte 0).
#define	MMC_CID_PNM1 4
	Product name (Byte 1).
#define	MMC_CID_PNM2 5
	Product name (Byte 2).
#define	MMC_CID_PNM3 6
	Product name (Byte 3).
#define	MMC_CID_PNM4 7
	Product name (Byte 4).
#define	MMC_CID_PNM5 8
	Product name (Byte 5).
#define	MMC_CID_PNM6 9
	Product name (Byte 6).
#define	MMC_CID_PRV 10
	Product revision.
#define	MMC_CID_HRV 11
	Hardware revision.
#define	MMC_CID_FRV 12
	Firmware revision.
#define	MMC_CID_PSN 13
	Product serial number.
#define	MMC_CID_MDT_YEAR 14
	Manufacturing year.
#define	MMC_CID_MDT_MONTH 15
	Manufacturing month.
#define	MMC_CID_CRC 16
	CRC.
#define	MMC_CSD_STRUCTURE 1
#define	MMC_CSD_SPECVER 2
	MMC/eMMC Only.
#define	MMC_CSD_TAAC_UNIT 3
#define	MMC_CSD_TAAC_VALUE 4
#define	MMC_CSD_NSAC 5
#define	MMC_CSD_TRAN_SPEED_UNIT 6
#define	MMC_CSD_TRAN_SPEED_VALUE 37
#define	MMC_CSD_CCC 7
#define	MMC_CSD_READ_BL_LEN 8
#define	MMC_CSD_READ_BL_PARTIAL 9
#define	MMC_CSD_WRITE_BLK_MISALIGN 10
#define	MMC_CSD_READ_BLK_MISALIGN 11
#define	MMC_CSD_DSR_IMP 12
#define	MMC_CSD_C_SIZE 13
#define	MMC_CSD_VDD_R_CURR_MIN 14
#define	MMC_CSD_VDD_R_CURR_MAX 15
#define	MMC_CSD_VDD_W_CURR_MIN 16
#define	MMC_CSD_VDD_W_CURR_MAX 17
#define	MMC_CSD_C_SIZE_MULT 18
#define	MMC_CSD_ERASE_BLK_EN 19
	SD Specification.
#define	MMC_CSD_SECTOR_SIZE 20
	MMC/eMMC Specification / SD Specification.
#define	MMC_CSD_ERASE_GRP_SIZE 21
	MMC/eMMC Specification.
#define	MMC_CSD_ERASE_GRP_MULT 22
	MMC/eMMC Specification.
#define	MMC_CSD_WP_GRP_SIZE 23
#define	MMC_CSD_WP_GRP_ENABLE 24
#define	MMC_CSD_DEFAULT_ECC 25
	MMC/eMMC Only.
#define	MMC_CSD_R2W_FACTOR 26
#define	MMC_CSD_WRITE_BL_LEN 27
#define	MMC_CSD_WRITE_BL_PARTIAL 28
#define	MMC_CSD_CONTENT_PROT_APP 29
	MMC/eMMC Only.
#define	MMC_CSD_FILE_FORMAT_GRP 30
#define	MMC_CSD_COPY 31
#define	MMC_CSD_PERM_WRITE_PROTECT 32
#define	MMC_CSD_TMP_WRITE_PROTECT 33
#define	MMC_CSD_FILE_FORMAT 34
#define	MMC_CSD_ECC 35
	MMC/eMMC Only.
#define	MMC_CSD_CRC 36
#define	MMC_CSD_STRUCT_VER_1_0 0
	Valid for system specification 1.0 - 1.2.
#define	MMC_CSD_STRUCT_VER_1_1 1
	Valid for system specification 1.4 - 2.2.
#define	MMC_CSD_STRUCT_VER_1_2 2
	Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1.
#define	MMC_CSD_STRUCT_EXT_CSD 3
	Version is coded in CSD_STRUCTURE in EXT_CSD.
#define	MMC_CSD_SPEC_VER_0 0
	Implements system specification 1.0 - 1.2.
#define	MMC_CSD_SPEC_VER_1 1
	Implements system specification 1.4.
#define	MMC_CSD_SPEC_VER_2 2
	Implements system specification 2.0 - 2.2.
#define	MMC_CSD_SPEC_VER_3 3
	Implements system specification 3.1 - 3.2 - 3.31.
#define	MMC_CSD_SPEC_VER_4 4
	Implements system specification 4.0 - 4.1.
#define	MMC_CCC_BASIC (1 << 0)
	(Class 0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15) (and for SPI, CMD58,59)
#define	MMC_CCC_STREAM_READ (1 << 1)
	(Class 1) Stream read commands (CMD11)
#define	MMC_CCC_BLOCK_READ (1 << 2)
	(Class 2) Block read commands (CMD16,17,18)
#define	MMC_CCC_STREAM_WRITE (1 << 3)
	(Class 3) Stream write commands (CMD20)
#define	MMC_CCC_BLOCK_WRITE (1 << 4)
	(Class 4) Block write commands (CMD16,24,25,26,27)
#define	MMC_CCC_ERASE (1 << 5)
	(Class 5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39)
#define	MMC_CCC_WRITE_PROT (1 << 6)
	(Class 6) Ability to write protect blocks (CMD28,29,30)
#define	MMC_CCC_LOCK_CARD (1 << 7)
	(Class 7) Ability to lock down card (CMD16,CMD42)
#define	MMC_CCC_APP_SPEC (1 << 8)
	(Class 8) Application specific (CMD55,56,57,ACMD*)
#define	MMC_CCC_IO_MODE (1 << 9)
	(Class 9) I/O mode (CMD5,39,40,52,53)
#define	MMC_CCC_SWITCH (1 << 10)
	(Class 10) High speed switch (CMD6,34,35,36,37,50)
#define	MMC_CCC_EXTENSION (1 << 11)
	(Class 11) Extension (CMD?)
#define	SECURE_ERASE 0x80000000
#define	MMC_VDD_165_195 0x00000080
	VDD voltage 1.65 - 1.95.
#define	MMC_VDD_20_21 0x00000100
	VDD voltage 2.0 ~ 2.1.
#define	MMC_VDD_21_22 0x00000200
	VDD voltage 2.1 ~ 2.2.
#define	MMC_VDD_22_23 0x00000400
	VDD voltage 2.2 ~ 2.3.
#define	MMC_VDD_23_24 0x00000800
	VDD voltage 2.3 ~ 2.4.
#define	MMC_VDD_24_25 0x00001000
	VDD voltage 2.4 ~ 2.5.
#define	MMC_VDD_25_26 0x00002000
	VDD voltage 2.5 ~ 2.6.
#define	MMC_VDD_26_27 0x00004000
	VDD voltage 2.6 ~ 2.7.
#define	MMC_VDD_27_28 0x00008000
	VDD voltage 2.7 ~ 2.8.
#define	MMC_VDD_28_29 0x00010000
	VDD voltage 2.8 ~ 2.9.
#define	MMC_VDD_29_30 0x00020000
	VDD voltage 2.9 ~ 3.0.
#define	MMC_VDD_30_31 0x00040000
	VDD voltage 3.0 ~ 3.1.
#define	MMC_VDD_31_32 0x00080000
	VDD voltage 3.1 ~ 3.2.
#define	MMC_VDD_32_33 0x00100000
	VDD voltage 3.2 ~ 3.3.
#define	MMC_VDD_33_34 0x00200000
	VDD voltage 3.3 ~ 3.4.
#define	MMC_VDD_34_35 0x00400000
	VDD voltage 3.4 ~ 3.5.
#define	MMC_VDD_35_36 0x00800000
	VDD voltage 3.5 ~ 3.6.
#define	MMC_SWITCH_MODE_CMD_SET 0x00
	Change the command set.
#define	MMC_SWITCH_MODE_SET_BITS 0x01
	Set bits in EXT_CSD byte addressed by index which are 1 in value field.
#define	MMC_SWITCH_MODE_CLEAR_BITS 0x02
	Clear bits in EXT_CSD byte addressed by index, which are 1 in value field.
#define	MMC_SWITCH_MODE_WRITE_BYTE 0x03
	Set target byte to value.
#define	EXT_CSD_CMDQ_MODE_EN 15
	R/W.
#define	EXT_CSD_FLUSH_CACHE 32
	W.
#define	EXT_CSD_CACHE_CTRL 33
	R/W.
#define	EXT_CSD_POWER_OFF_NOTIFICATION 34
	R/W.
#define	EXT_CSD_PACKED_FAILURE_INDEX 35
	RO.
#define	EXT_CSD_PACKED_CMD_STATUS 36
	RO.
#define	EXT_CSD_EXP_EVENTS_STATUS 54
	RO, 2 bytes.
#define	EXT_CSD_EXP_EVENTS_CTRL 56
	R/W, 2 bytes.
#define	EXT_CSD_DATA_SECTOR_SIZE 61
	R.
#define	EXT_CSD_ENH_START_ADDR 136
	R/W.
#define	EXT_CSD_ENH_SIZE_MULT 140
	R/W.
#define	EXT_CSD_GP_SIZE_MULT 143
	R/W.
#define	EXT_CSD_PARTITION_SETTING_COMPLETED 155
	R/W.
#define	EXT_CSD_PARTITION_ATTRIBUTE 156
	R/W.
#define	EXT_CSD_MAX_ENH_SIZE_MULT 157
	R.
#define	EXT_CSD_PARTITION_SUPPORT 160
	RO.
#define	EXT_CSD_HPI_MGMT 161
	R/W.
#define	EXT_CSD_RST_N_FUNCTION 162
	R/W.
#define	EXT_CSD_BKOPS_EN 163
	R/W.
#define	EXT_CSD_BKOPS_START 164
	W.
#define	EXT_CSD_SANITIZE_START 165
	W.
#define	EXT_CSD_WR_REL_PARAM 166
	RO.
#define	EXT_CSD_WR_REL_SET 167
	R/W.
#define	EXT_CSD_RPMB_MULT 168
	RO.
#define	EXT_CSD_FW_CONFIG 169
	R/W.
#define	EXT_CSD_BOOT_WP 173
	R/W.
#define	EXT_CSD_ERASE_GROUP_DEF 175
	R/W.
#define	EXT_CSD_BOOT_BUS_CONDITIONS 177
	R/W/E.
#define	EXT_CSD_PART_CONFIG 179
	R/W.
#define	EXT_CSD_ERASED_MEM_CONT 181
	RO.
#define	EXT_CSD_BUS_WIDTH 183
	R/W.
#define	EXT_CSD_STROBE_SUPPORT 184
	RO.
#define	EXT_CSD_HS_TIMING 185
	R/W.
#define	EXT_CSD_POWER_CLASS 187
	R/W.
#define	EXT_CSD_REV 192
	RO.
#define	EXT_CSD_STRUCTURE 194
	RO.
#define	EXT_CSD_CARD_TYPE 196
	RO.
#define	EXT_CSD_DRIVER_STRENGTH 197
	RO.
#define	EXT_CSD_OUT_OF_INTERRUPT_TIME 198
	RO.
#define	EXT_CSD_PART_SWITCH_TIME 199
	RO.
#define	EXT_CSD_PWR_CL_52_195 200
	RO.
#define	EXT_CSD_PWR_CL_26_195 201
	RO.
#define	EXT_CSD_PWR_CL_52_360 202
	RO.
#define	EXT_CSD_PWR_CL_26_360 203
	RO.
#define	EXT_CSD_SEC_CNT 212
	RO, 4 bytes.
#define	EXT_CSD_S_A_TIMEOUT 217
	RO.
#define	EXT_CSD_REL_WR_SEC_C 222
	RO.
#define	EXT_CSD_HC_WP_GRP_SIZE 221
	RO.
#define	EXT_CSD_ERASE_TIMEOUT_MULT 223
	RO.
#define	EXT_CSD_HC_ERASE_GRP_SIZE 224
	RO.
#define	EXT_CSD_BOOT_SIZE_MULT 226
	RO.
#define	EXT_CSD_SEC_TRIM_MULT 229
	RO.
#define	EXT_CSD_SEC_ERASE_MULT 230
	RO.
#define	EXT_CSD_SEC_FEATURE_SUPPORT 231
	RO.
#define	EXT_CSD_TRIM_MULT 232
	RO.
#define	EXT_CSD_PWR_CL_200_195 236
	RO.
#define	EXT_CSD_PWR_CL_200_360 237
	RO.
#define	EXT_CSD_PWR_CL_DDR_52_195 238
	RO.
#define	EXT_CSD_PWR_CL_DDR_52_360 239
	RO.
#define	EXT_CSD_BKOPS_STATUS 246
	RO.
#define	EXT_CSD_POWER_OFF_LONG_TIME 247
	RO.
#define	EXT_CSD_GENERIC_CMD6_TIME 248
	RO.
#define	EXT_CSD_CACHE_SIZE 249
	RO, 4 bytes.
#define	EXT_CSD_PWR_CL_DDR_200_360 253
	RO.
#define	EXT_CSD_FIRMWARE_VERSION 254
	RO, 8 bytes.
#define	EXT_CSD_PRE_EOL_INFO 267
	RO.
#define	EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268
	RO.
#define	EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269
	RO.
#define	EXT_CSD_CMDQ_DEPTH 307
	RO.
#define	EXT_CSD_CMDQ_SUPPORT 308
	RO.
#define	EXT_CSD_SUPPORTED_MODE 493
	RO.
#define	EXT_CSD_TAG_UNIT_SIZE 498
	RO.
#define	EXT_CSD_DATA_TAG_SUPPORT 499
	RO.
#define	EXT_CSD_MAX_PACKED_WRITES 500
	RO.
#define	EXT_CSD_MAX_PACKED_READS 501
	RO.
#define	EXT_CSD_BKOPS_SUPPORT 502
	RO.
#define	EXT_CSD_HPI_FEATURES 503
	RO.
#define	EXT_CSD_PARTITION_ATTRIBUTE_ENH_4 0x10
#define	EXT_CSD_PARTITION_ATTRIBUTE_ENH_3 0x08
#define	EXT_CSD_PARTITION_ATTRIBUTE_ENH_2 0x04
#define	EXT_CSD_PARTITION_ATTRIBUTE_ENH_1 0x02
#define	EXT_CSD_PARTITION_ATTRIBUTE_ENH_USR 0x01
#define	EXT_CSD_PARTITION_EXT_ATTRIBUTE_EN 0x04
#define	EXT_CSD_PARTITION_ENH_ATTRIBUTE_EN 0x02
#define	EXT_CSD_PARTITION_PARTITIONING_EN 0x01
#define	EXT_CSD_WR_REL_PARAM_EN (1 << 2)
#define	EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1 << 4)
#define	EXT_CSD_BOOT_WP_B_PWR_WP_DIS 0x40
#define	EXT_CSD_BOOT_WP_B_PERM_WP_DIS 0x10
#define	EXT_CSD_BOOT_WP_B_PERM_WP_EN 0x04
#define	EXT_CSD_BOOT_WP_B_PWR_WP_EN 0x01
#define	EXT_CSD_PART_CONFIG_ACC_MASK 0x07
#define	EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01
#define	EXT_CSD_PART_CONFIG_ACC_RPMB 0x03
#define	EXT_CSD_PART_CONFIG_ACC_GP0 0x04
#define	EXT_CSD_PART_SETTING_COMPLETED 0x01
#define	EXT_CSD_PART_SUPPORT_PART_EN 0x01
#define	EXT_CSD_CMD_SET_NORMAL (1 << 0)
#define	EXT_CSD_CMD_SET_SECURE (1 << 1)
#define	EXT_CSD_CMD_SET_CPSECURE (1 << 2)
#define	EXT_CSD_CARD_TYPE_HS_26 (1 << 0)
	Card can run at 26MHz.
#define	EXT_CSD_CARD_TYPE_HS_52 (1 << 1)
	Card can run at 52MHz.
#define	EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 \| EXT_CSD_CARD_TYPE_HS_52)
#define	EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
	Card can run at 52MHz / DDR mode @1.8V or 3V I/O.
#define	EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
	Card can run at 52MHz / DDR mode @1.2V I/O.
#define	EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define	EXT_CSD_CARD_TYPE_HS200_1_8V (1 << 4)
	Card can run at 200MHz.
#define	EXT_CSD_CARD_TYPE_HS200_1_2V (1 << 5)
	Card can run at 200MHz / SDR mode @1.2V I/O.
#define	EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V \| EXT_CSD_CARD_TYPE_HS200_1_2V)
#define	EXT_CSD_CARD_TYPE_HS400_1_8V (1 << 6)
	Card can run at 200MHz DDR, 1.8V.
#define	EXT_CSD_CARD_TYPE_HS400_1_2V (1 << 7)
	Card can run at 200MHz DDR, 1.2V.
#define	EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V \| EXT_CSD_CARD_TYPE_HS400_1_2V)
#define	EXT_CSD_CARD_TYPE_HS400ES (1 << 8)
	Card can run at HS400ES.
#define	EXT_CSD_BUS_WIDTH_1 0
	Card is in 1 bit mode.
#define	EXT_CSD_BUS_WIDTH_4 1
	Card is in 4 bit mode.
#define	EXT_CSD_BUS_WIDTH_8 2
	Card is in 8 bit mode.
#define	EXT_CSD_DDR_BUS_WIDTH_4 5
	Card is in 4 bit DDR mode.
#define	EXT_CSD_DDR_BUS_WIDTH_8 6
	Card is in 8 bit DDR mode.
#define	EXT_CSD_BUS_WIDTH_STROBE 1 << 7
	Enhanced strobe mode.
#define	EXT_CSD_TIMING_BC 0
	Backwards compatility.
#define	EXT_CSD_TIMING_HS 1
	High speed.
#define	EXT_CSD_TIMING_HS200 2
	HS200.
#define	EXT_CSD_TIMING_HS400 3
	HS400.
#define	EXT_CSD_DRV_STR_SHIFT 4
	Driver Strength shift.
#define	EXT_CSD_SEC_ER_EN 1 << 0
#define	EXT_CSD_SEC_BD_BLK_EN 1 << 2
#define	EXT_CSD_SEC_GB_CL_EN 1 << 4
#define	EXT_CSD_SEC_SANITIZE 1 << 6
	v4.5 only
#define	EXT_CSD_RST_N_EN_MASK 0x03
#define	EXT_CSD_RST_N_ENABLED 1
	RST_n is enabled on card.
#define	EXT_CSD_NO_POWER_NOTIFICATION 0
#define	EXT_CSD_POWER_ON 1
#define	EXT_CSD_POWER_OFF_SHORT 2
#define	EXT_CSD_POWER_OFF_LONG 3
#define	EXT_CSD_PWR_CL_8BIT_MASK 0xF0
	8 bit PWR CLS
#define	EXT_CSD_PWR_CL_4BIT_MASK 0x0F
	8 bit PWR CLS
#define	EXT_CSD_PWR_CL_8BIT_SHIFT 4
#define	EXT_CSD_PWR_CL_4BIT_SHIFT 0
#define	EXT_CSD_PACKED_EVENT_EN 1 << 3
#define	EXT_CSD_URGENT_BKOPS 1 << 0
#define	EXT_CSD_DYNCAP_NEEDED 1 << 1
#define	EXT_CSD_SYSPOOL_EXHAUSTED 1 << 2
#define	EXT_CSD_PACKED_FAILURE 1 << 3
#define	EXT_CSD_PACKED_GENERIC_ERROR 1 << 0
#define	EXT_CSD_PACKED_INDEXED_ERROR 1 << 1
#define	EXT_CSD_BKOPS_LEVEL_2 0x02
#define	EXT_CSD_MANUAL_BKOPS_MASK 0x01
#define	EXT_CSD_AUTO_BKOPS_MASK 0x02
#define	EXT_CSD_CMDQ_MODE_ENABLED 1 << 0
#define	EXT_CSD_CMDQ_DEPTH_MASK 0x1F
#define	EXT_CSD_CMDQ_SUPPORTED 1 << 0
#define	MMC_HIGH_26_MAX_DTR 26000000
#define	MMC_HIGH_52_MAX_DTR 52000000
#define	MMC_HIGH_DDR_MAX_DTR 52000000
#define	MMC_HS200_MAX_DTR 200000000
#define	MMC_MIN_PART_SWITCH_TIME 300
	Milliseconds.
#define	MMCPART_NOAVAILABLE (0xff)
#define	PART_ACCESS_MASK (0x07)
#define	PART_SUPPORT (0x01)
#define	ENHNCD_SUPPORT (0x02)
#define	PART_ENH_ATTRIB (0x1f)
#define	MMC_MAX_BLOCK_LEN 512
#define	MMC_MAX_BLOCK_COUNT 65535
#define	MMC_NUM_BOOT_PARTITION 2
#define	MMC_NUM_GP_PARTITION 4
#define	MMC_NUM_PHY_PARTITION 7
#define	MMC_DEFAULT_CMD6_TIMEOUT_MS 500
#define	MMC_MIN_CACHE_EN_TIMEOUT_MS 1600
#define	MMC_FIRMWARE_VERSION_LEN 8
#define	MMC_DISCARD_FEATURE 0x01
#define	MMC_BUSY_CMD6 0
#define	MMC_BUSY_ERASE 1
#define	MMC_BUSY_HPI 2
#define	MMC_ERASE_ARG 0x00000000
#define	MMC_SECURE_ERASE_ARG 0x80000000
#define	MMC_TRIM_ARG 0x00000001
#define	MMC_DISCARD_ARG 0x00000003
#define	MMC_SECURE_TRIM1_ARG 0x80000001
#define	MMC_SECURE_TRIM2_ARG 0x80008000
#define	MMC_SECURE_ARGS 0x80000000
#define	MMC_TRIM_ARGS 0x00008001
#define	SD_DEFAULT_BLOCKSIZE 512
#define	SD_DEFAULT_BLOCKSHIFT 9
#define	SD_BUS_WIDTH_1 0
#define	SD_BUS_WIDTH_4 2
#define	SD_BUS_SPEED_DEFAULT 25000000
#define	SD_BUS_SPEED_HS 50000000
#define	SD_BUS_SPEED_UHS_SDR12 25000000
#define	SD_BUS_SPEED_UHS_SDR25 50000000
#define	SD_BUS_SPEED_UHS_DDR50 50000000
#define	SD_BUS_SPEED_UHS_SDR50 100000000
#define	SD_BUS_SPEED_UHS_SDR104 208000000
#define	SD_CMD_SEND_RELATIVE_ADDR 3
#define	SD_CMD_SEND_IF_COND 8
#define	SD_CMD_SWITCH_VOLTAGE 11
#define	SD_CMD_SWITCH 6
	See: 4.3.10 Switch Function Command.
#define	SD_CMD_ERASE_WR_BLK_START 32
#define	SD_CMD_ERASE_WR_BLK_END 33
#define	SD_CMD_APP_SET_BUS_WIDTH 6
#define	SD_CMD_APP_SD_STATUS 13
#define	SD_CMD_APP_SEND_NUM_WR_BLKS 22
#define	SD_CMD_APP_SEND_OP_COND 41
#define	SD_CMD_APP_SEND_SCR 51
#define	SD_SWITCH_MODE_CHECK 0
#define	SD_SWITCH_MODE_SWITCH 1
#define	SD_SWITCH_FUNCTION_GROUP_ACCESS 0
	Access Mode.
#define	SD_SWITCH_FUNCTION_GROUP_COMMAND 1
	Command System.
#define	SD_SWITCH_FUNCTION_GROUP_DRIVER 2
	Driver Strength.
#define	SD_SWITCH_FUNCTION_GROUP_POWER 3
	Power Limit.
#define	SD_SWITCH_ACCESS_MODE_DEF 0
	Default SDR12.
#define	SD_SWITCH_ACCESS_MODE_HS 1
	High Speed SDR25.
#define	SD_SWITCH_ACCESS_MODE_SDR50 2
	SDR50 (1.8V only).
#define	SD_SWITCH_ACCESS_MODE_SDR104 3
	SDR104 (1.8V only).
#define	SD_SWITCH_ACCESS_MODE_DDR50 4
	DDR50 (1.8V only).
#define	SD_SWITCH_COMMAND_SYSTEM_DEF 0
	Default.
#define	SD_SWITCH_COMMAND_SYSTEM_EC 1
	For eC.
#define	SD_SWITCH_COMMAND_SYSTEM_OTP 3
	OTP.
#define	SD_SWITCH_COMMAND_SYSTEM_ASSD 4
	ASSD.
#define	SD_SWITCH_DRIVER_STRENGTH_DEF 0
	Default Type B.
#define	SD_SWITCH_DRIVER_STRENGTH_TYPE_A 1
	Type A.
#define	SD_SWITCH_DRIVER_STRENGTH_TYPE_C 2
	Type C.
#define	SD_SWITCH_DRIVER_STRENGTH_TYPE_D 3
	Type D.
#define	SD_SWITCH_POWER_LIMIT_DEF 0
	Default 0.72W.
#define	SD_SWITCH_POWER_LIMIT_144 1
	1.44W
#define	SD_SWITCH_POWER_LIMIT_216 2
	2.16W (Embedded only)
#define	SD_SWITCH_POWER_LIMIT_288 3
	2.88W (Embedded only)
#define	SD_SWITCH_POWER_LIMIT_180 4
	1.80W
#define	SD_SEND_IF_COND_CHECK_PATTERN 0xAA
#define	SD_SEND_IF_COND_VOLTAGE_MASK 0x00FF8000
	MMC_VDD_27_28, MMC_VDD_28_29, MMC_VDD_29_30, MMC_VDD_30_31, MMC_VDD_31_32, MMC_VDD_32_33, MMC_VDD_33_34, MMC_VDD_34_35, MMC_VDD_35_36.
#define	SD_SEND_OP_COND_VOLTAGE_MASK 0x00FF8000
	MMC_VDD_27_28, MMC_VDD_28_29, MMC_VDD_29_30, MMC_VDD_30_31, MMC_VDD_31_32, MMC_VDD_32_33, MMC_VDD_33_34, MMC_VDD_34_35, MMC_VDD_35_36.
#define	SD_OCR_CCS 0x40000000
	Card Capacity Status - 0 = SDSC / 1 = SDHC or SDXC.
#define	SD_OCR_UHS_II 0x20000000
	UHS-II Card Status - 0 = Non UHS-II Card / 1 = UHS-II Card.
#define	SD_OCR_XPC 0x10000000
	SDXC Power Control.
#define	SD_OCR_S18A 0x01000000
	1.8V Switching Accepted
#define	SD_CSD_STRUCT_VER_1_0 0
	Standard Capacity.
#define	SD_CSD_STRUCT_VER_2_0 1
	High Capacity and Extended Capacity.
#define	SD_SSR_DAT_BUS_WIDTH 1
#define	SD_SSR_SECURED_MODE 2
#define	SD_SSR_SD_CARD_TYPE 3
#define	SD_SSR_SIZE_OF_PROTECTED_AREA 4
#define	SD_SSR_SPEED_CLASS 5
#define	SD_SSR_PERFORMANCE_MOVE 6
#define	SD_SSR_AU_SIZE 7
#define	SD_SSR_ERASE_SIZE 8
#define	SD_SSR_ERASE_TIMEOUT 9
#define	SD_SSR_ERASE_OFFSET 10
#define	SD_SSR_UHS_SPEED_GRADE 11
#define	SD_SSR_UHS_AU_SIZE 12
#define	SD_SSR_BUS_WIDTH_1 0
	1 (default)
#define	SD_SSR_BUS_WIDTH_4 2
	4 bit width
#define	SD_SSR_CARD_TYPE_RW 0x0000
	Regular SD RD/WR Card.
#define	SD_SSR_CARD_TYPE_ROM 0x0001
	SD ROM Card.
#define	SD_SSR_CARD_TYPE_OTP 0x0002
	OTP.
#define	SD_SSR_SPEED_CLASS_0 0x00
	Class 0.
#define	SD_SSR_SPEED_CLASS_2 0x01
	Class 2.
#define	SD_SSR_SPEED_CLASS_4 0x02
	Class 4.
#define	SD_SSR_SPEED_CLASS_6 0x03
	Class 6.
#define	SD_SSR_SPEED_CLASS_10 0x04
	Class 10.
#define	SD_SSR_UHS_SPEED_GRADE_0 0
	Less than 10MB/sec.
#define	SD_SSR_UHS_SPEED_GRADE_1 1
	10MB/sec and above
#define	SD_SWITCH_MAXIMUM_CURRENT 1
#define	SD_SWITCH_GROUP6_SUPPORT 2
#define	SD_SWITCH_GROUP5_SUPPORT 3
#define	SD_SWITCH_GROUP4_SUPPORT 4
#define	SD_SWITCH_GROUP3_SUPPORT 5
#define	SD_SWITCH_GROUP2_SUPPORT 6
#define	SD_SWITCH_GROUP1_SUPPORT 7
#define	SD_SWITCH_GROUP6_SELECTION 8
#define	SD_SWITCH_GROUP5_SELECTION 9
#define	SD_SWITCH_GROUP4_SELECTION 10
#define	SD_SWITCH_GROUP3_SELECTION 11
#define	SD_SWITCH_GROUP2_SELECTION 12
#define	SD_SWITCH_GROUP1_SELECTION 13
#define	SD_SWITCH_STRUCT_VERSION 14
#define	SD_SWITCH_GROUP6_BUSY_STATUS 15
#define	SD_SWITCH_GROUP5_BUSY_STATUS 16
#define	SD_SWITCH_GROUP4_BUSY_STATUS 17
#define	SD_SWITCH_GROUP3_BUSY_STATUS 18
#define	SD_SWITCH_GROUP2_BUSY_STATUS 19
#define	SD_SWITCH_GROUP1_BUSY_STATUS 20
#define	SD_SWITCH_GROUP1_SDR12 (1 << 0)
#define	SD_SWITCH_GROUP1_HS (1 << 1)
#define	SD_SWITCH_GROUP1_SDR25 (1 << 1)
#define	SD_SWITCH_GROUP1_SDR50 (1 << 2)
#define	SD_SWITCH_GROUP1_SDR104 (1 << 3)
#define	SD_SWITCH_GROUP1_DDR50 (1 << 4)
#define	SD_SWITCH_GROUP3_TYPE_B (1 << 0)
#define	SD_SWITCH_GROUP3_TYPE_A (1 << 1)
#define	SD_SWITCH_GROUP3_TYPE_C (1 << 2)
#define	SD_SWITCH_GROUP3_TYPE_D (1 << 3)
#define	SD_SWITCH_STRUCT_VER_0 0
	Bits 511:376 are defined (SD_SWITCH_MAXIMUM_CURRENT to SD_SWITCH_GROUP1_SELECTION).
#define	SD_SWITCH_STRUCT_VER_1 1
	Bits 511:272 are defined (SD_SWITCH_MAXIMUM_CURRENT to SD_SWITCH_GROUP1_BUSY_STATUS.
#define	SD_SCR_STRUCTURE 1
#define	SD_SCR_SD_SPEC 2
#define	SD_SCR_DATA_STAT_AFTER_ERASE 3
#define	SD_SCR_SD_SECURITY 4
#define	SD_SCR_SD_BUS_WIDTHS 5
#define	SD_SCR_SD_SPEC3 6
#define	SD_SCR_EX_SECURITY 7
#define	SD_SCR_SD_SPEC4 8
#define	SD_SCR_CMD_SUPPORT 9
#define	SD_SCR_STRUCT_VER_1_0 0
	Valid for system specification 1.01 - 4.0.
#define	SD_SCR_SPEC_VER_0 0
	Implements system specification 1.0 - 1.01.
#define	SD_SCR_SPEC_VER_1 1
	Implements system specification 1.10.
#define	SD_SCR_SPEC_VER_2 2
	Implements system specification 2.00-4.0X.
#define	SD_SCR_SECURITY_VER_0 0
	No Security.
#define	SD_SCR_SECURITY_VER_2 2
	SDSC Card (Security Version 1.01).
#define	SD_SCR_SECURITY_VER_3 3
	SDHC Card (Security Version 2.00).
#define	SD_SCR_SECURITY_VER_4 4
	SDXC Card (Security Version 3.xx).
#define	SD_SCR_BUS_WIDTH_1 (1 << 0)
	1 bit (DAT0)
#define	SD_SCR_BUS_WIDTH_4 (1 << 2)
	4 bit (DAT0-3)
#define	SD_SCR_EX_SECURITY_VER_0 0
	Extended Security is not supported.
#define	SD_SCR_CMD20_SUPPORT (1 << 0)
	Mandatory for SDXC card.
#define	SD_SCR_CMD23_SUPPORT (1 << 1)
	Mandatory for UHS104 card.
#define	SD_SCR_CMD48_49_SUPPORT (1 << 2)
	Optional.
#define	SD_SCR_CMD58_59_SUPPORT (1 << 3)
	Optional (If CMD58/59 is supported, CMD48/49 shall be supported).
#define	SDIO_STATE_DETACHED 0
#define	SDIO_STATE_DETACHING 1
#define	SDIO_STATE_ATTACHING 2
#define	SDIO_STATE_ATTACHED 3
#define	SDIO_STATE_MAX 3
#define	SDIO_STATUS_UNBOUND 0
#define	SDIO_STATUS_BOUND 1
#define	SDIO_STATUS_MAX 1
#define	SDIO_CMD_SEND_OP_COND 5
#define	SDIO_CMD_RW_DIRECT 52
#define	SDIO_CMD_RW_EXTENDED 53
#define	SDIO_RSP_R4_18V_PRESENT (1 << 24)
#define	SDIO_RSP_R4_MEMORY_PRESENT (1 << 27)
#define	SDIO_RSP_R5_COM_CRC_ERROR (1 << 15)
#define	SDIO_RSP_R5_ILLEGAL_COMMAND (1 << 14)
#define	SDIO_RSP_R5_ERROR (1 << 11)
#define	SDIO_RSP_R5_FUNCTION_NUMBER (1 << 9)
#define	SDIO_RSP_R5_OUT_OF_RANGE (1 << 8)
#define	SDIO_CCCR_CCCR 0x00
#define	SDIO_CCCR_SD 0x01
#define	SDIO_CCCR_IOEx 0x02
#define	SDIO_CCCR_IORx 0x03
#define	SDIO_CCCR_IENx 0x04
	Function/Master Interrupt Enable.
#define	SDIO_CCCR_INTx 0x05
	Function Interrupt Pending.
#define	SDIO_CCCR_ABORT 0x06
	Function abort/card reset.
#define	SDIO_CCCR_IF 0x07
	Bus interface controls.
#define	SDIO_CCCR_CAPS 0x08
#define	SDIO_CCCR_CIS 0x09
	Common CIS pointer (3 bytes).
#define	SDIO_CCCR_SUSPEND 0x0c
#define	SDIO_CCCR_SELx 0x0d
#define	SDIO_CCCR_EXECx 0x0e
#define	SDIO_CCCR_READYx 0x0f
#define	SDIO_CCCR_BLKSIZE 0x10
#define	SDIO_CCCR_POWER 0x12
#define	SDIO_CCCR_SPEED 0x13
#define	SDIO_CCCR_UHS 0x14
#define	SDIO_CCCR_DRIVE_STRENGTH 0x15
#define	SDIO_CCCR_REV_1_00 0
	CCCR/FBR Version 1.00.
#define	SDIO_CCCR_REV_1_10 1
	CCCR/FBR Version 1.10.
#define	SDIO_CCCR_REV_1_20 2
	CCCR/FBR Version 1.20.
#define	SDIO_CCCR_REV_3_00 3
	CCCR/FBR Version 3.00.
#define	SDIO_SDIO_REV_1_00 0
	SDIO Spec Version 1.00.
#define	SDIO_SDIO_REV_1_10 1
	SDIO Spec Version 1.10.
#define	SDIO_SDIO_REV_1_20 2
	SDIO Spec Version 1.20.
#define	SDIO_SDIO_REV_2_00 3
	SDIO Spec Version 2.00.
#define	SDIO_SDIO_REV_3_00 4
	SDIO Spec Version 3.00.
#define	SDIO_SD_REV_1_01 0
	SD Physical Spec Version 1.01.
#define	SDIO_SD_REV_1_10 1
	SD Physical Spec Version 1.10.
#define	SDIO_SD_REV_2_00 2
	SD Physical Spec Version 2.00.
#define	SDIO_SD_REV_3_00 3
	SD Physical Spev Version 3.00.
#define	SDIO_BUS_WIDTH_MASK 0x03
	data bus width setting
#define	SDIO_BUS_WIDTH_1BIT 0x00
#define	SDIO_BUS_WIDTH_RESERVED 0x01
#define	SDIO_BUS_WIDTH_4BIT 0x02
#define	SDIO_BUS_ECSI 0x20
	Enable continuous SPI interrupt.
#define	SDIO_BUS_SCSI 0x40
	Support continuous SPI interrupt.
#define	SDIO_BUS_ASYNC_INT 0x20
#define	SDIO_BUS_CD_DISABLE 0x80
	disable pull-up on DAT3 (pin 1)
#define	SDIO_CCCR_CAP_SDC 0x01
	Can do CMD52 while data transfer.
#define	SDIO_CCCR_CAP_SMB 0x02
	Can do multi-block xfers (CMD53).
#define	SDIO_CCCR_CAP_SRW 0x04
	Supports read-wait protocol.
#define	SDIO_CCCR_CAP_SBS 0x08
	Supports suspend/resume.
#define	SDIO_CCCR_CAP_S4MI 0x10
	Interrupt during 4-bit CMD53.
#define	SDIO_CCCR_CAP_E4MI 0x20
	Enable ints during 4-bit CMD53.
#define	SDIO_CCCR_CAP_LSC 0x40
	Low speed card.
#define	SDIO_CCCR_CAP_4BLS 0x80
	4 bit low speed card
#define	SDIO_POWER_SMPC 0x01
	Supports Master Power Control.
#define	SDIO_POWER_EMPC 0x02
	Enable Master Power Control.
#define	SDIO_SPEED_SHS 0x01
	Supports High-Speed mode.
#define	SDIO_SPEED_BSS_SHIFT 1
#define	SDIO_SPEED_BSS_MASK (7 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_SDR12 (0 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_SDR25 (1 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_SDR50 (2 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_SDR104 (3 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_DDR50 (4 << SDIO_SPEED_BSS_SHIFT)
#define	SDIO_SPEED_EHS SDIO_SPEED_SDR25
	Enable High-Speed.
#define	SDIO_UHS_SDR50 0x01
#define	SDIO_UHS_SDR104 0x02
#define	SDIO_UHS_DDR50 0x04
#define	SDIO_SDTx_MASK 0x07
#define	SDIO_DRIVE_SDTA (1 << 0)
#define	SDIO_DRIVE_SDTC (1 << 1)
#define	SDIO_DRIVE_SDTD (1 << 2)
#define	SDIO_DRIVE_DTSx_MASK 0x03
#define	SDIO_DRIVE_DTSx_SHIFT 4
#define	SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)
#define	SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
#define	SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
#define	SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
#define	SDIO_FBR_BASE(f)
#define	SDIO_FBR_STD_IF 0x00
#define	SDIO_FBR_STD_IF_EXT 0x01
#define	SDIO_FBR_POWER 0x02
#define	SDIO_FBR_CIS 0x09
	CIS pointer (3 bytes).
#define	SDIO_FBR_CSA 0x0C
	CSA pointer (3 bytes).
#define	SDIO_FBR_CSA_DATA 0x0F
#define	SDIO_FBR_BLKSIZE 0x10
	Block size (2 bytes).
#define	SDIO_FBR_SUPPORTS_CSA 0x40
	Supports Code Storage Area.
#define	SDIO_FBR_ENABLE_CSA 0x80
	Enable Code Storage Area.
#define	SDIO_FBR_POWER_SPS 0x01
	Supports Power Selection.
#define	SDIO_FBR_POWER_EPS 0x02
	Enable (low) Power Selection.
#define	SDIO_CLASS_NONE 0x00
	Not a SDIO standard interface.
#define	SDIO_CLASS_UART 0x01
	Standard UART interface.
#define	SDIO_CLASS_BT_A 0x02
	Type-A BlueTooth std interface.
#define	SDIO_CLASS_BT_B 0x03
	Type-B BlueTooth std interface.
#define	SDIO_CLASS_GPS 0x04
	GPS standard interface.
#define	SDIO_CLASS_CAMERA 0x05
	Camera standard interface.
#define	SDIO_CLASS_PHS 0x06
	PHS standard interface.
#define	SDIO_CLASS_WLAN 0x07
	WLAN interface.
#define	SDIO_CLASS_ATA 0x08
	Embedded SDIO-ATA std interface.
#define	SDIO_CLASS_BT_AMP 0x09
	Type-A Bluetooth AMP interface.
#define	SDIO_VENDOR_ID_STE 0x0020
#define	SDIO_VENDOR_ID_INTEL 0x0089
#define	SDIO_VENDOR_ID_CGUYS 0x0092
#define	SDIO_VENDOR_ID_TI 0x0097
#define	SDIO_VENDOR_ID_ATHEROS 0x0271
#define	SDIO_VENDOR_ID_BROADCOM 0x02d0
#define	SDIO_VENDOR_ID_MARVELL 0x02df
#define	SDIO_VENDOR_ID_MEDIATEK 0x037a
#define	SDIO_VENDOR_ID_MICROCHIP_WILC 0x0296
#define	SDIO_VENDOR_ID_SIANO 0x039a
#define	SDIO_VENDOR_ID_RSI 0x041b
#define	SDIO_VENDOR_ID_TI_WL1251 0x104c
#define	SDIO_DEVICE_ID_STE_CW1200 0x2280
#define	SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402
#define	SDIO_DEVICE_ID_INTEL_IWMC3200WIFI 0x1403
#define	SDIO_DEVICE_ID_INTEL_IWMC3200TOP 0x1404
#define	SDIO_DEVICE_ID_INTEL_IWMC3200GPS 0x1405
#define	SDIO_DEVICE_ID_INTEL_IWMC3200BT 0x1406
#define	SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX_2G5 0x1407
#define	SDIO_DEVICE_ID_CGUYS_EW_CG1102GC 0x0004
#define	SDIO_DEVICE_ID_TI_WL1271 0x4076
#define	SDIO_DEVICE_ID_ATHEROS_AR6003_00 0x0300
#define	SDIO_DEVICE_ID_ATHEROS_AR6003_01 0x0301
#define	SDIO_DEVICE_ID_ATHEROS_AR6004_00 0x0400
#define	SDIO_DEVICE_ID_ATHEROS_AR6004_01 0x0401
#define	SDIO_DEVICE_ID_ATHEROS_AR6004_02 0x0402
#define	SDIO_DEVICE_ID_ATHEROS_AR6004_18 0x0418
#define	SDIO_DEVICE_ID_ATHEROS_AR6004_19 0x0419
#define	SDIO_DEVICE_ID_ATHEROS_AR6005 0x050A
#define	SDIO_DEVICE_ID_ATHEROS_QCA9377 0x0701
#define	SDIO_DEVICE_ID_BROADCOM_NINTENDO_WII 0x044b
#define	SDIO_DEVICE_ID_BROADCOM_43241 0x4324
#define	SDIO_DEVICE_ID_BROADCOM_4329 0x4329
#define	SDIO_DEVICE_ID_BROADCOM_4330 0x4330
#define	SDIO_DEVICE_ID_BROADCOM_4334 0x4334
#define	SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
#define	SDIO_DEVICE_ID_BROADCOM_4339 0x4339
#define	SDIO_DEVICE_ID_BROADCOM_4345 0x4345
#define	SDIO_DEVICE_ID_BROADCOM_4354 0x4354
#define	SDIO_DEVICE_ID_BROADCOM_CYPRESS_89359 0x4355
#define	SDIO_DEVICE_ID_BROADCOM_4356 0x4356
#define	SDIO_DEVICE_ID_BROADCOM_4359 0x4359
#define	SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373 0x4373
#define	SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012 0xa804
#define	SDIO_DEVICE_ID_BROADCOM_43143 0xa887
#define	SDIO_DEVICE_ID_BROADCOM_43340 0xa94c
#define	SDIO_DEVICE_ID_BROADCOM_43341 0xa94d
#define	SDIO_DEVICE_ID_BROADCOM_43362 0xa962
#define	SDIO_DEVICE_ID_BROADCOM_43364 0xa9a4
#define	SDIO_DEVICE_ID_BROADCOM_43430 0xa9a6
#define	SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf
#define	SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103
#define	SDIO_DEVICE_ID_MARVELL_8688_WLAN 0x9104
#define	SDIO_DEVICE_ID_MARVELL_8688_BT 0x9105
#define	SDIO_DEVICE_ID_MARVELL_8786_WLAN 0x9116
#define	SDIO_DEVICE_ID_MARVELL_8787_WLAN 0x9119
#define	SDIO_DEVICE_ID_MARVELL_8787_BT 0x911a
#define	SDIO_DEVICE_ID_MARVELL_8787_BT_AMP 0x911b
#define	SDIO_DEVICE_ID_MARVELL_8797_F0 0x9128
#define	SDIO_DEVICE_ID_MARVELL_8797_WLAN 0x9129
#define	SDIO_DEVICE_ID_MARVELL_8797_BT 0x912a
#define	SDIO_DEVICE_ID_MARVELL_8897_WLAN 0x912d
#define	SDIO_DEVICE_ID_MARVELL_8897_BT 0x912e
#define	SDIO_DEVICE_ID_MARVELL_8887_F0 0x9134
#define	SDIO_DEVICE_ID_MARVELL_8887_WLAN 0x9135
#define	SDIO_DEVICE_ID_MARVELL_8887_BT 0x9136
#define	SDIO_DEVICE_ID_MARVELL_8801_WLAN 0x9139
#define	SDIO_DEVICE_ID_MARVELL_8997_F0 0x9140
#define	SDIO_DEVICE_ID_MARVELL_8997_WLAN 0x9141
#define	SDIO_DEVICE_ID_MARVELL_8997_BT 0x9142
#define	SDIO_DEVICE_ID_MARVELL_8977_WLAN 0x9145
#define	SDIO_DEVICE_ID_MARVELL_8977_BT 0x9146
#define	SDIO_DEVICE_ID_MARVELL_8987_WLAN 0x9149
#define	SDIO_DEVICE_ID_MARVELL_8987_BT 0x914a
#define	SDIO_DEVICE_ID_MEDIATEK_MT7663 0x7663
#define	SDIO_DEVICE_ID_MEDIATEK_MT7668 0x7668
#define	SDIO_DEVICE_ID_MICROCHIP_WILC1000 0x5347
#define	SDIO_DEVICE_ID_SIANO_NOVA_B0 0x0201
#define	SDIO_DEVICE_ID_SIANO_NICE 0x0202
#define	SDIO_DEVICE_ID_SIANO_VEGA_A0 0x0300
#define	SDIO_DEVICE_ID_SIANO_VENICE 0x0301
#define	SDIO_DEVICE_ID_SIANO_MING 0x0302
#define	SDIO_DEVICE_ID_SIANO_PELE 0x0500
#define	SDIO_DEVICE_ID_SIANO_RIO 0x0600
#define	SDIO_DEVICE_ID_SIANO_DENVER_2160 0x0700
#define	SDIO_DEVICE_ID_SIANO_DENVER_1530 0x0800
#define	SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100
#define	SDIO_DEVICE_ID_SIANO_STELLAR 0x5347
#define	SDIO_DEVICE_ID_TI_WL1251 0x9066
#define	CISTPL_NULL 0x00
#define	CISTPL_CHECKSUM 0x10
#define	CISTPL_VERS_1 0x15
#define	CISTPL_ALTSTR 0x16
#define	CISTPL_MANFID 0x20
#define	CISTPL_FUNCID 0x21
#define	CISTPL_FUNCE 0x22
#define	CISTPL_SDIO_STD 0x91
#define	CISTPL_SDIO_EXT 0x92
#define	CISTPL_END 0xFF
#define	SDIO_MAX_FUNCTIONS 7
#define	SDIO_READ_CIS_TIMEOUT_MS (10 * 1000)
	10 seconds
#define	SDHCI_NAME_PREFIX "SDHCI"
	Name prefix for SDHCI Devices.
#define	SDHCI_TYPE_NONE 0
#define	SDHCI_TYPE_MMC 1
	An MMC specification host controller.
#define	SDHCI_TYPE_SD 2
	An SD specification host controller.
#define	SDHCI_TYPE_MMCI 3
	An MMCI specification host controller.
#define	SDHCI_TYPE_MAX 3
#define	SDHCI_STATE_DISABLED 0
#define	SDHCI_STATE_ENABLED 1
#define	SDHCI_STATE_MAX 1
#define	SDHCI_FLAG_NONE 0x00000000
#define	SDHCI_FLAG_SDMA 0x00000001
	Host Controller supports SDMA specification.
#define	SDHCI_FLAG_ADMA 0x00000002
	Host Controller supports ADMA specification.
#define	SDHCI_FLAG_SPI 0x00000004
	Host Controller uses SPI interface.
#define	SDHCI_FLAG_CRC_ENABLE 0x00000008
#define	SDHCI_FLAG_NON_STANDARD 0x00000010
	Host Controller uses a non standard interface (not supporting SDHCI register layout).
#define	SDHCI_FLAG_AUTO_CMD12 0x00000020
	Host Controller supports Auto CMD12 (Stop Transmission).
#define	SDHCI_FLAG_AUTO_CMD23 0x00000040
	Host Controller supports Auto CMD23 (Set Block Count).
#define	SDHCI_FLAG_64_BIT_DMA 0x00000080
	Host Controller supports 64-bit ADMA.
#define	SDHCI_FLAG_EXTERNAL_DMA 0x00000100
	Host Controller requires external DMA engine to perform transfers.
#define	SDHCI_FLAG_BUS_ADDRESSES 0x00000200
	Host Controller requires use of bus addresses for SDMA/ADMA transfers.
#define	SDHCI_DMA_ADDRESS 0x00
#define	SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
#define	SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
#define	SDHCI_BLOCK_SIZE 0x04
#define	SDHCI_BLOCK_COUNT 0x06
#define	SDHCI_ARGUMENT 0x08
#define	SDHCI_TRANSFER_MODE 0x0C
#define	SDHCI_COMMAND 0x0E
#define	SDHCI_RESPONSE 0x10
#define	SDHCI_BUFFER 0x20
#define	SDHCI_PRESENT_STATE 0x24
#define	SDHCI_HOST_CONTROL 0x28
#define	SDHCI_POWER_CONTROL 0x29
#define	SDHCI_BLOCK_GAP_CONTROL 0x2A
#define	SDHCI_WAKE_UP_CONTROL 0x2B
#define	SDHCI_CLOCK_CONTROL 0x2C
#define	SDHCI_TIMEOUT_CONTROL 0x2E
#define	SDHCI_SOFTWARE_RESET 0x2F
#define	SDHCI_INT_STATUS 0x30
#define	SDHCI_INT_ENABLE 0x34
#define	SDHCI_SIGNAL_ENABLE 0x38
#define	SDHCI_AUTO_CMD_STATUS 0x3C
	SDHCI_ACMD12_ERR.
#define	SDHCI_HOST_CONTROL2 0x3E
#define	SDHCI_CAPABILITIES 0x40
#define	SDHCI_CAPABILITIES_1 0x44
#define	SDHCI_MAX_CURRENT 0x48
#define	SDHCI_SET_ACMD12_ERROR 0x50
#define	SDHCI_SET_INT_ERROR 0x52
#define	SDHCI_ADMA_ERROR 0x54
#define	SDHCI_ADMA_ADDRESS 0x58
#define	SDHCI_ADMA_ADDRESS_HI 0x5C
#define	SDHCI_PRESET_FOR_SDR12 0x66
#define	SDHCI_PRESET_FOR_SDR25 0x68
#define	SDHCI_PRESET_FOR_SDR50 0x6A
#define	SDHCI_PRESET_FOR_SDR104 0x6C
#define	SDHCI_PRESET_FOR_DDR50 0x6E
#define	SDHCI_PRESET_FOR_HS400 0x74
	Non-standard.
#define	SDHCI_SLOT_INT_STATUS 0xFC
#define	SDHCI_HOST_VERSION 0xFE
#define	SDHCI_TRNS_DMA 0x01
#define	SDHCI_TRNS_BLK_CNT_EN 0x02
#define	SDHCI_TRNS_AUTO_CMD12 0x04
	SDHCI_TRNS_ACMD12.
#define	SDHCI_TRNS_AUTO_CMD23 0x08
#define	SDHCI_TRNS_AUTO_SEL SDHCI_TRNS_AUTO_CMD12 \| SDHCI_TRNS_AUTO_CMD23
#define	SDHCI_TRNS_READ 0x10
#define	SDHCI_TRNS_MULTI 0x20
#define	SDHCI_CMD_RESP_MASK 0x03
#define	SDHCI_CMD_CRC 0x08
#define	SDHCI_CMD_INDEX 0x10
#define	SDHCI_CMD_DATA 0x20
#define	SDHCI_CMD_ABORTCMD 0xC0
#define	SDHCI_CMD_RESP_NONE 0x00
#define	SDHCI_CMD_RESP_LONG 0x01
#define	SDHCI_CMD_RESP_SHORT 0x02
#define	SDHCI_CMD_RESP_SHORT_BUSY 0x03
#define	SDHCI_CMD_INHIBIT 0x00000001
#define	SDHCI_DATA_INHIBIT 0x00000002
#define	SDHCI_DOING_WRITE 0x00000100
#define	SDHCI_DOING_READ 0x00000200
#define	SDHCI_SPACE_AVAILABLE 0x00000400
#define	SDHCI_DATA_AVAILABLE 0x00000800
#define	SDHCI_CARD_PRESENT 0x00010000
#define	SDHCI_CARD_STATE_STABLE 0x00020000
	SDHCI_CD_STABLE.
#define	SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
	SDHCI_CD_LVL.
#define	SDHCI_WRITE_PROTECT 0x00080000
	Set if Write Enabled / Clear if Write Protected.
#define	SDHCI_DATA_LEVEL_MASK 0x00F00000
	SDHCI_DATA_LVL_MASK.
#define	SDHCI_DATA_0_LEVEL_MASK 0x00100000
	SDHCI_DATA_0_LVL_MASK.
#define	SDHCI_CMD_LEVEL 0x01000000
	SDHCI_CMD_LVL.
#define	SDHCI_CTRL_LED 0x01
#define	SDHCI_CTRL_4BITBUS 0x02
#define	SDHCI_CTRL_HISPD 0x04
#define	SDHCI_CTRL_DMA_MASK 0x18
#define	SDHCI_CTRL_SDMA 0x00
#define	SDHCI_CTRL_ADMA1 0x08
#define	SDHCI_CTRL_ADMA32 0x10
#define	SDHCI_CTRL_ADMA64 0x18
#define	SDHCI_CTRL_ADMA3 0x18
#define	SDHCI_CTRL_8BITBUS 0x20
#define	SDHCI_CTRL_CD_TEST_INS 0x40
#define	SDHCI_CTRL_CD_TEST 0x80
#define	SDHCI_POWER_ON 0x01
#define	SDHCI_POWER_180 0x0A
#define	SDHCI_POWER_300 0x0C
#define	SDHCI_POWER_330 0x0E
#define	SDHCI_WAKE_ON_INT 0x01
#define	SDHCI_WAKE_ON_INSERT 0x02
#define	SDHCI_WAKE_ON_REMOVE 0x04
#define	SDHCI_DIVIDER_SHIFT 8
#define	SDHCI_DIVIDER_HI_SHIFT 6
#define	SDHCI_DIV_MASK 0xFF
#define	SDHCI_DIV_MASK_LEN 8
#define	SDHCI_DIV_HI_MASK 0x0300
#define	SDHCI_PROG_CLOCK_MODE 0x0020
#define	SDHCI_CLOCK_CARD_EN 0x0004
#define	SDHCI_CLOCK_PLL_EN 0x0008
#define	SDHCI_CLOCK_INT_STABLE 0x0002
#define	SDHCI_CLOCK_INT_EN 0x0001
#define	SDHCI_RESET_ALL 0x01
#define	SDHCI_RESET_CMD 0x02
#define	SDHCI_RESET_DATA 0x04
#define	SDHCI_INT_RESPONSE 0x00000001
#define	SDHCI_INT_DATA_END 0x00000002
#define	SDHCI_INT_BLK_GAP 0x00000004
#define	SDHCI_INT_DMA_END 0x00000008
#define	SDHCI_INT_SPACE_AVAIL 0x00000010
#define	SDHCI_INT_DATA_AVAIL 0x00000020
#define	SDHCI_INT_CARD_INSERT 0x00000040
#define	SDHCI_INT_CARD_REMOVE 0x00000080
#define	SDHCI_INT_CARD_INT 0x00000100
#define	SDHCI_INT_RETUNE 0x00001000
#define	SDHCI_INT_CQE 0x00004000
#define	SDHCI_INT_ERROR 0x00008000
#define	SDHCI_INT_TIMEOUT 0x00010000
#define	SDHCI_INT_CRC 0x00020000
#define	SDHCI_INT_END_BIT 0x00040000
#define	SDHCI_INT_INDEX 0x00080000
#define	SDHCI_INT_DATA_TIMEOUT 0x00100000
#define	SDHCI_INT_DATA_CRC 0x00200000
#define	SDHCI_INT_DATA_END_BIT 0x00400000
#define	SDHCI_INT_BUS_POWER 0x00800000
#define	SDHCI_INT_AUTO_CMD_ERR 0x01000000
	SDHCI_INT_ACMD12ERR.
#define	SDHCI_INT_ADMA_ERROR 0x02000000
#define	SDHCI_INT_NORMAL_MASK 0x00007FFF
#define	SDHCI_INT_ERROR_MASK 0xFFFF8000
#define	SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX \| SDHCI_INT_AUTO_CMD_ERR)
#define	SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR \| SDHCI_INT_BLK_GAP)
#define	SDHCI_INT_ALL_MASK (LongWord(-1))
#define	SDHCI_CQE_INT_ERR_MASK (SDHCI_INT_ADMA_ERROR \| SDHCI_INT_BUS_POWER \| SDHCI_INT_DATA_END_BIT \| SDHCI_INT_DATA_CRC \| SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_INDEX \| SDHCI_INT_END_BIT \| SDHCI_INT_CRC \| SDHCI_INT_TIMEOUT)
#define	SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK \| SDHCI_INT_CQE)
#define	SDHCI_AUTO_CMD_TIMEOUT 0x00000002
#define	SDHCI_AUTO_CMD_CRC 0x00000004
#define	SDHCI_AUTO_CMD_END_BIT 0x00000008
#define	SDHCI_AUTO_CMD_INDEX 0x00000010
#define	SDHCI_CTRL_UHS_MASK 0x0007
#define	SDHCI_CTRL_UHS_SDR12 0x0000
#define	SDHCI_CTRL_UHS_SDR25 0x0001
#define	SDHCI_CTRL_UHS_SDR50 0x0002
#define	SDHCI_CTRL_UHS_SDR104 0x0003
#define	SDHCI_CTRL_UHS_DDR50 0x0004
#define	SDHCI_CTRL_HS400 0x0005
	Non-standard.
#define	SDHCI_CTRL_VDD_180 0x0008
#define	SDHCI_CTRL_DRV_TYPE_MASK 0x0030
#define	SDHCI_CTRL_DRV_TYPE_B 0x0000
#define	SDHCI_CTRL_DRV_TYPE_A 0x0010
#define	SDHCI_CTRL_DRV_TYPE_C 0x0020
#define	SDHCI_CTRL_DRV_TYPE_D 0x0030
#define	SDHCI_CTRL_EXEC_TUNING 0x0040
#define	SDHCI_CTRL_TUNED_CLK 0x0080
#define	SDHCI_CMD23_ENABLE 0x0800
#define	SDHCI_CTRL_V4_MODE 0x1000
#define	SDHCI_CTRL_64BIT_ADDR 0x2000
#define	SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define	SDHCI_TIMEOUT_CLK_MASK 0x0000003F
#define	SDHCI_TIMEOUT_CLK_SHIFT 0
#define	SDHCI_TIMEOUT_CLK_UNIT 0x00000080
#define	SDHCI_CLOCK_BASE_MASK 0x00003F00
#define	SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
#define	SDHCI_CLOCK_BASE_SHIFT 8
#define	SDHCI_CLOCK_BASE_MULTIPLIER 1000000
#define	SDHCI_MAX_BLOCK_MASK 0x00030000
#define	SDHCI_MAX_BLOCK_SHIFT 16
#define	SDHCI_CAN_DO_8BIT 0x00040000
#define	SDHCI_CAN_DO_ADMA2 0x00080000
#define	SDHCI_CAN_DO_ADMA1 0x00100000
#define	SDHCI_CAN_DO_HISPD 0x00200000
#define	SDHCI_CAN_DO_SDMA 0x00400000
#define	SDHCI_CAN_VDD_330 0x01000000
#define	SDHCI_CAN_VDD_300 0x02000000
#define	SDHCI_CAN_VDD_180 0x04000000
#define	SDHCI_CAN_64BIT_V4 0x08000000
#define	SDHCI_CAN_64BIT 0x10000000
#define	SDHCI_SUPPORT_SDR50 0x00000001
#define	SDHCI_SUPPORT_SDR104 0x00000002
#define	SDHCI_SUPPORT_DDR50 0x00000004
#define	SDHCI_DRIVER_TYPE_A 0x00000010
#define	SDHCI_DRIVER_TYPE_C 0x00000020
#define	SDHCI_DRIVER_TYPE_D 0x00000040
#define	SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
	GENMASK(11,8).
#define	SDHCI_USE_SDR50_TUNING 0x00002000
#define	SDHCI_RETUNING_MODE_MASK 0x0000C000
	GENMASK(15,14).
#define	SDHCI_CLOCK_MUL_MASK 0x00FF0000
	GENMASK(23,16).
#define	SDHCI_CAN_DO_ADMA3 0x08000000
#define	SDHCI_SUPPORT_HS400 0x80000000
	Non-standard.
#define	SDHCI_MAX_CURRENT_LIMIT 0x000000FF
	GENMASK(7,0).
#define	SDHCI_MAX_CURRENT_330_MASK 0x000000FF
	GENMASK(7,0).
#define	SDHCI_MAX_CURRENT_300_MASK 0x0000FF00
	GENMASK(15,8).
#define	SDHCI_MAX_CURRENT_180_MASK 0x00FF0000
	GENMASK(23,16).
#define	SDHCI_MAX_CURRENT_MULTIPLIER 4
#define	SDHCI_PRESET_DRV_MASK 0x0000C000
	GENMASK(15,14).
#define	SDHCI_PRESET_DRV_SHIFT 14
#define	SDHCI_PRESET_CLKGEN_SEL 1 << 10
	BIT(10).
#define	SDHCI_PRESET_SDCLK_FREQ_MASK 0x000003FF
	GENMASK(9,0).
#define	SDHCI_VENDOR_VER_MASK 0xFF00
#define	SDHCI_VENDOR_VER_SHIFT 8
#define	SDHCI_SPEC_VER_MASK 0x00FF
#define	SDHCI_SPEC_VER_SHIFT 0
#define	SDHCI_SPEC_100 0
#define	SDHCI_SPEC_200 1
#define	SDHCI_SPEC_300 2
#define	SDHCI_SPEC_400 3
#define	SDHCI_SPEC_410 4
#define	SDHCI_SPEC_420 5
#define	SDHCI_MAX_CLOCK_DIV_SPEC_200 256
#define	SDHCI_MAX_CLOCK_DIV_SPEC_300 2046
#define	SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
	Controller doesn't honor resets unless we touch the clock register.
#define	SDHCI_QUIRK_FORCE_DMA (1 << 1)
	Controller has bad caps bits, but really supports DMA.
#define	SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2)
	Controller doesn't like to be reset when there is no card inserted.
#define	SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3)
	Controller doesn't like clearing the power reg before a change.
#define	SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1 << 4)
	Controller has flaky internal state so reset it on each ios change.
#define	SDHCI_QUIRK_BROKEN_DMA (1 << 5)
	Controller has an unusable DMA engine.
#define	SDHCI_QUIRK_BROKEN_ADMA (1 << 6)
	Controller has an unusable ADMA engine.
#define	SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7)
	Controller can only DMA from 32-bit aligned addresses.
#define	SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8)
	Controller can only DMA chunk sizes that are a multiple of 32 bits.
#define	SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9)
	Controller can only ADMA chunks that are a multiple of 32 bits.
#define	SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10)
	Controller needs to be reset after each request to stay stable.
#define	SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11)
	Controller needs voltage and power writes to happen separately.
#define	SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12)
	Controller provides an incorrect timeout value for transfers.
#define	SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13)
	Controller has an issue with buffer bits for small transfers.
#define	SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14)
	Controller does not provide transfer-complete interrupt when not busy.
#define	SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15)
	Controller has unreliable card detection.
#define	SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16)
	Controller reports inverted write-protect state.
#define	SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18)
	Controller does not like fast PIO transfers.
#define	SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20)
	Controller has to be forced to use block size of 2048 bytes.
#define	SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21)
	Controller cannot do multi-block transfers.
#define	SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22)
	Controller can only handle 1-bit data transfers.
#define	SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23)
	Controller needs 10ms delay between applying power and clock.
#define	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
	Controller uses SDCLK instead of TMCLK for data timeouts.
#define	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25)
	Controller reports wrong base clock capability.
#define	SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26)
	Controller cannot support End Attribute in NOP ADMA descriptor.
#define	SDHCI_QUIRK_MISSING_CAPS (1 << 27)
	Controller is missing device caps. Use caps provided by host.
#define	SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28)
	Controller uses Auto CMD12 command to stop the transfer.
#define	SDHCI_QUIRK_NO_HISPD_BIT (1 << 29)
	Controller doesn't have HISPD bit field in HI-SPEED SD card.
#define	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30)
	Controller treats ADMA descriptors with length 0000h incorrectly.
#define	SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31)
	The read-only detection via SDHCI_PRESENT_STATE register is unstable.
#define	SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0)
#define	SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1)
#define	SDHCI_QUIRK2_NO_1_8_V (1 << 2)
	The system physically doesn't support 1.8v, even if the host does.
#define	SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3)
#define	SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4)
#define	SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5)
	Controller has a non-standard host control register.
#define	SDHCI_QUIRK2_BROKEN_HS200 (1 << 6)
	Controller does not support HS200.
#define	SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7)
	Controller does not support DDR50.
#define	SDHCI_QUIRK2_STOP_WITH_TC (1 << 8)
	Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY.
#define	SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9)
	Controller does not support 64-bit DMA.
#define	SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10)
	Need clear transfer mode register before send cmd.
#define	SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11)
	Capability register bit-63 indicates HS400 support.
#define	SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12)
	Forced tuned clock.
#define	SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13)
	Disable the block count for single block transactions.
#define	SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14)
	Controller broken with using ACMD23.
#define	SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15)
	Broken Clock divider zero in controller.
#define	SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16)
	Controller has CRC in 136 bit Command Response.
#define	SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17)
	Disable HW timeout if the requested timeout is more than the maximum obtainable timeout.
#define	SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18)
	32-bit block count may not support eMMC where upper bits of CMD23 are used for other purposes
#define	SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
	Default to 512K boundary.
#define	SDHCI_DEFAULT_BOUNDARY_ARG 7
	(ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
#define	SDHCI_ADMA2_32_DESC_SIZE 8
#define	SDHCI_ADMA2_ALIGN 4
#define	SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
#define	SDHCI_ADMA2_DESC_ALIGN 8
#define	SDHCI_ADMA2_64_DESC_SIZE 12
#define	SDHCI_ADMA2_64_DESC_V4_SIZE 16
	Use 128-bit descriptor, if Host Version 4 Enable is set in the Host Control 2 register.
#define	SDHCI_ADMA2_DESC_ATTR_VALID 0x01
#define	SDHCI_ADMA2_DESC_ATTR_END 0x02
#define	SDHCI_ADMA2_DESC_ATTR_INT 0x04
#define	SDHCI_ADMA2_DESC_ATTR_NOP 0x00
#define	SDHCI_ADMA2_DESC_ATTR_TRAN 0x20
#define	SDHCI_ADMA2_DESC_ATTR_LINK 0x30
#define	SDHCI_ADMA2_DESC_TRAN_VALID SDHCI_ADMA2_DESC_ATTR_TRAN \| SDHCI_ADMA2_DESC_ATTR_VALID
	0x21
#define	SDHCI_ADMA2_DESC_NOP_END_VALID SDHCI_ADMA2_DESC_ATTR_NOP \| SDHCI_ADMA2_DESC_ATTR_END \| SDHCI_ADMA2_DESC_ATTR_VALID
	0x3
#define	SDHCI_ADMA2_DESC_END SDHCI_ADMA2_DESC_ATTR_END
	0x2
#define	SDHCI_MAX_SEGS 128
#define	SDHCI_TIMEOUT_VALUE 0x0E

Typedefs
typedef struct _MMC_DATA	MMC_DATA
typedef struct _MMC_COMMAND	MMC_COMMAND
typedef struct _MMC_CARD_IDENTIFICATION_DATA	MMC_CARD_IDENTIFICATION_DATA
typedef struct _MMC_CARD_SPECIFIC_SD_ERASE_DATA	MMC_CARD_SPECIFIC_SD_ERASE_DATA
typedef struct _MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA	MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA
typedef struct _MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA	MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA
typedef union _MMC_CARD_SPECIFIC_ERASE_DATA	MMC_CARD_SPECIFIC_ERASE_DATA
typedef struct _MMC_CARD_SPECIFIC_DATA	MMC_CARD_SPECIFIC_DATA
typedef struct _MMC_EXTENDED_CARD_SPECIFIC_DATA	MMC_EXTENDED_CARD_SPECIFIC_DATA
typedef struct _SD_STATUS_DATA	SD_STATUS_DATA
typedef struct _SD_SWITCH_DATA	SD_SWITCH_DATA
typedef struct _SD_CONFIGURATION_DATA	SD_CONFIGURATION_DATA
typedef struct _MMC_DEVICE	MMC_DEVICE
typedef struct _SDIO_CCCR	SDIO_CCCR
	Forward declared to satisfy MMCDevice.
typedef struct _SDIO_CIS	SDIO_CIS
	Forward declared to satisfy MMCDevice.
typedef struct _SDIO_TUPLE	SDIO_TUPLE
	Forward declared to satisfy MMCDevice.
typedef struct _SDIO_FUNCTION	SDIO_FUNCTION
	Forward declared to satisfy MMCDevice.
typedef uint32_t STDCALL(*	mmc_enumerate_cb) (MMC_DEVICE mmc, void data)
typedef uint32_t STDCALL(*	mmc_notification_cb) (DEVICE device, void data, uint32_t notification)
typedef uint32_t STDCALL(*	mmc_device_initialize_proc) (MMC_DEVICE *mmc)
typedef uint32_t STDCALL(*	mmc_device_deinitialize_proc) (MMC_DEVICE *mmc)
typedef uint32_t STDCALL(*	mmc_device_get_card_detect_proc) (MMC_DEVICE *mmc)
typedef uint32_t STDCALL(*	mmc_device_get_write_protect_proc) (MMC_DEVICE *mmc)
typedef uint32_t STDCALL(*	mmc_device_send_command_proc) (MMC_DEVICE mmc, MMC_COMMAND command)
typedef uint32_t STDCALL(*	mmc_device_set_ios_proc) (MMC_DEVICE *mmc)
typedef struct _SDIO_DRIVER	SDIO_DRIVER
	Forward declared to satisfy SDIOFunction.
typedef void STDCALL(*	sdio_interrupt_handler) (SDIO_FUNCTION *func)
typedef uint32_t STDCALL(*	sdio_function_enumerate_cb) (SDIO_FUNCTION func, void data)
typedef uint32_t STDCALL(*	sdio_driver_enumerate_cb) (SDIO_DRIVER driver, void data)
typedef uint32_t STDCALL(*	sdio_driver_bind_proc) (MMC_DEVICE mmc, SDIO_FUNCTION func)
typedef uint32_t STDCALL(*	sdio_driver_unbind_proc) (MMC_DEVICE mmc, SDIO_FUNCTION func)
typedef struct _SDHCI_ADMA2_DESCRIPTOR32	SDHCI_ADMA2_DESCRIPTOR32
typedef struct _SDHCI_ADMA2_DESCRIPTOR64	SDHCI_ADMA2_DESCRIPTOR64
typedef struct _SDHCI_ADMA2_DESCRIPTOR64_V4	SDHCI_ADMA2_DESCRIPTOR64_V4
typedef struct _SDHCI_HOST	SDHCI_HOST
typedef uint32_t STDCALL(*	sdhci_enumerate_cb) (SDHCI_HOST sdhci, void data)
typedef uint32_t STDCALL(*	sdhci_notification_cb) (DEVICE device, void data, uint32_t notification)
typedef uint32_t STDCALL(*	sdhci_host_start_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_stop_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_lock_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_unlock_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_signal_proc) (SDHCI_HOST *sdhci, SEMAPHORE_HANDLE semaphore)
typedef uint8_t STDCALL(*	sdhci_host_read_byte_proc) (SDHCI_HOST *sdhci, uint32_t reg)
typedef uint16_t STDCALL(*	sdhci_host_read_word_proc) (SDHCI_HOST *sdhci, uint32_t reg)
typedef uint32_t STDCALL(*	sdhci_host_read_long_proc) (SDHCI_HOST *sdhci, uint32_t reg)
typedef void STDCALL(*	sdhci_host_write_byte_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint8_t value)
typedef void STDCALL(*	sdhci_host_write_word_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint16_t value)
typedef void STDCALL(*	sdhci_host_write_long_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint32_t value)
typedef uint32_t STDCALL(*	sdhci_host_reset_proc) (SDHCI_HOST *sdhci, uint8_t mask)
typedef uint32_t STDCALL(*	sdhci_host_hardware_reset_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_set_power_proc) (SDHCI_HOST *sdhci, uint16_t power)
typedef uint32_t STDCALL(*	sdhci_host_set_clock_proc) (SDHCI_HOST *sdhci, uint32_t clock)
typedef uint32_t STDCALL(*	sdhci_host_set_timing_proc) (SDHCI_HOST *sdhci, uint32_t timing)
typedef uint32_t STDCALL(*	sdhci_host_set_buswidth_proc) (SDHCI_HOST *sdhci, uint32_t buswidth)
typedef uint32_t STDCALL(*	sdhci_host_set_clock_divider_proc) (SDHCI_HOST *sdhci, int index, uint32_t divider)
typedef uint32_t STDCALL(*	sdhci_host_set_control_register_proc) (SDHCI_HOST *sdhci)
typedef uint32_t STDCALL(*	sdhci_host_prepare_dma_proc) (SDHCI_HOST sdhci, MMC_COMMAND command)
typedef uint32_t STDCALL(*	sdhci_host_start_dma_proc) (SDHCI_HOST sdhci, MMC_COMMAND command)
typedef uint32_t STDCALL(*	sdhci_host_stop_dma_proc) (SDHCI_HOST sdhci, MMC_COMMAND command)
typedef uint32_t STDCALL(*	sdhci_host_setup_card_irq_proc) (SDHCI_HOST *sdhci, LONGBOOL enable)
typedef uint32_t STDCALL(*	sdhci_host_complete_card_irq_proc) (SDHCI_HOST *sdhci)

Functions
uint32_t STDCALL	mmc_start (void)
uint32_t STDCALL	mmc_stop (void)
void STDCALL	mmc_async_start (SDHCI_HOST *sdhci)
uint32_t STDCALL	mmc_device_read_blocks (MMC_DEVICE mmc, int64_t start, int64_t count, void buffer)
uint32_t STDCALL	mmc_device_write_blocks (MMC_DEVICE mmc, int64_t start, int64_t count, void buffer)
uint32_t STDCALL	mmc_device_erase_blocks (MMC_DEVICE *mmc, int64_t start, int64_t count)
uint32_t STDCALL	mmc_device_go_idle (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_set_clock (MMC_DEVICE *mmc, uint32_t clock)
uint32_t STDCALL	mmc_device_set_timing (MMC_DEVICE *mmc, uint32_t timing)
uint32_t STDCALL	mmc_device_set_bus_width (MMC_DEVICE *mmc, uint32_t width)
uint32_t STDCALL	mmc_device_set_block_length (MMC_DEVICE *mmc, uint32_t length)
uint32_t STDCALL	mmc_device_set_block_count (MMC_DEVICE *mmc, uint32_t count, BOOL relative)
uint32_t STDCALL	mmc_device_set_driver_stage (MMC_DEVICE *mmc, uint32_t driverstage)
uint32_t STDCALL	mmc_device_stop_transmission (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_select_card (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_deselect_card (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_switch (MMC_DEVICE *mmc, uint8_t setting, uint8_t index, uint8_t value, uint32_t timeout)
	Modifies an Extended CSD register for the specificed MMC device.
uint32_t STDCALL	mmc_device_switch_ex (MMC_DEVICE *mmc, uint8_t setting, uint8_t index, uint8_t value, uint32_t timeout, uint32_t timing, BOOL sendstatus, BOOL retrycrcerror)
	Modifies an Extended CSD register for the specificed MMC device.
uint32_t STDCALL	mmc_device_poll_for_busy (MMC_DEVICE *mmc, uint32_t timeout, uint32_t command)
	Poll the specified MMC device for command completion using busy status.
uint32_t STDCALL	mmc_device_poll_for_busy_ex (MMC_DEVICE *mmc, uint32_t timeout, uint32_t command, BOOL sendstatus, BOOL retrycrcerror)
	Poll the specified MMC device for command completion using busy status.
uint32_t STDCALL	mmc_device_send_card_status (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_send_operation_condition (MMC_DEVICE *mmc, BOOL probe)
uint32_t STDCALL	mmc_device_send_card_specific (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_decode_card_specific (MMC_DEVICE *mmc)
	Given a 128-bit response, decode to our card CSD structure.
uint32_t STDCALL	mmc_device_send_card_identification (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_send_all_card_identification (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_decode_card_identification (MMC_DEVICE *mmc)
	Given a 128-bit response, decode to our card CID structure.
uint32_t STDCALL	mmc_device_get_extended_card_specific (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_send_extended_card_specific (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_decode_extended_card_specific (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_set_relative_address (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_spi_set_crc (MMC_DEVICE *mmc, BOOL enable)
uint32_t STDCALL	mmc_device_spi_read_operation_condition (MMC_DEVICE *mmc, BOOL highcapacity)
uint32_t STDCALL	mmc_device_insert (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_remove (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_initialize (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_deinitialize (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_get_card_detect (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_get_write_protect (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_device_send_command (MMC_DEVICE mmc, MMC_COMMAND command)
uint32_t STDCALL	mmc_device_set_ios (MMC_DEVICE *mmc)
MMC_DEVICE *STDCALL	mmc_device_create (void)
	Create a new MMC entry.
MMC_DEVICE *STDCALL	mmc_device_create_ex (uint32_t size)
	Create a new MMC entry.
uint32_t STDCALL	mmc_device_destroy (MMC_DEVICE *mmc)
	Destroy an existing MMC entry.
uint32_t STDCALL	mmc_device_register (MMC_DEVICE *mmc)
	Register a new MMC in the MMC table.
uint32_t STDCALL	mmc_device_deregister (MMC_DEVICE *mmc)
	Deregister a MMC from the MMC table.
MMC_DEVICE *STDCALL	mmc_device_find (uint32_t mmcid)
MMC_DEVICE *STDCALL	mmc_device_find_by_device (DEVICE *device)
	Find an MMC/SD device by the matching DeviceData property.
MMC_DEVICE *STDCALL	mmc_device_find_by_name (const char *name)
MMC_DEVICE *STDCALL	mmc_device_find_by_description (const char *description)
uint32_t STDCALL	mmc_device_enumerate (mmc_enumerate_cb callback, void *data)
uint32_t STDCALL	mmc_device_notification (MMC_DEVICE mmc, mmc_notification_cb callback, void data, uint32_t notification, uint32_t flags)
uint32_t STDCALL	sd_device_switch (MMC_DEVICE mmc, int mode, int group, uint8_t value, void buffer)
uint32_t STDCALL	sd_device_switch_highspeed (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_set_bus_width (MMC_DEVICE *mmc, uint32_t width)
uint32_t STDCALL	sd_device_send_interface_condition (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_send_operation_condition (MMC_DEVICE *mmc, BOOL probe)
uint32_t STDCALL	sd_device_get_card_specific (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_decode_card_specific (MMC_DEVICE *mmc)
	Given a 128-bit response, decode to our card CSD structure.
uint32_t STDCALL	sd_device_get_card_identification (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_decode_card_identification (MMC_DEVICE *mmc)
	Given a 128-bit response, decode to our card CID structure.
uint32_t STDCALL	sd_device_send_sd_status (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_decode_sd_status (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_send_sd_switch (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_decode_sd_switch (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_send_sd_configuration (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_decode_sd_configuration (MMC_DEVICE *mmc)
	Given a 64-bit response, decode to our card SCR structure.
uint32_t STDCALL	sd_device_send_relative_address (MMC_DEVICE *mmc)
uint32_t STDCALL	sd_device_send_application_command (MMC_DEVICE mmc, MMC_COMMAND command)
uint32_t STDCALL	sdio_device_reset (MMC_DEVICE *mmc)
	Device Methods.
uint32_t STDCALL	sdio_device_enable_wide_bus (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_disable_wide_bus (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_enable_highspeed (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_switch_highspeed (MMC_DEVICE *mmc, BOOL enable)
uint32_t STDCALL	sdio_device_send_operation_condition (MMC_DEVICE *mmc, BOOL probe)
uint32_t STDCALL	sdio_device_read_write_direct (MMC_DEVICE mmc, BOOL write, uint32_t operation, uint32_t address, uint8_t input, uint8_t output)
uint32_t STDCALL	sdio_device_read_write_extended (MMC_DEVICE mmc, BOOL write, uint32_t operation, uint32_t address, BOOL increment, void buffer, uint32_t blockcount, uint32_t blocksize)
uint32_t STDCALL	sdio_device_read_byte (MMC_DEVICE mmc, uint32_t address, uint8_t output)
	Wrapper for reading a single byte from Function 0.
uint32_t STDCALL	sdio_device_write_byte (MMC_DEVICE *mmc, uint32_t address, uint8_t input)
	Wrapper for writing a single byte to Function 0.
uint32_t STDCALL	sdio_device_read_cccr (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_read_fbr (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_device_read_cis (MMC_DEVICE mmc, SDIO_FUNCTION func)
uint32_t STDCALL	sdio_device_read_common_cis (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_read_function_cis (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_device_process_interrupts (MMC_DEVICE *mmc)
uint32_t STDCALL	sdio_device_register_interrupt (MMC_DEVICE mmc, SDIO_FUNCTION func, sdio_interrupt_handler handler)
uint32_t STDCALL	sdio_device_deregister_interrupt (MMC_DEVICE mmc, SDIO_FUNCTION func)
uint32_t STDCALL	sdio_device_bind_functions (MMC_DEVICE *mmc)
	Attempt to bind SDIO functions on an MMC device to one of the registered drivers.
uint32_t STDCALL	sdio_device_unbind_functions (MMC_DEVICE mmc, SDIO_DRIVER driver)
	Unbind SDIO functions on an MMC device from a driver.
SDIO_FUNCTION *STDCALL	sdio_function_allocate (MMC_DEVICE *mmc, uint32_t number)
	Function Methods.
uint32_t STDCALL	sdio_function_release (SDIO_FUNCTION *func)
SDIO_FUNCTION *STDCALL	sdio_function_find (MMC_DEVICE *mmc, uint32_t number)
SDIO_FUNCTION *STDCALL	sdio_function_find_by_id (MMC_DEVICE *mmc, uint16_t vendorid, uint16_t deviceid)
uint32_t STDCALL	sdio_function_enumerate (MMC_DEVICE mmc, sdio_function_enumerate_cb callback, void data)
uint32_t STDCALL	sdio_function_bind (SDIO_FUNCTION func, SDIO_DRIVER driver)
uint32_t STDCALL	sdio_function_unbind (SDIO_FUNCTION func, SDIO_DRIVER driver)
uint32_t STDCALL	sdio_function_enable (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_function_disable (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_function_set_block_size (SDIO_FUNCTION *func, uint32_t blocksize)
uint32_t STDCALL	sdio_function_read_write_extended (SDIO_FUNCTION func, BOOL write, uint32_t address, BOOL increment, void buffer, uint32_t size)
	Perform an SDIO read or write to the specified function at the specified address Handles splitting any size read or write into multiple IO_RW_EXTENDED requests, accounting for maximum block sizes.
uint32_t STDCALL	sdio_function_read (SDIO_FUNCTION func, uint32_t address, void buffer, uint32_t size)
	Wrapper for reading multiple bytes from an SDIO function.
uint32_t STDCALL	sdio_function_write (SDIO_FUNCTION func, uint32_t address, void buffer, uint32_t size)
	Wrapper for writing multiple bytes to an SDIO function.
uint32_t STDCALL	sdio_function_read_byte (SDIO_FUNCTION func, uint32_t address, uint8_t output)
	Wrapper for reading a single byte from an SDIO function.
uint32_t STDCALL	sdio_function_write_byte (SDIO_FUNCTION *func, uint32_t address, uint8_t input)
	Wrapper for writing a single byte to an SDIO function.
uint32_t STDCALL	sdio_function_write_read_byte (SDIO_FUNCTION func, uint32_t address, uint8_t input, uint8_t output)
	Wrapper for performing a read after write (RAW) operation on an SDIO function.
uint32_t STDCALL	sdio_function_read_word (SDIO_FUNCTION func, uint32_t address, uint16_t output)
	Wrapper for reading a single word from an SDIO function.
uint32_t STDCALL	sdio_function_write_word (SDIO_FUNCTION *func, uint32_t address, uint16_t input)
	Wrapper for writing a single word to an SDIO function.
uint32_t STDCALL	sdio_function_read_long (SDIO_FUNCTION func, uint32_t address, uint32_t output)
	Wrapper for reading a single longword from an SDIO function.
uint32_t STDCALL	sdio_function_write_long (SDIO_FUNCTION *func, uint32_t address, uint32_t input)
	Wrapper for writing a single longword to an SDIO function.
uint32_t STDCALL	sdio_function_register_interrupt (SDIO_FUNCTION *func, sdio_interrupt_handler handler)
uint32_t STDCALL	sdio_function_deregister_interrupt (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_host_dispatch_interrupt (SDHCI_HOST *sdhci, BOOL irq, BOOL fiq)
	Host Methods.
SDIO_DRIVER *STDCALL	sdio_driver_create (void)
	Driver Methods.
SDIO_DRIVER *STDCALL	sdio_driver_create_ex (uint32_t size)
	Create a new SDIO Driver entry.
uint32_t STDCALL	sdio_driver_destroy (SDIO_DRIVER *driver)
	Destroy an existing SDIO Driver entry.
uint32_t STDCALL	sdio_driver_register (SDIO_DRIVER *driver)
	Register a new Driver in the SDIO Driver table.
uint32_t STDCALL	sdio_driver_deregister (SDIO_DRIVER *driver)
	Deregister a Driver from the SDIO Driver table.
SDIO_DRIVER *STDCALL	sdio_driver_find (uint32_t driverid)
	Find a driver by Id in the SDIO Driver table.
SDIO_DRIVER *STDCALL	sdio_driver_find_by_name (const char *name)
	Find a driver by name in the Driver table.
uint32_t STDCALL	sdio_driver_enumerate (sdio_driver_enumerate_cb callback, void *data)
uint32_t STDCALL	sdhci_host_reset (SDHCI_HOST *sdhci, uint8_t mask)
	Default software reset function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_hardware_reset (SDHCI_HOST *sdhci)
	Default hardware reset function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_power (SDHCI_HOST *sdhci, uint16_t power)
	Default set power function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_clock (SDHCI_HOST *sdhci, uint32_t clock)
	Default set clock function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_timing (SDHCI_HOST *sdhci, uint32_t timing)
	Default set timing function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_bus_width (SDHCI_HOST *sdhci, uint32_t buswidth)
	Default set bus width function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_prepare_dma (SDHCI_HOST sdhci, MMC_COMMAND command)
	Default DMA transfer prepare function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_start_dma (SDHCI_HOST sdhci, MMC_COMMAND command)
	Default DMA transfer start function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_stop_dma (SDHCI_HOST sdhci, MMC_COMMAND command)
	Default DMA transfer stop function for SDHCI host controllers.
void STDCALL	sdhci_host_complete_dma (DMA_REQUEST *request)
	Default DMA request completion callback for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_setup_card_irq (SDHCI_HOST *sdhci, LONGBOOL enable)
	Default Card IRQ setup function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_complete_card_irq (SDHCI_HOST *sdhci)
	Default Card IRQ completion function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_transfer_pio (SDHCI_HOST *sdhci)
	Default PIO transfer function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_transfer_dma (SDHCI_HOST *sdhci)
	Default DMA transfer function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_finish_command (SDHCI_HOST *sdhci)
	Default finish command function for SDHCI host controllers Called by Interrupt Command handler when an SDHCI_INT_RESPONSE is received.
uint32_t STDCALL	sdhci_host_finish_data (SDHCI_HOST *sdhci)
	Default finish data function for SDHCI host controllers Called by Interrupt Data handler when data is received.
uint32_t STDCALL	sdhci_host_command_interrupt (SDHCI_HOST sdhci, uint32_t interruptmask, uint32_t returnmask)
	Default command interrupt processing function for SDHCI host controllers Called by SDHCI controller interrupt handler when a command interrupt is received.
uint32_t STDCALL	sdhci_host_data_interrupt (SDHCI_HOST *sdhci, uint32_t interruptmask)
	Default data interrupt processing function for SDHCI host controllers Called by SDHCI controller interrupt handler when a data interrupt is received.
uint32_t STDCALL	sdhci_host_start (SDHCI_HOST *sdhci)
	Default host start function for SDHCI host controllers Called automatically to start each registered SDHCI controller when required.
uint32_t STDCALL	sdhci_host_stop (SDHCI_HOST *sdhci)
	Default host stop function for SDHCI host controllers Called automatically to stop each registered SDHCI controller when required.
uint32_t STDCALL	sdhci_host_lock (SDHCI_HOST *sdhci)
	Default host lock function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_unlock (SDHCI_HOST *sdhci)
	Default host unlock function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_signal (SDHCI_HOST *sdhci, SEMAPHORE_HANDLE semaphore)
	Default host semaphore signal function for SDHCI host controllers.
uint8_t STDCALL	sdhci_host_read_byte (SDHCI_HOST *sdhci, uint32_t reg)
	Default read byte function for SDHCI host controllers.
uint16_t STDCALL	sdhci_host_read_word (SDHCI_HOST *sdhci, uint32_t reg)
	Default read word function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_read_long (SDHCI_HOST *sdhci, uint32_t reg)
	Default read longword function for SDHCI host controllers.
void STDCALL	sdhci_host_write_byte (SDHCI_HOST *sdhci, uint32_t reg, uint8_t value)
	Default write byte function for SDHCI host controllers.
void STDCALL	sdhci_host_write_word (SDHCI_HOST *sdhci, uint32_t reg, uint16_t value)
	Default write word function for SDHCI host controllers.
void STDCALL	sdhci_host_write_long (SDHCI_HOST *sdhci, uint32_t reg, uint32_t value)
	Default write longword function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_clock_divider (SDHCI_HOST *sdhci, int index, uint32_t divider)
	Default set clock divider function for SDHCI host controllers.
uint32_t STDCALL	sdhci_host_set_control_register (SDHCI_HOST *sdhci)
	Default set control register function for SDHCI host controllers.
size_t STDCALL	sdhci_host_get_adma_address (SDHCI_HOST *sdhci)
	Get the DMA address of the ADMA table for the current request.
void STDCALL	sdhci_host_set_adma_address (SDHCI_HOST *sdhci, size_t address)
	Set the address of the transfer data in the Advanced DMA (ADMA) registers.
size_t STDCALL	sdhci_host_get_sdma_address (SDHCI_HOST sdhci, MMC_COMMAND command)
	Get the DMA address of the transfer data for the current request.
void STDCALL	sdhci_host_set_sdma_address (SDHCI_HOST *sdhci, size_t address)
	Set the address of the transfer data in the Simple DMA (SDMA) register.
void STDCALL	sdhci_host_write_adma_descriptor (SDHCI_HOST sdhci, void descriptor, uint16_t command, uint16_t len, size_t address)
	Write the properties to an ADMA descriptor.
SDHCI_HOST *STDCALL	sdhci_host_create (void)
	Create a new SDHCI entry.
SDHCI_HOST *STDCALL	sdhci_host_create_ex (uint32_t size)
	Create a new SDHCI entry.
uint32_t STDCALL	sdhci_host_destroy (SDHCI_HOST *sdhci)
	Destroy an existing SDHCI entry.
uint32_t STDCALL	sdhci_host_register (SDHCI_HOST *sdhci)
	Register a new SDHCI in the SDHCI table.
uint32_t STDCALL	sdhci_host_deregister (SDHCI_HOST *sdhci)
	Deregister a SDHCI from the SDHCI table.
SDHCI_HOST *STDCALL	sdhci_host_find (uint32_t sdhciid)
uint32_t STDCALL	sdhci_host_enumerate (sdhci_enumerate_cb callback, void *data)
uint32_t STDCALL	sdhci_host_notification (SDHCI_HOST sdhci, sdhci_notification_cb callback, void data, uint32_t notification, uint32_t flags)
uint32_t STDCALL	mmc_get_count (void)
	Get the current MMC count.
MMC_DEVICE *STDCALL	mmc_device_check (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_is_sd (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_is_sdio (MMC_DEVICE *mmc)
SDHCI_HOST *STDCALL	mmc_get_sdhci (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_get_cid_value (MMC_DEVICE *mmc, uint32_t version, uint32_t value)
	Extract a CID field value from the 128 bit Card Identification register.
uint32_t STDCALL	mmc_get_csd_value (MMC_DEVICE *mmc, uint32_t value)
	Extract a CSD field value from the 128 bit Card Specific register.
uint32_t STDCALL	mmc_extract_bits (void *buffer, uint32_t start, uint32_t size)
	Start is the starting bit to extract, Size is the number of bits to extract Start is the LSB so to extract 8 bits from 127 to 120 then Start would be 120 and Size would be 8.
uint32_t STDCALL	mmc_extract_bits_ex (void *buffer, uint32_t length, uint32_t start, uint32_t size)
	Length is the size of the buffer in LongWords, Start is the starting bit to extract, Size is the number of bits to extract Start is the LSB so to extract 8 bits from 127 to 120 then Start would be 120 and Size would be 8 For a 128 bit buffer (16 bytes) Length would be 4 For a 512 bit buffer (64 bytes) Length would be 16.
BOOL STDCALL	mmc_is_multi_command (uint16_t command)
BOOL STDCALL	mmc_is_non_removable (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_has_extended_csd (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_has_set_block_count (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_has_auto_block_count (MMC_DEVICE *mmc)
BOOL STDCALL	mmc_has_auto_command_stop (MMC_DEVICE *mmc)
uint32_t STDCALL	mmc_status_to_string (uint32_t status, char *string, uint32_t len)
	Translates an MMC status code into a string describing it.
uint32_t STDCALL	mmc_version_to_string (uint32_t version, char *string, uint32_t len)
	Translates an MMC version into a string.
uint32_t STDCALL	mmc_timing_to_string (uint32_t timing, char *string, uint32_t len)
	Translates an MMC timing into a string.
uint32_t STDCALL	mmc_bus_width_to_string (uint32_t buswidth, char *string, uint32_t len)
	Translates an MMC bus width into a string.
uint32_t STDCALL	mmc_driver_type_to_string (uint32_t drivertype, char *string, uint32_t len)
	Translates an MMC driver type into a string.
uint32_t STDCALL	mmc_signal_voltage_to_string (uint32_t signalvoltage, char *string, uint32_t len)
	Translates an MMC signal voltage into a string.
uint32_t STDCALL	mmc_device_type_to_string (uint32_t mmctype, char *string, uint32_t len)
uint32_t STDCALL	mmc_device_state_to_string (uint32_t mmcstate, char *string, uint32_t len)
uint32_t STDCALL	mmc_device_state_to_notification (uint32_t state)
	Convert a Device state value into the notification code for device notifications.
uint32_t STDCALL	sd_get_max_clock (MMC_DEVICE *mmc)
	Determine the Maximum Clock (DTR) for the current card.
uint32_t STDCALL	sd_get_cid_value (MMC_DEVICE *mmc, uint32_t value)
	Extract a CID field value from the 128 bit Card Identification register.
uint32_t STDCALL	sd_get_csd_value (MMC_DEVICE *mmc, uint32_t version, uint32_t value)
	Extract a CSD field value from the 128 bit Card Specific register.
uint32_t STDCALL	sd_get_scr_value (MMC_DEVICE *mmc, uint32_t value)
	Extract an SCR field value from the 64 bit SD Configuration register.
uint32_t STDCALL	sd_get_ssr_value (MMC_DEVICE *mmc, uint32_t value)
	Extract an SCR field value from the 512 bit SD Status register.
uint32_t STDCALL	sd_get_switch_value (MMC_DEVICE *mmc, uint32_t value)
	Extract a Switch field value from the 512 bit SD Switch status.
uint32_t STDCALL	sd_version_to_string (uint32_t version, char *string, uint32_t len)
	Translates an SD version into a string.
uint32_t STDCALL	sd_bus_width_to_string (uint32_t buswidth, char *string, uint32_t len)
	Translates an SD bus width into a string.
uint32_t STDCALL	sdio_driver_get_count (void)
	Get the current SDIO driver count.
SDIO_DRIVER *STDCALL	sdio_driver_check (SDIO_DRIVER *driver)
	Check if the supplied SDIO Driver is in the driver table.
uint32_t STDCALL	sdio_device_get_max_clock (MMC_DEVICE *mmc)
	Determine the Maximum Clock (DTR) for the current SDIO device.
MMC_DEVICE *STDCALL	sdio_function_get_mmc (SDIO_FUNCTION *func)
SDHCI_HOST *STDCALL	sdio_function_get_sdhci (SDIO_FUNCTION *func)
uint32_t STDCALL	sdio_version_to_string (uint32_t version, char *string, uint32_t len)
	Translates an SDIO version into a string.
uint32_t STDCALL	sdio_function_state_to_string (uint32_t sdiostate, char *string, uint32_t len)
uint32_t STDCALL	sdio_function_status_to_string (uint32_t sdiostatus, char *string, uint32_t len)
uint32_t STDCALL	sdio_function_state_to_notification (uint32_t state)
	Convert a Device state value into the notification code for device notifications.
uint32_t STDCALL	sdio_function_status_to_notification (uint32_t status)
	Convert a Device status value into the notification code for device notifications.
uint32_t STDCALL	sdhci_get_count (void)
	Get the current SDHCI count.
SDHCI_HOST *STDCALL	sdhci_host_check (SDHCI_HOST *sdhci)
	Check if the supplied SDHCI is in the SDHCI table.
BOOL STDCALL	sdhci_is_spi (SDHCI_HOST *sdhci)
BOOL STDCALL	sdhci_has_dma (SDHCI_HOST *sdhci)
BOOL STDCALL	sdhci_has_cmd23 (SDHCI_HOST *sdhci)
BOOL STDCALL	sdhci_auto_cmd12 (SDHCI_HOST *sdhci)
BOOL STDCALL	sdhci_auto_cmd23 (SDHCI_HOST *sdhci)
uint16_t STDCALL	sdhci_get_version (SDHCI_HOST *sdhci)
uint16_t STDCALL	sdhci_get_command (uint16_t command)
uint16_t STDCALL	sdhci_make_command (uint16_t command, uint16_t flags)
uint16_t STDCALL	sdhci_make_block_size (uint16_t dma, uint16_t blocksize)
uint32_t STDCALL	sdhci_version_to_string (uint32_t version, char *name, uint32_t len)
	Translate an SDHCI version into a string.
uint32_t STDCALL	sdhci_power_to_string (uint32_t power, char *name, uint32_t len)
	Translate an SDHCI power value into a string.
uint32_t STDCALL	sdhci_device_type_to_string (uint32_t sdhcitype, char *name, uint32_t len)
uint32_t STDCALL	sdhci_host_type_to_string (uint32_t sdhcitype, char *name, uint32_t len)
uint32_t STDCALL	sdhci_device_state_to_string (uint32_t sdhcistate, char *name, uint32_t len)
uint32_t STDCALL	sdhci_host_state_to_string (uint32_t sdhcistate, char *name, uint32_t len)
uint32_t STDCALL	sdhci_host_state_to_notification (uint32_t state)
	Convert a Host state value into the notification code for device notifications.

Variables
struct _SDHCI_ADMA2_DESCRIPTOR32	PACKED

Macro Definition Documentation

◆ MMC_NAME_PREFIX

#define MMC_NAME_PREFIX "MMC"

Name prefix for MMC Devices.

MMC specific constants

◆ MMC_DEVICE_DESCRIPTION

#define MMC_DEVICE_DESCRIPTION "MMC/SD Device"

Description of MMC/SD device.

◆ MMC_STORAGE_DESCRIPTION

#define MMC_STORAGE_DESCRIPTION "MMC/SD Storage Device"

Description of MMC/SD storage device.

◆ MMC_STATUS_TIMER_INTERVAL

#define MMC_STATUS_TIMER_INTERVAL 1000

◆ MMC_DEFAULT_BLOCKSIZE

#define MMC_DEFAULT_BLOCKSIZE 512

◆ MMC_DEFAULT_BLOCKSHIFT

#define MMC_DEFAULT_BLOCKSHIFT 9

◆ MMC_TYPE_NONE

#define MMC_TYPE_NONE 0

MMC Device Types

◆ MMC_TYPE_MMC

#define MMC_TYPE_MMC 1

An MMC specification card.

◆ MMC_TYPE_SD

#define MMC_TYPE_SD 2

An SD specification card.

◆ MMC_TYPE_SDIO

#define MMC_TYPE_SDIO 3

An SDIO specification card.

◆ MMC_TYPE_SD_COMBO

#define MMC_TYPE_SD_COMBO 4

An SD/SDIO combination card.

◆ MMC_TYPE_MAX

#define MMC_TYPE_MAX 4

◆ MMC_STATE_EJECTED

#define MMC_STATE_EJECTED 0

MMC Device States

◆ MMC_STATE_INSERTED

#define MMC_STATE_INSERTED 1

◆ MMC_STATE_MAX

#define MMC_STATE_MAX 1

◆ MMC_FLAG_NONE

#define MMC_FLAG_NONE 0x00000000

MMC Device Flags

◆ MMC_FLAG_CARD_PRESENT

#define MMC_FLAG_CARD_PRESENT 0x00000001

Card is present.

◆ MMC_FLAG_WRITE_PROTECT

#define MMC_FLAG_WRITE_PROTECT 0x00000002

Card is write protected.

◆ MMC_FLAG_HIGH_CAPACITY

#define MMC_FLAG_HIGH_CAPACITY 0x00000004

High Capacity (SDHC).

◆ MMC_FLAG_EXT_CAPACITY

#define MMC_FLAG_EXT_CAPACITY 0x00000008

Extended Capacity (SDXC).

◆ MMC_FLAG_UHS_I

#define MMC_FLAG_UHS_I 0x00000010

Ultra High Speed (UHS-I).

◆ MMC_FLAG_UHS_II

#define MMC_FLAG_UHS_II 0x00000020

Ultra High Speed (UHS-II).

◆ MMC_FLAG_BLOCK_ADDRESSED

#define MMC_FLAG_BLOCK_ADDRESSED 0x00000040

Block Addressed (SDHC/SDXC and others).

◆ MMC_FLAG_AUTO_BLOCK_COUNT

#define MMC_FLAG_AUTO_BLOCK_COUNT 0x00000080

Controller supports Auto CMD23 (Set Block Count).

◆ MMC_FLAG_AUTO_COMMAND_STOP

#define MMC_FLAG_AUTO_COMMAND_STOP 0x00000100

Controller supports Auto CMD12 (Stop Transmission).

◆ MMC_FLAG_DDR_MODE

#define MMC_FLAG_DDR_MODE 0x00000200

Device supports DDR mode.

◆ MMC_FLAG_NON_REMOVABLE

#define MMC_FLAG_NON_REMOVABLE 0x00000400

Device is non removable, only check for presence once.

◆ MMC_FLAG_SET_BLOCK_COUNT

#define MMC_FLAG_SET_BLOCK_COUNT 0x00000800

Device supports CMD23 (Set Block Count).

◆ MMC_STATUS_SUCCESS

#define MMC_STATUS_SUCCESS 0

Function successful.

MMC/SD/SDIO Status Codes

◆ MMC_STATUS_TIMEOUT

#define MMC_STATUS_TIMEOUT 1

The operation timed out.

◆ MMC_STATUS_NO_MEDIA

#define MMC_STATUS_NO_MEDIA 2

No media present in device.

◆ MMC_STATUS_HARDWARE_ERROR

#define MMC_STATUS_HARDWARE_ERROR 3

Hardware error of some form occurred.

◆ MMC_STATUS_INVALID_DATA

#define MMC_STATUS_INVALID_DATA 4

Invalid data was received.

◆ MMC_STATUS_INVALID_PARAMETER

#define MMC_STATUS_INVALID_PARAMETER 5

An invalid parameter was passed to the function.

◆ MMC_STATUS_INVALID_SEQUENCE

#define MMC_STATUS_INVALID_SEQUENCE 6

Invalid sequence encountered.

◆ MMC_STATUS_OUT_OF_MEMORY

#define MMC_STATUS_OUT_OF_MEMORY 7

No memory available for operation.

◆ MMC_STATUS_UNSUPPORTED_REQUEST

#define MMC_STATUS_UNSUPPORTED_REQUEST 8

The request is unsupported.

◆ MMC_STATUS_NOT_PROCESSED

#define MMC_STATUS_NOT_PROCESSED 9

The MMC transfer has not yet been processed.

◆ MMC_STATUS_OPERATION_FAILED

#define MMC_STATUS_OPERATION_FAILED 10

The operation was not able to be completed.

◆ MMC_STATUS_DEVICE_DETACHED

#define MMC_STATUS_DEVICE_DETACHED 11

SDIO device was detached.

◆ MMC_STATUS_DEVICE_UNSUPPORTED

#define MMC_STATUS_DEVICE_UNSUPPORTED 12

SDIO device is unsupported by the driver.

◆ MMC_STATUS_NOT_BOUND

#define MMC_STATUS_NOT_BOUND 13

SDIO device is not bound to a driver.

◆ MMC_STATUS_ALREADY_BOUND

#define MMC_STATUS_ALREADY_BOUND 14

SDIO device is already bound to a driver.

◆ MMC_STATUS_NOT_READY

#define MMC_STATUS_NOT_READY 15

The device is not ready yet, retry again later.

◆ SDIO_VERSION_SDIO

#define SDIO_VERSION_SDIO 0x00040000

MMC/SD/SDIO Versions

◆ SDIO_VERSION_1_00

#define SDIO_VERSION_1_00 (SDIO_VERSION_SDIO | 0x0100)

◆ SDIO_VERSION_1_10

#define SDIO_VERSION_1_10 (SDIO_VERSION_SDIO | 0x010a)

◆ SDIO_VERSION_1_20

#define SDIO_VERSION_1_20 (SDIO_VERSION_SDIO | 0x0114)

◆ SDIO_VERSION_2_00

#define SDIO_VERSION_2_00 (SDIO_VERSION_SDIO | 0x0200)

◆ SDIO_VERSION_3_00

#define SDIO_VERSION_3_00 (SDIO_VERSION_SDIO | 0x0300)

◆ SD_VERSION_SD

#define SD_VERSION_SD 0x00020000

◆ SD_VERSION_1_0

#define SD_VERSION_1_0 (SD_VERSION_SD | 0x0100)

◆ SD_VERSION_1_10

#define SD_VERSION_1_10 (SD_VERSION_SD | 0x010a)

◆ SD_VERSION_2

#define SD_VERSION_2 (SD_VERSION_SD | 0x0200)

◆ SD_VERSION_3

#define SD_VERSION_3 (SD_VERSION_SD | 0x0300)

◆ SD_VERSION_4

#define SD_VERSION_4 (SD_VERSION_SD | 0x0400)

◆ MMC_VERSION_MMC

#define MMC_VERSION_MMC 0x00010000

◆ MMC_VERSION_1_2

#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x0102)

◆ MMC_VERSION_1_4

#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x0104)

◆ MMC_VERSION_2_2

#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x0202)

◆ MMC_VERSION_3

#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x0300)

◆ MMC_VERSION_4

#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x0400)

◆ MMC_VERSION_4_1

#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x0401)

◆ MMC_VERSION_4_2

#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x0402)

◆ MMC_VERSION_4_3

#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x0403)

◆ MMC_VERSION_4_41

#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x0429)

◆ MMC_VERSION_4_5

#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x0405)

◆ MMC_VERSION_5_0

#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x0500)

◆ MMC_VERSION_5_1

#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x0501)

◆ MMC_VERSION_UNKNOWN

#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)

◆ MMC_CAP_4_BIT_DATA

#define MMC_CAP_4_BIT_DATA (1 << 0)

Can the host do 4 bit transfers.

MMC/SD Capabilities (From: /include/linux/mmc/host.h)

◆ MMC_CAP_MMC_HIGHSPEED

#define MMC_CAP_MMC_HIGHSPEED (1 << 1)

Can do MMC high-speed timing.

◆ MMC_CAP_SD_HIGHSPEED

#define MMC_CAP_SD_HIGHSPEED (1 << 2)

Can do SD high-speed timing.

◆ MMC_CAP_SDIO_IRQ

#define MMC_CAP_SDIO_IRQ (1 << 3)

Can signal pending SDIO IRQs.

◆ MMC_CAP_SPI

#define MMC_CAP_SPI (1 << 4)

Talks only SPI protocols.

◆ MMC_CAP_NEEDS_POLL

#define MMC_CAP_NEEDS_POLL (1 << 5)

Needs polling for card-detection.

◆ MMC_CAP_8_BIT_DATA

#define MMC_CAP_8_BIT_DATA (1 << 6)

Can the host do 8 bit transfers.

◆ MMC_CAP_AGGRESSIVE_PM

#define MMC_CAP_AGGRESSIVE_PM (1 << 7)

Suspend = (e)MMC/SD at idle.

◆ MMC_CAP_NONREMOVABLE

#define MMC_CAP_NONREMOVABLE (1 << 8)

Nonremovable eg. eMMC.

◆ MMC_CAP_WAIT_WHILE_BUSY

#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)

Waits while card is busy.

◆ MMC_CAP_3_3V_DDR

#define MMC_CAP_3_3V_DDR (1 << 11)

Host supports eMMC DDR 3.3V.

◆ MMC_CAP_1_8V_DDR

#define MMC_CAP_1_8V_DDR (1 << 12)

Host supports eMMC DDR 1.8V.

◆ MMC_CAP_1_2V_DDR

#define MMC_CAP_1_2V_DDR (1 << 13)

Host supports eMMC DDR 1.2V.

◆ MMC_CAP_DDR

#define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)

◆ MMC_CAP_POWER_OFF_CARD

#define MMC_CAP_POWER_OFF_CARD (1 << 14)

Can power off after boot.

◆ MMC_CAP_BUS_WIDTH_TEST

#define MMC_CAP_BUS_WIDTH_TEST (1 << 15)

CMD14/CMD19 bus width ok.

◆ MMC_CAP_UHS_SDR12

#define MMC_CAP_UHS_SDR12 (1 << 16)

Host supports UHS SDR12 mode.

◆ MMC_CAP_UHS_SDR25

#define MMC_CAP_UHS_SDR25 (1 << 17)

Host supports UHS SDR25 mode.

◆ MMC_CAP_UHS_SDR50

#define MMC_CAP_UHS_SDR50 (1 << 18)

Host supports UHS SDR50 mode.

◆ MMC_CAP_UHS_SDR104

#define MMC_CAP_UHS_SDR104 (1 << 19)

Host supports UHS SDR104 mode.

◆ MMC_CAP_UHS_DDR50

#define MMC_CAP_UHS_DDR50 (1 << 20)

Host supports UHS DDR50 mode.

◆ MMC_CAP_UHS

#define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50)

◆ MMC_CAP_SYNC_RUNTIME_PM

#define MMC_CAP_SYNC_RUNTIME_PM (1 << 21)

Synced runtime PM suspends.

◆ MMC_CAP_NEED_RSP_BUSY

#define MMC_CAP_NEED_RSP_BUSY (1 << 22)

Commands with R1B can't use R1.

◆ MMC_CAP_DRIVER_TYPE_A

#define MMC_CAP_DRIVER_TYPE_A (1 << 23)

Host supports Driver Type A.

◆ MMC_CAP_DRIVER_TYPE_C

#define MMC_CAP_DRIVER_TYPE_C (1 << 24)

Host supports Driver Type C.

◆ MMC_CAP_DRIVER_TYPE_D

#define MMC_CAP_DRIVER_TYPE_D (1 << 25)

Host supports Driver Type D.

◆ MMC_CAP_DONE_COMPLETE

#define MMC_CAP_DONE_COMPLETE (1 << 27)

RW reqs can be completed within mmc_request_done().

◆ MMC_CAP_CD_WAKE

#define MMC_CAP_CD_WAKE (1 << 28)

Enable card detect wake.

◆ MMC_CAP_CMD_DURING_TFR

#define MMC_CAP_CMD_DURING_TFR (1 << 29)

Commands during data transfer.

◆ MMC_CAP_CMD23

#define MMC_CAP_CMD23 (1 << 30)

CMD23 supported.

◆ MMC_CAP_HW_RESET

#define MMC_CAP_HW_RESET (1 << 31)

Reset the eMMC card via RST_n.

◆ MMC_CAP2_BOOTPART_NOACC

#define MMC_CAP2_BOOTPART_NOACC (1 << 0)

Boot partition no access.

MMC/SD Capabilities2 (From: /include/linux/mmc/host.h)

◆ MMC_CAP2_FULL_PWR_CYCLE

#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2)

Can do full power cycle.

◆ MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND

#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3)

Can do full power cycle in suspend.

◆ MMC_CAP2_HS200_1_8V_SDR

#define MMC_CAP2_HS200_1_8V_SDR (1 << 5)

Can support HS200 1.8V.

◆ MMC_CAP2_HS200_1_2V_SDR

#define MMC_CAP2_HS200_1_2V_SDR (1 << 6)

Can support HS200 1.2V.

◆ MMC_CAP2_HS200

#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR)

◆ MMC_CAP2_CD_ACTIVE_HIGH

#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10)

Card-detect signal active high.

◆ MMC_CAP2_RO_ACTIVE_HIGH

#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11)

Write-protect signal active high.

◆ MMC_CAP2_NO_PRESCAN_POWERUP

#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14)

Don't power up before scan.

◆ MMC_CAP2_HS400_1_8V

#define MMC_CAP2_HS400_1_8V (1 << 15)

Can support HS400 1.8V.

◆ MMC_CAP2_HS400_1_2V

#define MMC_CAP2_HS400_1_2V (1 << 16)

Can support HS400 1.2V.

◆ MMC_CAP2_HS400

#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V)

◆ MMC_CAP2_HSX00_1_8V

#define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)

◆ MMC_CAP2_HSX00_1_2V

#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)

◆ MMC_CAP2_SDIO_IRQ_NOTHREAD

#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)

Don't create a thread to poll for SDIO IRQ.

◆ MMC_CAP2_NO_WRITE_PROTECT

#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18)

No physical write protect pin, assume that card is always read-write.

◆ MMC_CAP2_NO_SDIO

#define MMC_CAP2_NO_SDIO (1 << 19)

Do not send SDIO commands during initialization.

◆ MMC_CAP2_HS400_ES

#define MMC_CAP2_HS400_ES (1 << 20)

Host supports enhanced strobe.

◆ MMC_CAP2_NO_SD

#define MMC_CAP2_NO_SD (1 << 21)

Do not send SD commands during initialization.

◆ MMC_CAP2_NO_MMC

#define MMC_CAP2_NO_MMC (1 << 22)

Do not send = (e)MMC commands during initialization.

◆ MMC_CAP2_CQE

#define MMC_CAP2_CQE (1 << 23)

Has eMMC command queue engine.

◆ MMC_CAP2_CQE_DCMD

#define MMC_CAP2_CQE_DCMD (1 << 24)

CQE can issue a direct command.

◆ MMC_CAP2_AVOID_3_3V

#define MMC_CAP2_AVOID_3_3V (1 << 25)

Host must negotiate down from 3.3V.

◆ MMC_CAP2_MERGE_CAPABLE

#define MMC_CAP2_MERGE_CAPABLE (1 << 26)

Host can merge a segment over the segment size.

◆ MMC_DATA_READ

#define MMC_DATA_READ 1

MMC/SD Directions

◆ MMC_DATA_WRITE

#define MMC_DATA_WRITE 2

◆ MMC_BUS_WIDTH_1

#define MMC_BUS_WIDTH_1 0

MMC/SD Bus Widths

◆ MMC_BUS_WIDTH_4

#define MMC_BUS_WIDTH_4 2

◆ MMC_BUS_WIDTH_8

#define MMC_BUS_WIDTH_8 3

◆ MMC_BUS_SPEED_DEFAULT

#define MMC_BUS_SPEED_DEFAULT 0

MMC Bus Speeds (Hz)

◆ MMC_BUS_SPEED_HS26

#define MMC_BUS_SPEED_HS26 26000000

◆ MMC_BUS_SPEED_HS52

#define MMC_BUS_SPEED_HS52 52000000

◆ MMC_BUS_SPEED_DDR

#define MMC_BUS_SPEED_DDR 52000000

◆ MMC_BUS_SPEED_HS200

#define MMC_BUS_SPEED_HS200 200000000

◆ MMC_TIMING_LEGACY

#define MMC_TIMING_LEGACY 0

MMC/SD Timing (From: /include/linux/mmc/host.h)

◆ MMC_TIMING_MMC_HS

#define MMC_TIMING_MMC_HS 1

◆ MMC_TIMING_SD_HS

#define MMC_TIMING_SD_HS 2

◆ MMC_TIMING_UHS_SDR12

#define MMC_TIMING_UHS_SDR12 3

◆ MMC_TIMING_UHS_SDR25

#define MMC_TIMING_UHS_SDR25 4

◆ MMC_TIMING_UHS_SDR50

#define MMC_TIMING_UHS_SDR50 5

◆ MMC_TIMING_UHS_SDR104

#define MMC_TIMING_UHS_SDR104 6

◆ MMC_TIMING_UHS_DDR50

#define MMC_TIMING_UHS_DDR50 7

◆ MMC_TIMING_MMC_DDR52

#define MMC_TIMING_MMC_DDR52 8

◆ MMC_TIMING_MMC_HS200

#define MMC_TIMING_MMC_HS200 9

◆ MMC_TIMING_MMC_HS400

#define MMC_TIMING_MMC_HS400 10

◆ MMC_SIGNAL_VOLTAGE_330

#define MMC_SIGNAL_VOLTAGE_330 0

MMC/SD Signal Voltage (From: /include/linux/mmc/host.h)

◆ MMC_SIGNAL_VOLTAGE_180

#define MMC_SIGNAL_VOLTAGE_180 1

◆ MMC_SIGNAL_VOLTAGE_120

#define MMC_SIGNAL_VOLTAGE_120 2

◆ MMC_SET_DRIVER_TYPE_B

#define MMC_SET_DRIVER_TYPE_B 0

MMC/SD Driver Type (From: /include/linux/mmc/host.h)

◆ MMC_SET_DRIVER_TYPE_A

#define MMC_SET_DRIVER_TYPE_A 1

◆ MMC_SET_DRIVER_TYPE_C

#define MMC_SET_DRIVER_TYPE_C 2

◆ MMC_SET_DRIVER_TYPE_D

#define MMC_SET_DRIVER_TYPE_D 3

◆ MMC_CMD_GO_IDLE_STATE

#define MMC_CMD_GO_IDLE_STATE 0

MMC Commands (From: /include/linux/mmc/mmc.h) Class 1

◆ MMC_CMD_SEND_OP_COND

#define MMC_CMD_SEND_OP_COND 1

◆ MMC_CMD_ALL_SEND_CID

#define MMC_CMD_ALL_SEND_CID 2

◆ MMC_CMD_SET_RELATIVE_ADDR

#define MMC_CMD_SET_RELATIVE_ADDR 3

◆ MMC_CMD_SET_DSR

#define MMC_CMD_SET_DSR 4

◆ MMC_CMD_SLEEP_AWAKE

#define MMC_CMD_SLEEP_AWAKE 5

◆ MMC_CMD_SWITCH

#define MMC_CMD_SWITCH 6

◆ MMC_CMD_SELECT_CARD

#define MMC_CMD_SELECT_CARD 7

◆ MMC_CMD_SEND_EXT_CSD

#define MMC_CMD_SEND_EXT_CSD 8

◆ MMC_CMD_SEND_CSD

#define MMC_CMD_SEND_CSD 9

◆ MMC_CMD_SEND_CID

#define MMC_CMD_SEND_CID 10

◆ MMC_CMD_READ_DAT_UNTIL_STOP

#define MMC_CMD_READ_DAT_UNTIL_STOP 11

◆ MMC_CMD_STOP_TRANSMISSION

#define MMC_CMD_STOP_TRANSMISSION 12

◆ MMC_CMD_SEND_STATUS

#define MMC_CMD_SEND_STATUS 13

◆ MMC_CMD_BUS_TEST_R

#define MMC_CMD_BUS_TEST_R 14

◆ MMC_CMD_GO_INACTIVE_STATE

#define MMC_CMD_GO_INACTIVE_STATE 15

◆ MMC_CMD_BUS_TEST_W

#define MMC_CMD_BUS_TEST_W 19

◆ MMC_CMD_SPI_READ_OCR

#define MMC_CMD_SPI_READ_OCR 58

◆ MMC_CMD_SPI_CRC_ON_OFF

#define MMC_CMD_SPI_CRC_ON_OFF 59

◆ MMC_CMD_SET_BLOCKLEN

#define MMC_CMD_SET_BLOCKLEN 16

Class 2

◆ MMC_CMD_READ_SINGLE_BLOCK

#define MMC_CMD_READ_SINGLE_BLOCK 17

◆ MMC_CMD_READ_MULTIPLE_BLOCK

#define MMC_CMD_READ_MULTIPLE_BLOCK 18

◆ MMC_CMD_SEND_TUNING_BLOCK

#define MMC_CMD_SEND_TUNING_BLOCK 19

◆ MMC_CMD_SEND_TUNING_BLOCK_HS200

#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21

◆ MMC_CMD_WRITE_DAT_UNTIL_STOP

#define MMC_CMD_WRITE_DAT_UNTIL_STOP 20

Class 3

◆ MMC_CMD_SET_BLOCK_COUNT

#define MMC_CMD_SET_BLOCK_COUNT 23

Class 4

◆ MMC_CMD_WRITE_SINGLE_BLOCK

#define MMC_CMD_WRITE_SINGLE_BLOCK 24

◆ MMC_CMD_WRITE_MULTIPLE_BLOCK

#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25

◆ MMC_CMD_PROGRAM_CID

#define MMC_CMD_PROGRAM_CID 26

◆ MMC_CMD_PROGRAM_CSD

#define MMC_CMD_PROGRAM_CSD 27

◆ MMC_CMD_SET_WRITE_PROT

#define MMC_CMD_SET_WRITE_PROT 28

Class 6

◆ MMC_CMD_CLR_WRITE_PROT

#define MMC_CMD_CLR_WRITE_PROT 29

◆ MMC_CMD_SEND_WRITE_PROT

#define MMC_CMD_SEND_WRITE_PROT 30

◆ MMC_CMD_ERASE_GROUP_START

#define MMC_CMD_ERASE_GROUP_START 35

Class 5

◆ MMC_CMD_ERASE_GROUP_END

#define MMC_CMD_ERASE_GROUP_END 36

◆ MMC_CMD_ERASE

#define MMC_CMD_ERASE 38

◆ MMC_CMD_FAST_IO

#define MMC_CMD_FAST_IO 39

Class 9

◆ MMC_CMD_GO_IRQ_STATE

#define MMC_CMD_GO_IRQ_STATE 40

◆ MMC_CMD_LOCK_UNLOCK

#define MMC_CMD_LOCK_UNLOCK 42

Class 7

◆ MMC_CMD_APP_CMD

#define MMC_CMD_APP_CMD 55

Class 8

◆ MMC_CMD_GEN_CMD

#define MMC_CMD_GEN_CMD 56

◆ MMC_CMD_RES_MAN

#define MMC_CMD_RES_MAN 62

◆ MMC_CMD62_ARG1

#define MMC_CMD62_ARG1 0xEFAC62EC

◆ MMC_CMD62_ARG2

#define MMC_CMD62_ARG2 0x00CBAEA7

◆ MMC_RSP_PRESENT

#define MMC_RSP_PRESENT (1 << 0)

MMC Response Types (From: /include/linux/mmc/mmc.h) Native

◆ MMC_RSP_136

#define MMC_RSP_136 (1 << 1)

136 bit response

◆ MMC_RSP_CRC

#define MMC_RSP_CRC (1 << 2)

Expect valid crc.

◆ MMC_RSP_BUSY

#define MMC_RSP_BUSY (1 << 3)

Card may send busy.

◆ MMC_RSP_OPCODE

#define MMC_RSP_OPCODE (1 << 4)

Response contains opcode.

◆ MMC_RSP_NONE

#define MMC_RSP_NONE (0)

These are the native response types, and correspond to valid bit patterns of the above flags. One additional valid pattern is all zeros, which means we don't expect a response

◆ MMC_RSP_R1

#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

◆ MMC_RSP_R1B

#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)

◆ MMC_RSP_R2

#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)

◆ MMC_RSP_R3

#define MMC_RSP_R3 (MMC_RSP_PRESENT)

◆ MMC_RSP_R4

#define MMC_RSP_R4 (MMC_RSP_PRESENT)

◆ MMC_RSP_R5

#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

◆ MMC_RSP_R6

#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

◆ MMC_RSP_R7

#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

◆ MMC_CMD_MASK

#define MMC_CMD_MASK (3 << 5)

Non-SPI Command Type Flags

◆ MMC_CMD_AC

#define MMC_CMD_AC (0 << 5)

Addressed Command, no Data.

◆ MMC_CMD_ADTC

#define MMC_CMD_ADTC (1 << 5)

Addressed Data Transfer Command.

◆ MMC_CMD_BC

#define MMC_CMD_BC (2 << 5)

Broadcast Command, no Response.

◆ MMC_CMD_BCR

#define MMC_CMD_BCR (3 << 5)

Broadcast Command with Response.

◆ MMC_RSP_SPI_S1

#define MMC_RSP_SPI_S1 (1 << 7)

One status byte.

SPI

◆ MMC_RSP_SPI_S2

#define MMC_RSP_SPI_S2 (1 << 8)

Second byte.

◆ MMC_RSP_SPI_B4

#define MMC_RSP_SPI_B4 (1 << 9)

Four data bytes.

◆ MMC_RSP_SPI_BUSY

#define MMC_RSP_SPI_BUSY (1 << 10)

Card may send busy.

◆ MMC_RSP_SPI_R1

#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)

These are the SPI response types for MMC, SD, and SDIO cards. Commands return R1, with maybe more info. Zero is an error type, callers must always provide the appropriate MMC_RSP_SPI_Rx flags

◆ MMC_RSP_SPI_R1B

#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1 | MMC_RSP_SPI_BUSY)

◆ MMC_RSP_SPI_R2

#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1 | MMC_RSP_SPI_S2)

◆ MMC_RSP_SPI_R3

#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)

◆ MMC_RSP_SPI_R4

#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)

◆ MMC_RSP_SPI_R5

#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1 | MMC_RSP_SPI_S2)

◆ MMC_RSP_SPI_R7

#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)

◆ MMC_RSP_R1_OUT_OF_RANGE

#define MMC_RSP_R1_OUT_OF_RANGE (1 << 31)

MMC Response Values R1 - MMC status in R1, for native mode (SPI bits are different)

◆ MMC_RSP_R1_ADDRESS_ERROR

#define MMC_RSP_R1_ADDRESS_ERROR (1 << 30)

◆ MMC_RSP_R1_BLOCK_LEN_ERROR

#define MMC_RSP_R1_BLOCK_LEN_ERROR (1 << 29)

◆ MMC_RSP_R1_ERASE_SEQ_ERROR

#define MMC_RSP_R1_ERASE_SEQ_ERROR (1 << 28)

◆ MMC_RSP_R1_ERASE_PARAM

#define MMC_RSP_R1_ERASE_PARAM (1 << 27)

◆ MMC_RSP_R1_WP_VIOLATION

#define MMC_RSP_R1_WP_VIOLATION (1 << 26)

◆ MMC_RSP_R1_CARD_IS_LOCKED

#define MMC_RSP_R1_CARD_IS_LOCKED (1 << 25)

◆ MMC_RSP_R1_LOCK_UNLOCK_FAILED

#define MMC_RSP_R1_LOCK_UNLOCK_FAILED (1 << 24)

◆ MMC_RSP_R1_COM_CRC_ERROR

#define MMC_RSP_R1_COM_CRC_ERROR (1 << 23)

◆ MMC_RSP_R1_ILLEGAL_COMMAND

#define MMC_RSP_R1_ILLEGAL_COMMAND (1 << 22)

◆ MMC_RSP_R1_CARD_ECC_FAILED

#define MMC_RSP_R1_CARD_ECC_FAILED (1 << 21)

◆ MMC_RSP_R1_CC_ERROR

#define MMC_RSP_R1_CC_ERROR (1 << 20)

◆ MMC_RSP_R1_ERROR

#define MMC_RSP_R1_ERROR (1 << 19)

◆ MMC_RSP_R1_UNDERRUN

#define MMC_RSP_R1_UNDERRUN (1 << 18)

◆ MMC_RSP_R1_OVERRUN

#define MMC_RSP_R1_OVERRUN (1 << 17)

◆ MMC_RSP_R1_CID_CSD_OVERWRITE

#define MMC_RSP_R1_CID_CSD_OVERWRITE (1 << 16)

◆ MMC_RSP_R1_WP_ERASE_SKIP

#define MMC_RSP_R1_WP_ERASE_SKIP (1 << 15)

◆ MMC_RSP_R1_CARD_ECC_DISABLED

#define MMC_RSP_R1_CARD_ECC_DISABLED (1 << 14)

◆ MMC_RSP_R1_ERASE_RESET

#define MMC_RSP_R1_ERASE_RESET (1 << 13)

◆ MMC_RSP_R1_READY_FOR_DATA

#define MMC_RSP_R1_READY_FOR_DATA (1 << 8)

MMC_RSP_R1_STATUS(x) (x & 0xFFFFE000) MMC_RSP_R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)

◆ MMC_RSP_R1_SWITCH_ERROR

#define MMC_RSP_R1_SWITCH_ERROR (1 << 7)

◆ MMC_RSP_R1_EXCEPTION_EVENT

#define MMC_RSP_R1_EXCEPTION_EVENT (1 << 6)

◆ MMC_RSP_R1_APP_CMD

#define MMC_RSP_R1_APP_CMD (1 << 5)

◆ MMC_RSP_R1_AKE_SEQ_ERROR

#define MMC_RSP_R1_AKE_SEQ_ERROR (1 << 3)

◆ MMC_RSP_R1_SPI_IDLE

#define MMC_RSP_R1_SPI_IDLE (1 << 0)

R1 SPI - MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS. R1 is the low order byte, R2 is the next highest byte, when present

◆ MMC_RSP_R1_SPI_ERASE_RESET

#define MMC_RSP_R1_SPI_ERASE_RESET (1 << 1)

◆ MMC_RSP_R1_SPI_ILLEGAL_COMMAND

#define MMC_RSP_R1_SPI_ILLEGAL_COMMAND (1 << 2)

◆ MMC_RSP_R1_SPI_COM_CRC

#define MMC_RSP_R1_SPI_COM_CRC (1 << 3)

◆ MMC_RSP_R1_SPI_ERASE_SEQ

#define MMC_RSP_R1_SPI_ERASE_SEQ (1 << 4)

◆ MMC_RSP_R1_SPI_ADDRESS

#define MMC_RSP_R1_SPI_ADDRESS (1 << 5)

◆ MMC_RSP_R1_SPI_PARAMETER

#define MMC_RSP_R1_SPI_PARAMETER (1 << 6)

◆ MMC_RSP_R2_SPI_CARD_LOCKED

#define MMC_RSP_R2_SPI_CARD_LOCKED (1 << 8)

R1 bit 7 is always zero R2 SPI - See above

◆ MMC_RSP_R2_SPI_WP_ERASE_SKIP

#define MMC_RSP_R2_SPI_WP_ERASE_SKIP (1 << 9)

Or lock/unlock fail.

◆ MMC_RSP_R2_SPI_LOCK_UNLOCK_FAIL

#define MMC_RSP_R2_SPI_LOCK_UNLOCK_FAIL MMC_RSP_R2_SPI_WP_ERASE_SKIP

◆ MMC_RSP_R2_SPI_ERROR

#define MMC_RSP_R2_SPI_ERROR (1 << 10)

◆ MMC_RSP_R2_SPI_CC_ERROR

#define MMC_RSP_R2_SPI_CC_ERROR (1 << 11)

◆ MMC_RSP_R2_SPI_CARD_ECC_ERROR

#define MMC_RSP_R2_SPI_CARD_ECC_ERROR (1 << 12)

◆ MMC_RSP_R2_SPI_WP_VIOLATION

#define MMC_RSP_R2_SPI_WP_VIOLATION (1 << 13)

◆ MMC_RSP_R2_SPI_ERASE_PARAM

#define MMC_RSP_R2_SPI_ERASE_PARAM (1 << 14)

◆ MMC_RSP_R2_SPI_OUT_OF_RANGE

#define MMC_RSP_R2_SPI_OUT_OF_RANGE (1 << 15)

Or CSD overwrite.

◆ MMC_RSP_R2_SPI_CSD_OVERWRITE

#define MMC_RSP_R2_SPI_CSD_OVERWRITE MMC_RSP_R2_SPI_OUT_OF_RANGE

◆ MMC_OCR_BUSY

#define MMC_OCR_BUSY 0x80000000

Busy Status - 0 = Initializing / 1 = Initialization Complete.

MMC Operation Condition Register (OCR) values

◆ MMC_OCR_HCS

#define MMC_OCR_HCS 0x40000000

Card Capacity Status - 0 = SDSC / 1 = SDHC or SDXC.

◆ MMC_OCR_UHS_II

#define MMC_OCR_UHS_II 0x20000000

UHS-II Card Status - 0 = Non UHS-II Card / 1 = UHS-II Card.

◆ MMC_OCR_S18A

#define MMC_OCR_S18A 0x01000000

Switching to 1.8V Accepted - 0 = Continue current voltage signaling / 1 = Ready for switching signal voltage.

◆ MMC_OCR_VOLTAGE_MASK

#define MMC_OCR_VOLTAGE_MASK 0x007FFF80

◆ MMC_OCR_ACCESS_MODE

#define MMC_OCR_ACCESS_MODE 0x60000000

◆ MMC_CARD_STATUS_MASK

#define MMC_CARD_STATUS_MASK (~0x0206BF7F)

MMC Card Status Register (CSR) values Note: These map to the Native mode R1 response values

◆ MMC_CARD_STATUS_ERROR

#define MMC_CARD_STATUS_ERROR (1 << 19)

◆ MMC_CARD_STATUS_CURRENT_STATE

#define MMC_CARD_STATUS_CURRENT_STATE (0x0F << 9)

See MMC_CURRENT_STATE_ definitions below.

◆ MMC_CARD_STATUS_READY_FOR_DATA

#define MMC_CARD_STATUS_READY_FOR_DATA (1 << 8)

◆ MMC_CARD_STATUS_SWITCH_ERROR

#define MMC_CARD_STATUS_SWITCH_ERROR (1 << 7)

◆ MMC_CURRENT_STATE_IDLE

#define MMC_CURRENT_STATE_IDLE (0 << 9)

MMC Current State values (From Card Status Register or R1 Response)

◆ MMC_CURRENT_STATE_READY

#define MMC_CURRENT_STATE_READY (1 << 9)

◆ MMC_CURRENT_STATE_IDENT

#define MMC_CURRENT_STATE_IDENT (2 << 9)

◆ MMC_CURRENT_STATE_STBY

#define MMC_CURRENT_STATE_STBY (3 << 9)

◆ MMC_CURRENT_STATE_TRAN

#define MMC_CURRENT_STATE_TRAN (4 << 9)

◆ MMC_CURRENT_STATE_DATA

#define MMC_CURRENT_STATE_DATA (5 << 9)

◆ MMC_CURRENT_STATE_RCV

#define MMC_CURRENT_STATE_RCV (6 << 9)

◆ MMC_CURRENT_STATE_PRG

#define MMC_CURRENT_STATE_PRG (7 << 9)

◆ MMC_CURRENT_STATE_DIS

#define MMC_CURRENT_STATE_DIS (8 << 9)

◆ MMC_CID_MID

#define MMC_CID_MID 1

Manufacturer ID.

MMC Card Identification Data (CID) values MMC CID Fields

◆ MMC_CID_OID

#define MMC_CID_OID 2

OEM/Application ID.

◆ MMC_CID_PNM0

#define MMC_CID_PNM0 3

Product name (Byte 0).

◆ MMC_CID_PNM1

#define MMC_CID_PNM1 4

Product name (Byte 1).

◆ MMC_CID_PNM2

#define MMC_CID_PNM2 5

Product name (Byte 2).

◆ MMC_CID_PNM3

#define MMC_CID_PNM3 6

Product name (Byte 3).

◆ MMC_CID_PNM4

#define MMC_CID_PNM4 7

Product name (Byte 4).

◆ MMC_CID_PNM5

#define MMC_CID_PNM5 8

Product name (Byte 5).

◆ MMC_CID_PNM6

#define MMC_CID_PNM6 9

Product name (Byte 6).

◆ MMC_CID_PRV

#define MMC_CID_PRV 10

Product revision.

◆ MMC_CID_HRV

#define MMC_CID_HRV 11

Hardware revision.

◆ MMC_CID_FRV

#define MMC_CID_FRV 12

Firmware revision.

◆ MMC_CID_PSN

#define MMC_CID_PSN 13

Product serial number.

◆ MMC_CID_MDT_YEAR

#define MMC_CID_MDT_YEAR 14

Manufacturing year.

◆ MMC_CID_MDT_MONTH

#define MMC_CID_MDT_MONTH 15

Manufacturing month.

◆ MMC_CID_CRC

#define MMC_CID_CRC 16

CRC.

◆ MMC_CSD_STRUCTURE

#define MMC_CSD_STRUCTURE 1

MMC Card Specific Data (CSD) values MMC CSD Fields

◆ MMC_CSD_SPECVER

#define MMC_CSD_SPECVER 2

MMC/eMMC Only.

◆ MMC_CSD_TAAC_UNIT

#define MMC_CSD_TAAC_UNIT 3

◆ MMC_CSD_TAAC_VALUE

#define MMC_CSD_TAAC_VALUE 4

◆ MMC_CSD_NSAC

#define MMC_CSD_NSAC 5

◆ MMC_CSD_TRAN_SPEED_UNIT

#define MMC_CSD_TRAN_SPEED_UNIT 6

◆ MMC_CSD_TRAN_SPEED_VALUE

#define MMC_CSD_TRAN_SPEED_VALUE 37

◆ MMC_CSD_CCC

#define MMC_CSD_CCC 7

◆ MMC_CSD_READ_BL_LEN

#define MMC_CSD_READ_BL_LEN 8

◆ MMC_CSD_READ_BL_PARTIAL

#define MMC_CSD_READ_BL_PARTIAL 9

◆ MMC_CSD_WRITE_BLK_MISALIGN

#define MMC_CSD_WRITE_BLK_MISALIGN 10

◆ MMC_CSD_READ_BLK_MISALIGN

#define MMC_CSD_READ_BLK_MISALIGN 11

◆ MMC_CSD_DSR_IMP

#define MMC_CSD_DSR_IMP 12

◆ MMC_CSD_C_SIZE

#define MMC_CSD_C_SIZE 13

◆ MMC_CSD_VDD_R_CURR_MIN

#define MMC_CSD_VDD_R_CURR_MIN 14

◆ MMC_CSD_VDD_R_CURR_MAX

#define MMC_CSD_VDD_R_CURR_MAX 15

◆ MMC_CSD_VDD_W_CURR_MIN

#define MMC_CSD_VDD_W_CURR_MIN 16

◆ MMC_CSD_VDD_W_CURR_MAX

#define MMC_CSD_VDD_W_CURR_MAX 17

◆ MMC_CSD_C_SIZE_MULT

#define MMC_CSD_C_SIZE_MULT 18

◆ MMC_CSD_ERASE_BLK_EN

#define MMC_CSD_ERASE_BLK_EN 19

SD Specification.

◆ MMC_CSD_SECTOR_SIZE

#define MMC_CSD_SECTOR_SIZE 20

MMC/eMMC Specification / SD Specification.

◆ MMC_CSD_ERASE_GRP_SIZE

#define MMC_CSD_ERASE_GRP_SIZE 21

MMC/eMMC Specification.

◆ MMC_CSD_ERASE_GRP_MULT

#define MMC_CSD_ERASE_GRP_MULT 22

MMC/eMMC Specification.

◆ MMC_CSD_WP_GRP_SIZE

#define MMC_CSD_WP_GRP_SIZE 23

◆ MMC_CSD_WP_GRP_ENABLE

#define MMC_CSD_WP_GRP_ENABLE 24

◆ MMC_CSD_DEFAULT_ECC

#define MMC_CSD_DEFAULT_ECC 25

MMC/eMMC Only.

◆ MMC_CSD_R2W_FACTOR

#define MMC_CSD_R2W_FACTOR 26

◆ MMC_CSD_WRITE_BL_LEN

#define MMC_CSD_WRITE_BL_LEN 27

◆ MMC_CSD_WRITE_BL_PARTIAL

#define MMC_CSD_WRITE_BL_PARTIAL 28

◆ MMC_CSD_CONTENT_PROT_APP

#define MMC_CSD_CONTENT_PROT_APP 29

MMC/eMMC Only.

◆ MMC_CSD_FILE_FORMAT_GRP

#define MMC_CSD_FILE_FORMAT_GRP 30

◆ MMC_CSD_COPY

#define MMC_CSD_COPY 31

◆ MMC_CSD_PERM_WRITE_PROTECT

#define MMC_CSD_PERM_WRITE_PROTECT 32

◆ MMC_CSD_TMP_WRITE_PROTECT

#define MMC_CSD_TMP_WRITE_PROTECT 33

◆ MMC_CSD_FILE_FORMAT

#define MMC_CSD_FILE_FORMAT 34

◆ MMC_CSD_ECC

#define MMC_CSD_ECC 35

MMC/eMMC Only.

◆ MMC_CSD_CRC

#define MMC_CSD_CRC 36

◆ MMC_CSD_STRUCT_VER_1_0

#define MMC_CSD_STRUCT_VER_1_0 0

Valid for system specification 1.0 - 1.2.

MMC CSD Structure values

◆ MMC_CSD_STRUCT_VER_1_1

#define MMC_CSD_STRUCT_VER_1_1 1

Valid for system specification 1.4 - 2.2.

◆ MMC_CSD_STRUCT_VER_1_2

#define MMC_CSD_STRUCT_VER_1_2 2

Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1.

◆ MMC_CSD_STRUCT_EXT_CSD

#define MMC_CSD_STRUCT_EXT_CSD 3

Version is coded in CSD_STRUCTURE in EXT_CSD.

◆ MMC_CSD_SPEC_VER_0

#define MMC_CSD_SPEC_VER_0 0

Implements system specification 1.0 - 1.2.

MMC CSD Spec Version values

◆ MMC_CSD_SPEC_VER_1

#define MMC_CSD_SPEC_VER_1 1

Implements system specification 1.4.

◆ MMC_CSD_SPEC_VER_2

#define MMC_CSD_SPEC_VER_2 2

Implements system specification 2.0 - 2.2.

◆ MMC_CSD_SPEC_VER_3

#define MMC_CSD_SPEC_VER_3 3

Implements system specification 3.1 - 3.2 - 3.31.

◆ MMC_CSD_SPEC_VER_4

#define MMC_CSD_SPEC_VER_4 4

Implements system specification 4.0 - 4.1.

◆ MMC_CCC_BASIC

#define MMC_CCC_BASIC (1 << 0)

(Class 0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15) (and for SPI, CMD58,59)

MMC CSD Card Command Class (CCC) values

◆ MMC_CCC_STREAM_READ

#define MMC_CCC_STREAM_READ (1 << 1)

(Class 1) Stream read commands (CMD11)

◆ MMC_CCC_BLOCK_READ

#define MMC_CCC_BLOCK_READ (1 << 2)

(Class 2) Block read commands (CMD16,17,18)

◆ MMC_CCC_STREAM_WRITE

#define MMC_CCC_STREAM_WRITE (1 << 3)

(Class 3) Stream write commands (CMD20)

◆ MMC_CCC_BLOCK_WRITE

#define MMC_CCC_BLOCK_WRITE (1 << 4)

(Class 4) Block write commands (CMD16,24,25,26,27)

◆ MMC_CCC_ERASE

#define MMC_CCC_ERASE (1 << 5)

(Class 5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39)

◆ MMC_CCC_WRITE_PROT

#define MMC_CCC_WRITE_PROT (1 << 6)

(Class 6) Ability to write protect blocks (CMD28,29,30)

◆ MMC_CCC_LOCK_CARD

#define MMC_CCC_LOCK_CARD (1 << 7)

(Class 7) Ability to lock down card (CMD16,CMD42)

◆ MMC_CCC_APP_SPEC

#define MMC_CCC_APP_SPEC (1 << 8)

(Class 8) Application specific (CMD55,56,57,ACMD*)

◆ MMC_CCC_IO_MODE

#define MMC_CCC_IO_MODE (1 << 9)

(Class 9) I/O mode (CMD5,39,40,52,53)

◆ MMC_CCC_SWITCH

#define MMC_CCC_SWITCH (1 << 10)

(Class 10) High speed switch (CMD6,34,35,36,37,50)

◆ MMC_CCC_EXTENSION

#define MMC_CCC_EXTENSION (1 << 11)

(Class 11) Extension (CMD?)

◆ SECURE_ERASE

#define SECURE_ERASE 0x80000000

◆ MMC_VDD_165_195

#define MMC_VDD_165_195 0x00000080

VDD voltage 1.65 - 1.95.

MMC Voltage Values

◆ MMC_VDD_20_21

#define MMC_VDD_20_21 0x00000100

VDD voltage 2.0 ~ 2.1.

◆ MMC_VDD_21_22

#define MMC_VDD_21_22 0x00000200

VDD voltage 2.1 ~ 2.2.

◆ MMC_VDD_22_23

#define MMC_VDD_22_23 0x00000400

VDD voltage 2.2 ~ 2.3.

◆ MMC_VDD_23_24

#define MMC_VDD_23_24 0x00000800

VDD voltage 2.3 ~ 2.4.

◆ MMC_VDD_24_25

#define MMC_VDD_24_25 0x00001000

VDD voltage 2.4 ~ 2.5.

◆ MMC_VDD_25_26

#define MMC_VDD_25_26 0x00002000

VDD voltage 2.5 ~ 2.6.

◆ MMC_VDD_26_27

#define MMC_VDD_26_27 0x00004000

VDD voltage 2.6 ~ 2.7.

◆ MMC_VDD_27_28

#define MMC_VDD_27_28 0x00008000

VDD voltage 2.7 ~ 2.8.

◆ MMC_VDD_28_29

#define MMC_VDD_28_29 0x00010000

VDD voltage 2.8 ~ 2.9.

◆ MMC_VDD_29_30

#define MMC_VDD_29_30 0x00020000

VDD voltage 2.9 ~ 3.0.

◆ MMC_VDD_30_31

#define MMC_VDD_30_31 0x00040000

VDD voltage 3.0 ~ 3.1.

◆ MMC_VDD_31_32

#define MMC_VDD_31_32 0x00080000

VDD voltage 3.1 ~ 3.2.

◆ MMC_VDD_32_33

#define MMC_VDD_32_33 0x00100000

VDD voltage 3.2 ~ 3.3.

◆ MMC_VDD_33_34

#define MMC_VDD_33_34 0x00200000

VDD voltage 3.3 ~ 3.4.

◆ MMC_VDD_34_35

#define MMC_VDD_34_35 0x00400000

VDD voltage 3.4 ~ 3.5.

◆ MMC_VDD_35_36

#define MMC_VDD_35_36 0x00800000

VDD voltage 3.5 ~ 3.6.

◆ MMC_SWITCH_MODE_CMD_SET

#define MMC_SWITCH_MODE_CMD_SET 0x00

Change the command set.

MMC Switch Mode Values

◆ MMC_SWITCH_MODE_SET_BITS

#define MMC_SWITCH_MODE_SET_BITS 0x01

Set bits in EXT_CSD byte addressed by index which are 1 in value field.

◆ MMC_SWITCH_MODE_CLEAR_BITS

#define MMC_SWITCH_MODE_CLEAR_BITS 0x02

Clear bits in EXT_CSD byte addressed by index, which are 1 in value field.

◆ MMC_SWITCH_MODE_WRITE_BYTE

#define MMC_SWITCH_MODE_WRITE_BYTE 0x03

Set target byte to value.

◆ EXT_CSD_CMDQ_MODE_EN

◆ EXT_CSD_HPI_FEATURES

#define EXT_CSD_HPI_FEATURES 503

RO.

◆ EXT_CSD_PARTITION_ATTRIBUTE_ENH_4

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_4 0x10

MMC EXT_CSD field definitions

◆ EXT_CSD_PARTITION_ATTRIBUTE_ENH_3

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_3 0x08

◆ EXT_CSD_PARTITION_ATTRIBUTE_ENH_2

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_2 0x04

◆ EXT_CSD_PARTITION_ATTRIBUTE_ENH_1

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_1 0x02

◆ EXT_CSD_PARTITION_ATTRIBUTE_ENH_USR

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_USR 0x01

◆ EXT_CSD_PARTITION_EXT_ATTRIBUTE_EN

#define EXT_CSD_PARTITION_EXT_ATTRIBUTE_EN 0x04

◆ EXT_CSD_PARTITION_ENH_ATTRIBUTE_EN

#define EXT_CSD_PARTITION_ENH_ATTRIBUTE_EN 0x02

◆ EXT_CSD_PARTITION_PARTITIONING_EN

#define EXT_CSD_PARTITION_PARTITIONING_EN 0x01

◆ EXT_CSD_WR_REL_PARAM_EN

#define EXT_CSD_WR_REL_PARAM_EN (1 << 2)

◆ EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR

#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1 << 4)

◆ EXT_CSD_BOOT_WP_B_PWR_WP_DIS

#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS 0x40

◆ EXT_CSD_BOOT_WP_B_PERM_WP_DIS

#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS 0x10

◆ EXT_CSD_BOOT_WP_B_PERM_WP_EN

#define EXT_CSD_BOOT_WP_B_PERM_WP_EN 0x04

◆ EXT_CSD_BOOT_WP_B_PWR_WP_EN

#define EXT_CSD_BOOT_WP_B_PWR_WP_EN 0x01

◆ EXT_CSD_PART_CONFIG_ACC_MASK

#define EXT_CSD_PART_CONFIG_ACC_MASK 0x07

◆ EXT_CSD_PART_CONFIG_ACC_BOOT0

#define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01

◆ EXT_CSD_PART_CONFIG_ACC_RPMB

#define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03

◆ EXT_CSD_PART_CONFIG_ACC_GP0

#define EXT_CSD_PART_CONFIG_ACC_GP0 0x04

◆ EXT_CSD_PART_SETTING_COMPLETED

#define EXT_CSD_PART_SETTING_COMPLETED 0x01

◆ EXT_CSD_PART_SUPPORT_PART_EN

#define EXT_CSD_PART_SUPPORT_PART_EN 0x01

◆ EXT_CSD_CMD_SET_NORMAL

#define EXT_CSD_CMD_SET_NORMAL (1 << 0)

◆ EXT_CSD_CMD_SET_SECURE

#define EXT_CSD_CMD_SET_SECURE (1 << 1)

◆ EXT_CSD_CMD_SET_CPSECURE

#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)

◆ EXT_CSD_CARD_TYPE_HS_26

#define EXT_CSD_CARD_TYPE_HS_26 (1 << 0)

Card can run at 26MHz.

◆ EXT_CSD_CARD_TYPE_HS_52

#define EXT_CSD_CARD_TYPE_HS_52 (1 << 1)

Card can run at 52MHz.

◆ EXT_CSD_CARD_TYPE_HS

#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | EXT_CSD_CARD_TYPE_HS_52)

◆ EXT_CSD_CARD_TYPE_DDR_1_8V

#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)

Card can run at 52MHz / DDR mode @1.8V or 3V I/O.

◆ EXT_CSD_CARD_TYPE_DDR_1_2V

#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)

Card can run at 52MHz / DDR mode @1.2V I/O.

◆ EXT_CSD_CARD_TYPE_DDR_52

#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V)

◆ EXT_CSD_CARD_TYPE_HS200_1_8V

#define EXT_CSD_CARD_TYPE_HS200_1_8V (1 << 4)

Card can run at 200MHz.

◆ EXT_CSD_CARD_TYPE_HS200_1_2V

#define EXT_CSD_CARD_TYPE_HS200_1_2V (1 << 5)

Card can run at 200MHz / SDR mode @1.2V I/O.

◆ EXT_CSD_CARD_TYPE_HS200

#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | EXT_CSD_CARD_TYPE_HS200_1_2V)

◆ EXT_CSD_CARD_TYPE_HS400_1_8V

#define EXT_CSD_CARD_TYPE_HS400_1_8V (1 << 6)

Card can run at 200MHz DDR, 1.8V.

◆ EXT_CSD_CARD_TYPE_HS400_1_2V

#define EXT_CSD_CARD_TYPE_HS400_1_2V (1 << 7)

Card can run at 200MHz DDR, 1.2V.

◆ EXT_CSD_CARD_TYPE_HS400

#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | EXT_CSD_CARD_TYPE_HS400_1_2V)

◆ EXT_CSD_CARD_TYPE_HS400ES

#define EXT_CSD_CARD_TYPE_HS400ES (1 << 8)

Card can run at HS400ES.

◆ EXT_CSD_BUS_WIDTH_1

#define EXT_CSD_BUS_WIDTH_1 0

Card is in 1 bit mode.

◆ EXT_CSD_BUS_WIDTH_4

#define EXT_CSD_BUS_WIDTH_4 1

Card is in 4 bit mode.

◆ EXT_CSD_BUS_WIDTH_8

#define EXT_CSD_BUS_WIDTH_8 2

Card is in 8 bit mode.

◆ EXT_CSD_DDR_BUS_WIDTH_4

#define EXT_CSD_DDR_BUS_WIDTH_4 5

Card is in 4 bit DDR mode.

◆ EXT_CSD_DDR_BUS_WIDTH_8

#define EXT_CSD_DDR_BUS_WIDTH_8 6

Card is in 8 bit DDR mode.

◆ EXT_CSD_BUS_WIDTH_STROBE

#define EXT_CSD_BUS_WIDTH_STROBE 1 << 7

Enhanced strobe mode.

◆ EXT_CSD_TIMING_BC

#define EXT_CSD_TIMING_BC 0

Backwards compatility.

◆ EXT_CSD_TIMING_HS

#define EXT_CSD_TIMING_HS 1

High speed.

◆ EXT_CSD_TIMING_HS200

#define EXT_CSD_TIMING_HS200 2

HS200.

◆ EXT_CSD_TIMING_HS400

#define EXT_CSD_TIMING_HS400 3

HS400.

◆ EXT_CSD_DRV_STR_SHIFT

#define EXT_CSD_DRV_STR_SHIFT 4

Driver Strength shift.

◆ EXT_CSD_SEC_ER_EN

#define EXT_CSD_SEC_ER_EN 1 << 0

◆ EXT_CSD_SEC_BD_BLK_EN

#define EXT_CSD_SEC_BD_BLK_EN 1 << 2

◆ EXT_CSD_SEC_GB_CL_EN

#define EXT_CSD_SEC_GB_CL_EN 1 << 4

◆ EXT_CSD_SEC_SANITIZE

#define EXT_CSD_SEC_SANITIZE 1 << 6

v4.5 only

◆ EXT_CSD_RST_N_EN_MASK

#define EXT_CSD_RST_N_EN_MASK 0x03

◆ EXT_CSD_RST_N_ENABLED

#define EXT_CSD_RST_N_ENABLED 1

RST_n is enabled on card.

◆ EXT_CSD_NO_POWER_NOTIFICATION

#define EXT_CSD_NO_POWER_NOTIFICATION 0

◆ EXT_CSD_POWER_ON

#define EXT_CSD_POWER_ON 1

◆ EXT_CSD_POWER_OFF_SHORT

#define EXT_CSD_POWER_OFF_SHORT 2

◆ EXT_CSD_POWER_OFF_LONG

#define EXT_CSD_POWER_OFF_LONG 3

◆ EXT_CSD_PWR_CL_8BIT_MASK

#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0

8 bit PWR CLS

◆ EXT_CSD_PWR_CL_4BIT_MASK

#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F

8 bit PWR CLS

◆ EXT_CSD_PWR_CL_8BIT_SHIFT

#define EXT_CSD_PWR_CL_8BIT_SHIFT 4

◆ EXT_CSD_PWR_CL_4BIT_SHIFT

#define EXT_CSD_PWR_CL_4BIT_SHIFT 0

◆ EXT_CSD_PACKED_EVENT_EN

#define EXT_CSD_PACKED_EVENT_EN 1 << 3

◆ EXT_CSD_URGENT_BKOPS

#define EXT_CSD_URGENT_BKOPS 1 << 0

EXCEPTION_EVENT_STATUS field

◆ EXT_CSD_DYNCAP_NEEDED

#define EXT_CSD_DYNCAP_NEEDED 1 << 1

◆ EXT_CSD_SYSPOOL_EXHAUSTED

#define EXT_CSD_SYSPOOL_EXHAUSTED 1 << 2

◆ EXT_CSD_PACKED_FAILURE

#define EXT_CSD_PACKED_FAILURE 1 << 3

◆ EXT_CSD_PACKED_GENERIC_ERROR

#define EXT_CSD_PACKED_GENERIC_ERROR 1 << 0

◆ EXT_CSD_PACKED_INDEXED_ERROR

#define EXT_CSD_PACKED_INDEXED_ERROR 1 << 1

◆ EXT_CSD_BKOPS_LEVEL_2

#define EXT_CSD_BKOPS_LEVEL_2 0x02

BKOPS status level

◆ EXT_CSD_MANUAL_BKOPS_MASK

#define EXT_CSD_MANUAL_BKOPS_MASK 0x01

BKOPS modes

◆ EXT_CSD_AUTO_BKOPS_MASK

#define EXT_CSD_AUTO_BKOPS_MASK 0x02

◆ EXT_CSD_CMDQ_MODE_ENABLED

#define EXT_CSD_CMDQ_MODE_ENABLED 1 << 0

Command Queue

◆ EXT_CSD_CMDQ_DEPTH_MASK

#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F

◆ EXT_CSD_CMDQ_SUPPORTED

#define EXT_CSD_CMDQ_SUPPORTED 1 << 0

◆ MMC_HIGH_26_MAX_DTR

#define MMC_HIGH_26_MAX_DTR 26000000

High Speed Max

◆ MMC_HIGH_52_MAX_DTR

#define MMC_HIGH_52_MAX_DTR 52000000

◆ MMC_HIGH_DDR_MAX_DTR

#define MMC_HIGH_DDR_MAX_DTR 52000000

◆ MMC_HS200_MAX_DTR

#define MMC_HS200_MAX_DTR 200000000

◆ MMC_MIN_PART_SWITCH_TIME

#define MMC_MIN_PART_SWITCH_TIME 300

Milliseconds.

Minimum partition switch timeout

◆ MMCPART_NOAVAILABLE

#define MMCPART_NOAVAILABLE (0xff)

MMC ?????

◆ PART_ACCESS_MASK

#define PART_ACCESS_MASK (0x07)

◆ PART_SUPPORT

#define PART_SUPPORT (0x01)

◆ ENHNCD_SUPPORT

#define ENHNCD_SUPPORT (0x02)

◆ PART_ENH_ATTRIB

#define PART_ENH_ATTRIB (0x1f)

◆ MMC_MAX_BLOCK_LEN

#define MMC_MAX_BLOCK_LEN 512

Maximum block size for MMC

◆ MMC_MAX_BLOCK_COUNT

#define MMC_MAX_BLOCK_COUNT 65535

Maximum block count for MMC

◆ MMC_NUM_BOOT_PARTITION

#define MMC_NUM_BOOT_PARTITION 2

The number of MMC physical partitions. These consist of: boot partitions (2), general purpose partitions (4) and RPMB partition (1) in MMC v4.4

◆ MMC_NUM_GP_PARTITION

#define MMC_NUM_GP_PARTITION 4

◆ MMC_NUM_PHY_PARTITION

#define MMC_NUM_PHY_PARTITION 7

◆ MMC_DEFAULT_CMD6_TIMEOUT_MS

#define MMC_DEFAULT_CMD6_TIMEOUT_MS 500

Timeouts

◆ MMC_MIN_CACHE_EN_TIMEOUT_MS

#define MMC_MIN_CACHE_EN_TIMEOUT_MS 1600

◆ MMC_FIRMWARE_VERSION_LEN

#define MMC_FIRMWARE_VERSION_LEN 8

Sizes

◆ MMC_DISCARD_FEATURE

#define MMC_DISCARD_FEATURE 0x01

Version specific features

◆ MMC_BUSY_CMD6

#define MMC_BUSY_CMD6 0

Busy Poll Commands

◆ MMC_BUSY_ERASE

#define MMC_BUSY_ERASE 1

◆ MMC_BUSY_HPI

#define MMC_BUSY_HPI 2

◆ MMC_ERASE_ARG

#define MMC_ERASE_ARG 0x00000000

Erase/Trim/Discard Arguments

◆ MMC_SECURE_ERASE_ARG

#define MMC_SECURE_ERASE_ARG 0x80000000

◆ MMC_TRIM_ARG

#define MMC_TRIM_ARG 0x00000001

◆ MMC_DISCARD_ARG

#define MMC_DISCARD_ARG 0x00000003

◆ MMC_SECURE_TRIM1_ARG

#define MMC_SECURE_TRIM1_ARG 0x80000001

◆ MMC_SECURE_TRIM2_ARG

#define MMC_SECURE_TRIM2_ARG 0x80008000

◆ MMC_SECURE_ARGS

#define MMC_SECURE_ARGS 0x80000000

◆ MMC_TRIM_ARGS

#define MMC_TRIM_ARGS 0x00008001

◆ SD_DEFAULT_BLOCKSIZE

#define SD_DEFAULT_BLOCKSIZE 512

SD specific constants

◆ SD_DEFAULT_BLOCKSHIFT

#define SD_DEFAULT_BLOCKSHIFT 9

◆ SD_BUS_WIDTH_1

#define SD_BUS_WIDTH_1 0

SD Bus Widths

◆ SD_BUS_WIDTH_4

#define SD_BUS_WIDTH_4 2

◆ SD_BUS_SPEED_DEFAULT

#define SD_BUS_SPEED_DEFAULT 25000000

SD Bus Speeds (Hz)

◆ SD_BUS_SPEED_HS

#define SD_BUS_SPEED_HS 50000000

◆ SD_BUS_SPEED_UHS_SDR12

#define SD_BUS_SPEED_UHS_SDR12 25000000

◆ SD_BUS_SPEED_UHS_SDR25

#define SD_BUS_SPEED_UHS_SDR25 50000000

◆ SD_BUS_SPEED_UHS_DDR50

#define SD_BUS_SPEED_UHS_DDR50 50000000

◆ SD_BUS_SPEED_UHS_SDR50

#define SD_BUS_SPEED_UHS_SDR50 100000000

◆ SD_BUS_SPEED_UHS_SDR104

#define SD_BUS_SPEED_UHS_SDR104 208000000

◆ SD_CMD_SEND_RELATIVE_ADDR

#define SD_CMD_SEND_RELATIVE_ADDR 3

SD Commands (From: /include/linux/mmc/sd.h) Class 0

◆ SD_CMD_SEND_IF_COND

#define SD_CMD_SEND_IF_COND 8

◆ SD_CMD_SWITCH_VOLTAGE

#define SD_CMD_SWITCH_VOLTAGE 11

◆ SD_CMD_SWITCH

#define SD_CMD_SWITCH 6

See: 4.3.10 Switch Function Command.

Class 10

◆ SD_CMD_ERASE_WR_BLK_START

#define SD_CMD_ERASE_WR_BLK_START 32

Class 5

◆ SD_CMD_ERASE_WR_BLK_END

#define SD_CMD_ERASE_WR_BLK_END 33

◆ SD_CMD_APP_SET_BUS_WIDTH

#define SD_CMD_APP_SET_BUS_WIDTH 6

Application commands

◆ SD_CMD_APP_SD_STATUS

#define SD_CMD_APP_SD_STATUS 13

◆ SD_CMD_APP_SEND_NUM_WR_BLKS

#define SD_CMD_APP_SEND_NUM_WR_BLKS 22

◆ SD_CMD_APP_SEND_OP_COND

#define SD_CMD_APP_SEND_OP_COND 41

◆ SD_CMD_APP_SEND_SCR

#define SD_CMD_APP_SEND_SCR 51

◆ SD_SWITCH_MODE_CHECK

#define SD_SWITCH_MODE_CHECK 0

SD_CMD_SWITCH argument format: [31] Check (0) or switch (1) [30:24] Reserved (0) [23:20] Function group 6 [19:16] Function group 5 [15:12] Function group 4 [11:8] Function group 3 [7:4] Function group 2 [3:0] Function group 1 SD Switch Mode Values

◆ SD_SWITCH_MODE_SWITCH

#define SD_SWITCH_MODE_SWITCH 1

◆ SD_SWITCH_FUNCTION_GROUP_ACCESS

#define SD_SWITCH_FUNCTION_GROUP_ACCESS 0

Access Mode.

SD Switch Function Groups

◆ SD_SWITCH_FUNCTION_GROUP_COMMAND

#define SD_SWITCH_FUNCTION_GROUP_COMMAND 1

Command System.

◆ SD_SWITCH_FUNCTION_GROUP_DRIVER

#define SD_SWITCH_FUNCTION_GROUP_DRIVER 2

Driver Strength.

◆ SD_SWITCH_FUNCTION_GROUP_POWER

#define SD_SWITCH_FUNCTION_GROUP_POWER 3

Power Limit.

◆ SD_SWITCH_ACCESS_MODE_DEF

#define SD_SWITCH_ACCESS_MODE_DEF 0

Default SDR12.

SD Switch Access Modes

◆ SD_SWITCH_ACCESS_MODE_HS

#define SD_SWITCH_ACCESS_MODE_HS 1

High Speed SDR25.

◆ SD_SWITCH_ACCESS_MODE_SDR50

#define SD_SWITCH_ACCESS_MODE_SDR50 2

SDR50 (1.8V only).

◆ SD_SWITCH_ACCESS_MODE_SDR104

#define SD_SWITCH_ACCESS_MODE_SDR104 3

SDR104 (1.8V only).

◆ SD_SWITCH_ACCESS_MODE_DDR50

#define SD_SWITCH_ACCESS_MODE_DDR50 4

DDR50 (1.8V only).

◆ SD_SWITCH_COMMAND_SYSTEM_DEF

#define SD_SWITCH_COMMAND_SYSTEM_DEF 0

Default.

SD Switch Command System

◆ SD_SWITCH_COMMAND_SYSTEM_EC

#define SD_SWITCH_COMMAND_SYSTEM_EC 1

For eC.

◆ SD_SWITCH_COMMAND_SYSTEM_OTP

#define SD_SWITCH_COMMAND_SYSTEM_OTP 3

OTP.

◆ SD_SWITCH_COMMAND_SYSTEM_ASSD

#define SD_SWITCH_COMMAND_SYSTEM_ASSD 4

ASSD.

◆ SD_SWITCH_DRIVER_STRENGTH_DEF

#define SD_SWITCH_DRIVER_STRENGTH_DEF 0

Default Type B.

SD Switch Driver Strength

◆ SD_SWITCH_DRIVER_STRENGTH_TYPE_A

#define SD_SWITCH_DRIVER_STRENGTH_TYPE_A 1

Type A.

◆ SD_SWITCH_DRIVER_STRENGTH_TYPE_C

#define SD_SWITCH_DRIVER_STRENGTH_TYPE_C 2

Type C.

◆ SD_SWITCH_DRIVER_STRENGTH_TYPE_D

#define SD_SWITCH_DRIVER_STRENGTH_TYPE_D 3

Type D.

◆ SD_SWITCH_POWER_LIMIT_DEF

#define SD_SWITCH_POWER_LIMIT_DEF 0

Default 0.72W.

SD Switch Power Limit

◆ SD_SWITCH_POWER_LIMIT_144

#define SD_SWITCH_POWER_LIMIT_144 1

1.44W

◆ SD_SWITCH_POWER_LIMIT_216

#define SD_SWITCH_POWER_LIMIT_216 2

2.16W (Embedded only)

◆ SD_SWITCH_POWER_LIMIT_288

#define SD_SWITCH_POWER_LIMIT_288 3

2.88W (Embedded only)

◆ SD_SWITCH_POWER_LIMIT_180

#define SD_SWITCH_POWER_LIMIT_180 4

1.80W

◆ SD_SEND_IF_COND_CHECK_PATTERN

#define SD_SEND_IF_COND_CHECK_PATTERN 0xAA

SD_CMD_SEND_IF_COND argument format: [31:12] Reserved (0) [11:8] Host Voltage Supply Flags [7:0] Check Pattern (0xAA) SD Send Interface Condition Values

◆ SD_SEND_IF_COND_VOLTAGE_MASK

#define SD_SEND_IF_COND_VOLTAGE_MASK 0x00FF8000

MMC_VDD_27_28, MMC_VDD_28_29, MMC_VDD_29_30, MMC_VDD_30_31, MMC_VDD_31_32, MMC_VDD_32_33, MMC_VDD_33_34, MMC_VDD_34_35, MMC_VDD_35_36.

◆ SD_SEND_OP_COND_VOLTAGE_MASK

#define SD_SEND_OP_COND_VOLTAGE_MASK 0x00FF8000

MMC_VDD_27_28, MMC_VDD_28_29, MMC_VDD_29_30, MMC_VDD_30_31, MMC_VDD_31_32, MMC_VDD_32_33, MMC_VDD_33_34, MMC_VDD_34_35, MMC_VDD_35_36.

SD Send Operation Condition Values

◆ SD_OCR_CCS

#define SD_OCR_CCS 0x40000000

Card Capacity Status - 0 = SDSC / 1 = SDHC or SDXC.

SD Operation Condition Register values

◆ SD_OCR_UHS_II

#define SD_OCR_UHS_II 0x20000000

UHS-II Card Status - 0 = Non UHS-II Card / 1 = UHS-II Card.

◆ SD_OCR_XPC

#define SD_OCR_XPC 0x10000000

SDXC Power Control.

◆ SD_OCR_S18A

#define SD_OCR_S18A 0x01000000

1.8V Switching Accepted

◆ SD_CSD_STRUCT_VER_1_0

#define SD_CSD_STRUCT_VER_1_0 0

Standard Capacity.

SD CSD Structure values

◆ SD_CSD_STRUCT_VER_2_0

#define SD_CSD_STRUCT_VER_2_0 1

High Capacity and Extended Capacity.

◆ SD_SSR_DAT_BUS_WIDTH

#define SD_SSR_DAT_BUS_WIDTH 1

SD Status Register (SSR) values SD SSR Fields

◆ SD_SSR_SECURED_MODE

#define SD_SSR_SECURED_MODE 2

◆ SD_SSR_SD_CARD_TYPE

#define SD_SSR_SD_CARD_TYPE 3

◆ SD_SSR_SIZE_OF_PROTECTED_AREA

#define SD_SSR_SIZE_OF_PROTECTED_AREA 4

◆ SD_SSR_SPEED_CLASS

#define SD_SSR_SPEED_CLASS 5

◆ SD_SSR_PERFORMANCE_MOVE

#define SD_SSR_PERFORMANCE_MOVE 6

◆ SD_SSR_AU_SIZE

#define SD_SSR_AU_SIZE 7

◆ SD_SSR_ERASE_SIZE

#define SD_SSR_ERASE_SIZE 8

◆ SD_SSR_ERASE_TIMEOUT

#define SD_SSR_ERASE_TIMEOUT 9

◆ SD_SSR_ERASE_OFFSET

#define SD_SSR_ERASE_OFFSET 10

◆ SD_SSR_UHS_SPEED_GRADE

#define SD_SSR_UHS_SPEED_GRADE 11

◆ SD_SSR_UHS_AU_SIZE

#define SD_SSR_UHS_AU_SIZE 12

◆ SD_SSR_BUS_WIDTH_1

#define SD_SSR_BUS_WIDTH_1 0

1 (default)

SD SSR Bus Width values

◆ SD_SSR_BUS_WIDTH_4

#define SD_SSR_BUS_WIDTH_4 2

4 bit width

◆ SD_SSR_CARD_TYPE_RW

#define SD_SSR_CARD_TYPE_RW 0x0000

Regular SD RD/WR Card.

SD SSR Card Type values

◆ SD_SSR_CARD_TYPE_ROM

#define SD_SSR_CARD_TYPE_ROM 0x0001

SD ROM Card.

◆ SD_SSR_CARD_TYPE_OTP

#define SD_SSR_CARD_TYPE_OTP 0x0002

OTP.

◆ SD_SSR_SPEED_CLASS_0

#define SD_SSR_SPEED_CLASS_0 0x00

Class 0.

SD SSR Speed Class values

◆ SD_SSR_SPEED_CLASS_2

#define SD_SSR_SPEED_CLASS_2 0x01

Class 2.

◆ SD_SSR_SPEED_CLASS_4

#define SD_SSR_SPEED_CLASS_4 0x02

Class 4.

◆ SD_SSR_SPEED_CLASS_6

#define SD_SSR_SPEED_CLASS_6 0x03

Class 6.

◆ SD_SSR_SPEED_CLASS_10

#define SD_SSR_SPEED_CLASS_10 0x04

Class 10.

◆ SD_SSR_UHS_SPEED_GRADE_0

#define SD_SSR_UHS_SPEED_GRADE_0 0

Less than 10MB/sec.

SD SSR UHS Speed Grade values

◆ SD_SSR_UHS_SPEED_GRADE_1

#define SD_SSR_UHS_SPEED_GRADE_1 1

10MB/sec and above

◆ SD_SWITCH_MAXIMUM_CURRENT

#define SD_SWITCH_MAXIMUM_CURRENT 1

SD Switch Status values SD Switch Fields

◆ SD_SWITCH_GROUP6_SUPPORT

#define SD_SWITCH_GROUP6_SUPPORT 2

◆ SD_SWITCH_GROUP5_SUPPORT

#define SD_SWITCH_GROUP5_SUPPORT 3

◆ SD_SWITCH_GROUP4_SUPPORT

#define SD_SWITCH_GROUP4_SUPPORT 4

◆ SD_SWITCH_GROUP3_SUPPORT

#define SD_SWITCH_GROUP3_SUPPORT 5

◆ SD_SWITCH_GROUP2_SUPPORT

#define SD_SWITCH_GROUP2_SUPPORT 6

◆ SD_SWITCH_GROUP1_SUPPORT

#define SD_SWITCH_GROUP1_SUPPORT 7

◆ SD_SWITCH_GROUP6_SELECTION

#define SD_SWITCH_GROUP6_SELECTION 8

◆ SD_SWITCH_GROUP5_SELECTION

#define SD_SWITCH_GROUP5_SELECTION 9

◆ SD_SWITCH_GROUP4_SELECTION

#define SD_SWITCH_GROUP4_SELECTION 10

◆ SD_SWITCH_GROUP3_SELECTION

#define SD_SWITCH_GROUP3_SELECTION 11

◆ SD_SWITCH_GROUP2_SELECTION

#define SD_SWITCH_GROUP2_SELECTION 12

◆ SD_SWITCH_GROUP1_SELECTION

#define SD_SWITCH_GROUP1_SELECTION 13

◆ SD_SWITCH_STRUCT_VERSION

#define SD_SWITCH_STRUCT_VERSION 14

◆ SD_SWITCH_GROUP6_BUSY_STATUS

#define SD_SWITCH_GROUP6_BUSY_STATUS 15

◆ SD_SWITCH_GROUP5_BUSY_STATUS

#define SD_SWITCH_GROUP5_BUSY_STATUS 16

◆ SD_SWITCH_GROUP4_BUSY_STATUS

#define SD_SWITCH_GROUP4_BUSY_STATUS 17

◆ SD_SWITCH_GROUP3_BUSY_STATUS

#define SD_SWITCH_GROUP3_BUSY_STATUS 18

◆ SD_SWITCH_GROUP2_BUSY_STATUS

#define SD_SWITCH_GROUP2_BUSY_STATUS 19

◆ SD_SWITCH_GROUP1_BUSY_STATUS

#define SD_SWITCH_GROUP1_BUSY_STATUS 20

◆ SD_SWITCH_GROUP1_SDR12

#define SD_SWITCH_GROUP1_SDR12 (1 << 0)

SD Switch Access Mode (Bus Speed) Support (Group 1)

◆ SD_SWITCH_GROUP1_HS

#define SD_SWITCH_GROUP1_HS (1 << 1)

◆ SD_SWITCH_GROUP1_SDR25

#define SD_SWITCH_GROUP1_SDR25 (1 << 1)

◆ SD_SWITCH_GROUP1_SDR50

#define SD_SWITCH_GROUP1_SDR50 (1 << 2)

◆ SD_SWITCH_GROUP1_SDR104

#define SD_SWITCH_GROUP1_SDR104 (1 << 3)

◆ SD_SWITCH_GROUP1_DDR50

#define SD_SWITCH_GROUP1_DDR50 (1 << 4)

◆ SD_SWITCH_GROUP3_TYPE_B

#define SD_SWITCH_GROUP3_TYPE_B (1 << 0)

SD Switch Driver Strength Support (Group 3)

◆ SD_SWITCH_GROUP3_TYPE_A

#define SD_SWITCH_GROUP3_TYPE_A (1 << 1)

◆ SD_SWITCH_GROUP3_TYPE_C

#define SD_SWITCH_GROUP3_TYPE_C (1 << 2)

◆ SD_SWITCH_GROUP3_TYPE_D

#define SD_SWITCH_GROUP3_TYPE_D (1 << 3)

◆ SD_SWITCH_STRUCT_VER_0

#define SD_SWITCH_STRUCT_VER_0 0

Bits 511:376 are defined (SD_SWITCH_MAXIMUM_CURRENT to SD_SWITCH_GROUP1_SELECTION).

SD Switch Structure Versions

◆ SD_SWITCH_STRUCT_VER_1

#define SD_SWITCH_STRUCT_VER_1 1

Bits 511:272 are defined (SD_SWITCH_MAXIMUM_CURRENT to SD_SWITCH_GROUP1_BUSY_STATUS.

◆ SD_SCR_STRUCTURE

#define SD_SCR_STRUCTURE 1

SD Configuration Register (SCR) values SD SCR Fields

◆ SD_SCR_SD_SPEC

#define SD_SCR_SD_SPEC 2

◆ SD_SCR_DATA_STAT_AFTER_ERASE

#define SD_SCR_DATA_STAT_AFTER_ERASE 3

◆ SD_SCR_SD_SECURITY

#define SD_SCR_SD_SECURITY 4

◆ SD_SCR_SD_BUS_WIDTHS

#define SD_SCR_SD_BUS_WIDTHS 5

◆ SD_SCR_SD_SPEC3

#define SD_SCR_SD_SPEC3 6

◆ SD_SCR_EX_SECURITY

#define SD_SCR_EX_SECURITY 7

◆ SD_SCR_SD_SPEC4

#define SD_SCR_SD_SPEC4 8

◆ SD_SCR_CMD_SUPPORT

#define SD_SCR_CMD_SUPPORT 9

◆ SD_SCR_STRUCT_VER_1_0

#define SD_SCR_STRUCT_VER_1_0 0

Valid for system specification 1.01 - 4.0.

SD SCR Structure values

◆ SD_SCR_SPEC_VER_0

#define SD_SCR_SPEC_VER_0 0

Implements system specification 1.0 - 1.01.

SD SCR Spec Version values

◆ SD_SCR_SPEC_VER_1

#define SD_SCR_SPEC_VER_1 1

Implements system specification 1.10.

◆ SD_SCR_SPEC_VER_2

#define SD_SCR_SPEC_VER_2 2

Implements system specification 2.00-4.0X.

◆ SD_SCR_SECURITY_VER_0

#define SD_SCR_SECURITY_VER_0 0

No Security.

SD SCR Security values

◆ SD_SCR_SECURITY_VER_2

#define SD_SCR_SECURITY_VER_2 2

SDSC Card (Security Version 1.01).

◆ SD_SCR_SECURITY_VER_3

#define SD_SCR_SECURITY_VER_3 3

SDHC Card (Security Version 2.00).

◆ SD_SCR_SECURITY_VER_4

#define SD_SCR_SECURITY_VER_4 4

SDXC Card (Security Version 3.xx).

◆ SD_SCR_BUS_WIDTH_1

#define SD_SCR_BUS_WIDTH_1 (1 << 0)

1 bit (DAT0)

SD SCR Bus Width values

◆ SD_SCR_BUS_WIDTH_4

#define SD_SCR_BUS_WIDTH_4 (1 << 2)

4 bit (DAT0-3)

◆ SD_SCR_EX_SECURITY_VER_0

#define SD_SCR_EX_SECURITY_VER_0 0

Extended Security is not supported.

SD SCR Extended Security values

◆ SD_SCR_CMD20_SUPPORT

#define SD_SCR_CMD20_SUPPORT (1 << 0)

Mandatory for SDXC card.

SD SCR Command Support values

◆ SD_SCR_CMD23_SUPPORT

#define SD_SCR_CMD23_SUPPORT (1 << 1)

Mandatory for UHS104 card.

◆ SD_SCR_CMD48_49_SUPPORT

#define SD_SCR_CMD48_49_SUPPORT (1 << 2)

Optional.

◆ SD_SCR_CMD58_59_SUPPORT

#define SD_SCR_CMD58_59_SUPPORT (1 << 3)

Optional (If CMD58/59 is supported, CMD48/49 shall be supported).

◆ SDIO_STATE_DETACHED

#define SDIO_STATE_DETACHED 0

SDIO specific constants SDIO Function States

◆ SDIO_STATE_DETACHING

#define SDIO_STATE_DETACHING 1

◆ SDIO_STATE_ATTACHING

#define SDIO_STATE_ATTACHING 2

◆ SDIO_STATE_ATTACHED

#define SDIO_STATE_ATTACHED 3

◆ SDIO_STATE_MAX

#define SDIO_STATE_MAX 3

◆ SDIO_STATUS_UNBOUND

#define SDIO_STATUS_UNBOUND 0

SDIO Function Status

◆ SDIO_STATUS_BOUND

#define SDIO_STATUS_BOUND 1

◆ SDIO_STATUS_MAX

#define SDIO_STATUS_MAX 1

◆ SDIO_CMD_SEND_OP_COND

#define SDIO_CMD_SEND_OP_COND 5

SDIO Commands (From: /include/linux/mmc/sdio.h)

◆ SDIO_CMD_RW_DIRECT

#define SDIO_CMD_RW_DIRECT 52

◆ SDIO_CMD_RW_EXTENDED

#define SDIO_CMD_RW_EXTENDED 53

◆ SDIO_RSP_R4_18V_PRESENT

#define SDIO_RSP_R4_18V_PRESENT (1 << 24)

SDIO_CMD_RW_DIRECT argument format: [31] R/W flag [30:28] Function number [27] RAW flag [25:9] Register address [7:0] Data SDIO_CMD_RW_EXTENDED argument format: [31] R/W flag [30:28] Function number [27] Block mode [26] Increment address [25:9] Register address [8:0] Byte/block count SDIO Response Values (From: /include/linux/mmc/sdio.h) R4

◆ SDIO_RSP_R4_MEMORY_PRESENT

#define SDIO_RSP_R4_MEMORY_PRESENT (1 << 27)

◆ SDIO_RSP_R5_COM_CRC_ERROR

#define SDIO_RSP_R5_COM_CRC_ERROR (1 << 15)

R5

◆ SDIO_RSP_R5_ILLEGAL_COMMAND

#define SDIO_RSP_R5_ILLEGAL_COMMAND (1 << 14)

◆ SDIO_RSP_R5_ERROR

#define SDIO_RSP_R5_ERROR (1 << 11)

◆ SDIO_RSP_R5_FUNCTION_NUMBER

#define SDIO_RSP_R5_FUNCTION_NUMBER (1 << 9)

◆ SDIO_RSP_R5_OUT_OF_RANGE

#define SDIO_RSP_R5_OUT_OF_RANGE (1 << 8)

◆ SDIO_CCCR_CCCR

#define SDIO_CCCR_CCCR 0x00

SDIO_RSP_R5_STATUS(x) (x & 0xCB00) SDIO_RSP_R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b *‍/ SDIO status in R5 Type e : error bit s : status bit r : detected and set for the actual command response x : detected and set during command execution. the host must poll the card by sending status command in order to read these bits. Clear condition a : according to the card state b : always related to the previous command. Reception of a valid command will clear it (with a delay of one command) c : clear by read SDIO Card Common Control Registers (CCCR)

◆ SDIO_CCCR_SD

#define SDIO_CCCR_SD 0x01

◆ SDIO_CCCR_IOEx

#define SDIO_CCCR_IOEx 0x02

◆ SDIO_CCCR_IORx

#define SDIO_CCCR_IORx 0x03

◆ SDIO_CCCR_IENx

#define SDIO_CCCR_IENx 0x04

Function/Master Interrupt Enable.

◆ SDIO_CCCR_INTx

#define SDIO_CCCR_INTx 0x05

Function Interrupt Pending.

◆ SDIO_CCCR_ABORT

#define SDIO_CCCR_ABORT 0x06

Function abort/card reset.

◆ SDIO_CCCR_IF

#define SDIO_CCCR_IF 0x07

Bus interface controls.

◆ SDIO_CCCR_CAPS

#define SDIO_CCCR_CAPS 0x08

◆ SDIO_CCCR_CIS

#define SDIO_CCCR_CIS 0x09

Common CIS pointer (3 bytes).

◆ SDIO_CCCR_SUSPEND

#define SDIO_CCCR_SUSPEND 0x0c

Following 4 regs are valid only if SBS is set

◆ SDIO_CCCR_SELx

#define SDIO_CCCR_SELx 0x0d

◆ SDIO_CCCR_EXECx

#define SDIO_CCCR_EXECx 0x0e

◆ SDIO_CCCR_READYx

#define SDIO_CCCR_READYx 0x0f

◆ SDIO_CCCR_BLKSIZE

#define SDIO_CCCR_BLKSIZE 0x10

◆ SDIO_CCCR_POWER

#define SDIO_CCCR_POWER 0x12

◆ SDIO_CCCR_SPEED

#define SDIO_CCCR_SPEED 0x13

◆ SDIO_CCCR_UHS

#define SDIO_CCCR_UHS 0x14

◆ SDIO_CCCR_DRIVE_STRENGTH

#define SDIO_CCCR_DRIVE_STRENGTH 0x15

◆ SDIO_CCCR_REV_1_00

#define SDIO_CCCR_REV_1_00 0

CCCR/FBR Version 1.00.

SDIO CCCR CCCR Register values

◆ SDIO_CCCR_REV_1_10

#define SDIO_CCCR_REV_1_10 1

CCCR/FBR Version 1.10.

◆ SDIO_CCCR_REV_1_20

#define SDIO_CCCR_REV_1_20 2

CCCR/FBR Version 1.20.

◆ SDIO_CCCR_REV_3_00

#define SDIO_CCCR_REV_3_00 3

CCCR/FBR Version 3.00.

◆ SDIO_SDIO_REV_1_00

#define SDIO_SDIO_REV_1_00 0

SDIO Spec Version 1.00.

◆ SDIO_SDIO_REV_1_10

#define SDIO_SDIO_REV_1_10 1

SDIO Spec Version 1.10.

◆ SDIO_SDIO_REV_1_20

#define SDIO_SDIO_REV_1_20 2

SDIO Spec Version 1.20.

◆ SDIO_SDIO_REV_2_00

#define SDIO_SDIO_REV_2_00 3

SDIO Spec Version 2.00.

◆ SDIO_SDIO_REV_3_00

#define SDIO_SDIO_REV_3_00 4

SDIO Spec Version 3.00.

◆ SDIO_SD_REV_1_01

#define SDIO_SD_REV_1_01 0

SD Physical Spec Version 1.01.

SDIO CCCR SD Register values

◆ SDIO_SD_REV_1_10

#define SDIO_SD_REV_1_10 1

SD Physical Spec Version 1.10.

◆ SDIO_SD_REV_2_00

#define SDIO_SD_REV_2_00 2

SD Physical Spec Version 2.00.

◆ SDIO_SD_REV_3_00

#define SDIO_SD_REV_3_00 3

SD Physical Spev Version 3.00.

◆ SDIO_BUS_WIDTH_MASK

#define SDIO_BUS_WIDTH_MASK 0x03

data bus width setting

SDIO CCCR IF Register values

◆ SDIO_BUS_WIDTH_1BIT

#define SDIO_BUS_WIDTH_1BIT 0x00

◆ SDIO_BUS_WIDTH_RESERVED

#define SDIO_BUS_WIDTH_RESERVED 0x01

◆ SDIO_BUS_WIDTH_4BIT

#define SDIO_BUS_WIDTH_4BIT 0x02

◆ SDIO_BUS_ECSI

#define SDIO_BUS_ECSI 0x20

Enable continuous SPI interrupt.

◆ SDIO_BUS_SCSI

#define SDIO_BUS_SCSI 0x40

Support continuous SPI interrupt.

◆ SDIO_BUS_ASYNC_INT

#define SDIO_BUS_ASYNC_INT 0x20

◆ SDIO_BUS_CD_DISABLE

#define SDIO_BUS_CD_DISABLE 0x80

disable pull-up on DAT3 (pin 1)

◆ SDIO_CCCR_CAP_SDC

#define SDIO_CCCR_CAP_SDC 0x01

Can do CMD52 while data transfer.

SDIO CCCR CAPS Register values

◆ SDIO_CCCR_CAP_SMB

#define SDIO_CCCR_CAP_SMB 0x02

Can do multi-block xfers (CMD53).

◆ SDIO_CCCR_CAP_SRW

#define SDIO_CCCR_CAP_SRW 0x04

Supports read-wait protocol.

◆ SDIO_CCCR_CAP_SBS

#define SDIO_CCCR_CAP_SBS 0x08

Supports suspend/resume.

◆ SDIO_CCCR_CAP_S4MI

#define SDIO_CCCR_CAP_S4MI 0x10

Interrupt during 4-bit CMD53.

◆ SDIO_CCCR_CAP_E4MI

#define SDIO_CCCR_CAP_E4MI 0x20

Enable ints during 4-bit CMD53.

◆ SDIO_CCCR_CAP_LSC

#define SDIO_CCCR_CAP_LSC 0x40

Low speed card.

◆ SDIO_CCCR_CAP_4BLS

#define SDIO_CCCR_CAP_4BLS 0x80

4 bit low speed card

◆ SDIO_POWER_SMPC

#define SDIO_POWER_SMPC 0x01

Supports Master Power Control.

SDIO CCCR POWER Register values

◆ SDIO_POWER_EMPC

#define SDIO_POWER_EMPC 0x02

Enable Master Power Control.

◆ SDIO_SPEED_SHS

#define SDIO_SPEED_SHS 0x01

Supports High-Speed mode.

SDIO CCCR SPEED Register values

◆ SDIO_SPEED_BSS_SHIFT

#define SDIO_SPEED_BSS_SHIFT 1

◆ SDIO_SPEED_BSS_MASK

#define SDIO_SPEED_BSS_MASK (7 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_SDR12

#define SDIO_SPEED_SDR12 (0 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_SDR25

#define SDIO_SPEED_SDR25 (1 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_SDR50

#define SDIO_SPEED_SDR50 (2 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_SDR104

#define SDIO_SPEED_SDR104 (3 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_DDR50

#define SDIO_SPEED_DDR50 (4 << SDIO_SPEED_BSS_SHIFT)

◆ SDIO_SPEED_EHS

#define SDIO_SPEED_EHS SDIO_SPEED_SDR25

Enable High-Speed.

◆ SDIO_UHS_SDR50

#define SDIO_UHS_SDR50 0x01

SDIO CCCR UHS Register values

◆ SDIO_UHS_SDR104

#define SDIO_UHS_SDR104 0x02

◆ SDIO_UHS_DDR50

#define SDIO_UHS_DDR50 0x04

◆ SDIO_SDTx_MASK

#define SDIO_SDTx_MASK 0x07

SDIO CCCR DRIVE STRENGTH Register values

◆ SDIO_DRIVE_SDTA

#define SDIO_DRIVE_SDTA (1 << 0)

◆ SDIO_DRIVE_SDTC

#define SDIO_DRIVE_SDTC (1 << 1)

◆ SDIO_DRIVE_SDTD

#define SDIO_DRIVE_SDTD (1 << 2)

◆ SDIO_DRIVE_DTSx_MASK

#define SDIO_DRIVE_DTSx_MASK 0x03

◆ SDIO_DRIVE_DTSx_SHIFT

#define SDIO_DRIVE_DTSx_SHIFT 4

◆ SDIO_DTSx_SET_TYPE_B

#define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)

◆ SDIO_DTSx_SET_TYPE_A

#define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)

◆ SDIO_DTSx_SET_TYPE_C

#define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)

◆ SDIO_DTSx_SET_TYPE_D

#define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)

◆ SDIO_FBR_BASE

#define SDIO_FBR_BASE ( f )

Value:

((f) * 0x100) /* base of function f's FBRs */

SDIO Function Basic Registers (FBR)

◆ SDIO_FBR_STD_IF

#define SDIO_FBR_STD_IF 0x00

◆ SDIO_FBR_STD_IF_EXT

#define SDIO_FBR_STD_IF_EXT 0x01

◆ SDIO_FBR_POWER

#define SDIO_FBR_POWER 0x02

◆ SDIO_FBR_CIS

#define SDIO_FBR_CIS 0x09

CIS pointer (3 bytes).

◆ SDIO_FBR_CSA

#define SDIO_FBR_CSA 0x0C

CSA pointer (3 bytes).

◆ SDIO_FBR_CSA_DATA

#define SDIO_FBR_CSA_DATA 0x0F

◆ SDIO_FBR_BLKSIZE

#define SDIO_FBR_BLKSIZE 0x10

Block size (2 bytes).

◆ SDIO_FBR_SUPPORTS_CSA

#define SDIO_FBR_SUPPORTS_CSA 0x40

Supports Code Storage Area.

SDIO FBR IF Register values

◆ SDIO_FBR_ENABLE_CSA

#define SDIO_FBR_ENABLE_CSA 0x80

Enable Code Storage Area.

◆ SDIO_FBR_POWER_SPS

#define SDIO_FBR_POWER_SPS 0x01

Supports Power Selection.

SDIO FBR POWER Register values

◆ SDIO_FBR_POWER_EPS

#define SDIO_FBR_POWER_EPS 0x02

Enable (low) Power Selection.

◆ SDIO_CLASS_NONE

#define SDIO_CLASS_NONE 0x00

Not a SDIO standard interface.

SDIO Function Classes

◆ SDIO_CLASS_UART

#define SDIO_CLASS_UART 0x01

Standard UART interface.

◆ SDIO_CLASS_BT_A

#define SDIO_CLASS_BT_A 0x02

Type-A BlueTooth std interface.

◆ SDIO_CLASS_BT_B

#define SDIO_CLASS_BT_B 0x03

Type-B BlueTooth std interface.

◆ SDIO_CLASS_GPS

#define SDIO_CLASS_GPS 0x04

GPS standard interface.

◆ SDIO_CLASS_CAMERA

#define SDIO_CLASS_CAMERA 0x05

Camera standard interface.

◆ SDIO_CLASS_PHS

#define SDIO_CLASS_PHS 0x06

PHS standard interface.

◆ SDIO_CLASS_WLAN

#define SDIO_CLASS_WLAN 0x07

WLAN interface.

◆ SDIO_CLASS_ATA

#define SDIO_CLASS_ATA 0x08

Embedded SDIO-ATA std interface.

◆ SDIO_CLASS_BT_AMP

#define SDIO_CLASS_BT_AMP 0x09

Type-A Bluetooth AMP interface.

◆ SDIO_VENDOR_ID_STE

#define SDIO_VENDOR_ID_STE 0x0020

SDIO Vendors

◆ SDIO_VENDOR_ID_INTEL

#define SDIO_VENDOR_ID_INTEL 0x0089

◆ SDIO_VENDOR_ID_CGUYS

#define SDIO_VENDOR_ID_CGUYS 0x0092

◆ SDIO_VENDOR_ID_TI

#define SDIO_VENDOR_ID_TI 0x0097

◆ SDIO_VENDOR_ID_ATHEROS

#define SDIO_VENDOR_ID_ATHEROS 0x0271

◆ SDIO_VENDOR_ID_BROADCOM

#define SDIO_VENDOR_ID_BROADCOM 0x02d0

◆ SDIO_VENDOR_ID_MARVELL

#define SDIO_VENDOR_ID_MARVELL 0x02df

◆ SDIO_VENDOR_ID_MEDIATEK

#define SDIO_VENDOR_ID_MEDIATEK 0x037a

◆ SDIO_VENDOR_ID_MICROCHIP_WILC

#define SDIO_VENDOR_ID_MICROCHIP_WILC 0x0296

◆ SDIO_VENDOR_ID_SIANO

#define SDIO_VENDOR_ID_SIANO 0x039a

◆ SDIO_VENDOR_ID_RSI

#define SDIO_VENDOR_ID_RSI 0x041b

◆ SDIO_VENDOR_ID_TI_WL1251

#define SDIO_VENDOR_ID_TI_WL1251 0x104c

◆ SDIO_DEVICE_ID_STE_CW1200

#define SDIO_DEVICE_ID_STE_CW1200 0x2280

SDIO Devices

◆ SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX

#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402

◆ SDIO_DEVICE_ID_INTEL_IWMC3200WIFI

#define SDIO_DEVICE_ID_INTEL_IWMC3200WIFI 0x1403

◆ SDIO_DEVICE_ID_INTEL_IWMC3200TOP

#define SDIO_DEVICE_ID_INTEL_IWMC3200TOP 0x1404

◆ SDIO_DEVICE_ID_INTEL_IWMC3200GPS

#define SDIO_DEVICE_ID_INTEL_IWMC3200GPS 0x1405

◆ SDIO_DEVICE_ID_INTEL_IWMC3200BT

#define SDIO_DEVICE_ID_INTEL_IWMC3200BT 0x1406

◆ SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX_2G5

#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX_2G5 0x1407

◆ SDIO_DEVICE_ID_CGUYS_EW_CG1102GC

#define SDIO_DEVICE_ID_CGUYS_EW_CG1102GC 0x0004

◆ SDIO_DEVICE_ID_TI_WL1271

#define SDIO_DEVICE_ID_TI_WL1271 0x4076

◆ SDIO_DEVICE_ID_ATHEROS_AR6003_00

#define SDIO_DEVICE_ID_ATHEROS_AR6003_00 0x0300

◆ SDIO_DEVICE_ID_ATHEROS_AR6003_01

#define SDIO_DEVICE_ID_ATHEROS_AR6003_01 0x0301

◆ SDIO_DEVICE_ID_ATHEROS_AR6004_00

#define SDIO_DEVICE_ID_ATHEROS_AR6004_00 0x0400

◆ SDIO_DEVICE_ID_ATHEROS_AR6004_01

#define SDIO_DEVICE_ID_ATHEROS_AR6004_01 0x0401

◆ SDIO_DEVICE_ID_ATHEROS_AR6004_02

#define SDIO_DEVICE_ID_ATHEROS_AR6004_02 0x0402

◆ SDIO_DEVICE_ID_ATHEROS_AR6004_18

#define SDIO_DEVICE_ID_ATHEROS_AR6004_18 0x0418

◆ SDIO_DEVICE_ID_ATHEROS_AR6004_19

#define SDIO_DEVICE_ID_ATHEROS_AR6004_19 0x0419

◆ SDIO_DEVICE_ID_ATHEROS_AR6005

#define SDIO_DEVICE_ID_ATHEROS_AR6005 0x050A

◆ SDIO_DEVICE_ID_ATHEROS_QCA9377

#define SDIO_DEVICE_ID_ATHEROS_QCA9377 0x0701

◆ SDIO_DEVICE_ID_BROADCOM_NINTENDO_WII

#define SDIO_DEVICE_ID_BROADCOM_NINTENDO_WII 0x044b

◆ SDIO_DEVICE_ID_BROADCOM_43241

#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324

◆ SDIO_DEVICE_ID_BROADCOM_4329

#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329

◆ SDIO_DEVICE_ID_BROADCOM_4330

#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330

◆ SDIO_DEVICE_ID_BROADCOM_4334

#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334

◆ SDIO_DEVICE_ID_BROADCOM_4335_4339

#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335

◆ SDIO_DEVICE_ID_BROADCOM_4339

#define SDIO_DEVICE_ID_BROADCOM_4339 0x4339

◆ SDIO_DEVICE_ID_BROADCOM_4345

#define SDIO_DEVICE_ID_BROADCOM_4345 0x4345

◆ SDIO_DEVICE_ID_BROADCOM_4354

#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354

◆ SDIO_DEVICE_ID_BROADCOM_CYPRESS_89359

#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_89359 0x4355

◆ SDIO_DEVICE_ID_BROADCOM_4356

#define SDIO_DEVICE_ID_BROADCOM_4356 0x4356

◆ SDIO_DEVICE_ID_BROADCOM_4359

#define SDIO_DEVICE_ID_BROADCOM_4359 0x4359

◆ SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373

#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373 0x4373

◆ SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012

#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012 0xa804

◆ SDIO_DEVICE_ID_BROADCOM_43143

#define SDIO_DEVICE_ID_BROADCOM_43143 0xa887

◆ SDIO_DEVICE_ID_BROADCOM_43340

#define SDIO_DEVICE_ID_BROADCOM_43340 0xa94c

◆ SDIO_DEVICE_ID_BROADCOM_43341

#define SDIO_DEVICE_ID_BROADCOM_43341 0xa94d

◆ SDIO_DEVICE_ID_BROADCOM_43362

#define SDIO_DEVICE_ID_BROADCOM_43362 0xa962

◆ SDIO_DEVICE_ID_BROADCOM_43364

#define SDIO_DEVICE_ID_BROADCOM_43364 0xa9a4

◆ SDIO_DEVICE_ID_BROADCOM_43430

#define SDIO_DEVICE_ID_BROADCOM_43430 0xa9a6

◆ SDIO_DEVICE_ID_BROADCOM_43455

#define SDIO_DEVICE_ID_BROADCOM_43455 0xa9bf

◆ SDIO_DEVICE_ID_MARVELL_LIBERTAS

#define SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103

◆ SDIO_DEVICE_ID_MARVELL_8688_WLAN

#define SDIO_DEVICE_ID_MARVELL_8688_WLAN 0x9104

◆ SDIO_DEVICE_ID_MARVELL_8688_BT

#define SDIO_DEVICE_ID_MARVELL_8688_BT 0x9105

◆ SDIO_DEVICE_ID_MARVELL_8786_WLAN

#define SDIO_DEVICE_ID_MARVELL_8786_WLAN 0x9116

◆ SDIO_DEVICE_ID_MARVELL_8787_WLAN

#define SDIO_DEVICE_ID_MARVELL_8787_WLAN 0x9119

◆ SDIO_DEVICE_ID_MARVELL_8787_BT

#define SDIO_DEVICE_ID_MARVELL_8787_BT 0x911a

◆ SDIO_DEVICE_ID_MARVELL_8787_BT_AMP

#define SDIO_DEVICE_ID_MARVELL_8787_BT_AMP 0x911b

◆ SDIO_DEVICE_ID_MARVELL_8797_F0

#define SDIO_DEVICE_ID_MARVELL_8797_F0 0x9128

◆ SDIO_DEVICE_ID_MARVELL_8797_WLAN

#define SDIO_DEVICE_ID_MARVELL_8797_WLAN 0x9129

◆ SDIO_DEVICE_ID_MARVELL_8797_BT

#define SDIO_DEVICE_ID_MARVELL_8797_BT 0x912a

◆ SDIO_DEVICE_ID_MARVELL_8897_WLAN

#define SDIO_DEVICE_ID_MARVELL_8897_WLAN 0x912d

◆ SDIO_DEVICE_ID_MARVELL_8897_BT

#define SDIO_DEVICE_ID_MARVELL_8897_BT 0x912e

◆ SDIO_DEVICE_ID_MARVELL_8887_F0

#define SDIO_DEVICE_ID_MARVELL_8887_F0 0x9134

◆ SDIO_DEVICE_ID_MARVELL_8887_WLAN

#define SDIO_DEVICE_ID_MARVELL_8887_WLAN 0x9135

◆ SDIO_DEVICE_ID_MARVELL_8887_BT

#define SDIO_DEVICE_ID_MARVELL_8887_BT 0x9136

◆ SDIO_DEVICE_ID_MARVELL_8801_WLAN

#define SDIO_DEVICE_ID_MARVELL_8801_WLAN 0x9139

◆ SDIO_DEVICE_ID_MARVELL_8997_F0

#define SDIO_DEVICE_ID_MARVELL_8997_F0 0x9140

◆ SDIO_DEVICE_ID_MARVELL_8997_WLAN

#define SDIO_DEVICE_ID_MARVELL_8997_WLAN 0x9141

◆ SDIO_DEVICE_ID_MARVELL_8997_BT

#define SDIO_DEVICE_ID_MARVELL_8997_BT 0x9142

◆ SDIO_DEVICE_ID_MARVELL_8977_WLAN

#define SDIO_DEVICE_ID_MARVELL_8977_WLAN 0x9145

◆ SDIO_DEVICE_ID_MARVELL_8977_BT

#define SDIO_DEVICE_ID_MARVELL_8977_BT 0x9146

◆ SDIO_DEVICE_ID_MARVELL_8987_WLAN

#define SDIO_DEVICE_ID_MARVELL_8987_WLAN 0x9149

◆ SDIO_DEVICE_ID_MARVELL_8987_BT

#define SDIO_DEVICE_ID_MARVELL_8987_BT 0x914a

◆ SDIO_DEVICE_ID_MEDIATEK_MT7663

#define SDIO_DEVICE_ID_MEDIATEK_MT7663 0x7663

◆ SDIO_DEVICE_ID_MEDIATEK_MT7668

#define SDIO_DEVICE_ID_MEDIATEK_MT7668 0x7668

◆ SDIO_DEVICE_ID_MICROCHIP_WILC1000

#define SDIO_DEVICE_ID_MICROCHIP_WILC1000 0x5347

◆ SDIO_DEVICE_ID_SIANO_NOVA_B0

#define SDIO_DEVICE_ID_SIANO_NOVA_B0 0x0201

◆ SDIO_DEVICE_ID_SIANO_NICE

#define SDIO_DEVICE_ID_SIANO_NICE 0x0202

◆ SDIO_DEVICE_ID_SIANO_VEGA_A0

#define SDIO_DEVICE_ID_SIANO_VEGA_A0 0x0300

◆ SDIO_DEVICE_ID_SIANO_VENICE

#define SDIO_DEVICE_ID_SIANO_VENICE 0x0301

◆ SDIO_DEVICE_ID_SIANO_MING

#define SDIO_DEVICE_ID_SIANO_MING 0x0302

◆ SDIO_DEVICE_ID_SIANO_PELE

#define SDIO_DEVICE_ID_SIANO_PELE 0x0500

◆ SDIO_DEVICE_ID_SIANO_RIO

#define SDIO_DEVICE_ID_SIANO_RIO 0x0600

◆ SDIO_DEVICE_ID_SIANO_DENVER_2160

#define SDIO_DEVICE_ID_SIANO_DENVER_2160 0x0700

◆ SDIO_DEVICE_ID_SIANO_DENVER_1530

#define SDIO_DEVICE_ID_SIANO_DENVER_1530 0x0800

◆ SDIO_DEVICE_ID_SIANO_NOVA_A0

#define SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100

◆ SDIO_DEVICE_ID_SIANO_STELLAR

#define SDIO_DEVICE_ID_SIANO_STELLAR 0x5347

◆ SDIO_DEVICE_ID_TI_WL1251

#define SDIO_DEVICE_ID_TI_WL1251 0x9066

◆ CISTPL_NULL

#define CISTPL_NULL 0x00

SDIO CIS Tuple Codes

◆ CISTPL_CHECKSUM

#define CISTPL_CHECKSUM 0x10

◆ CISTPL_VERS_1

#define CISTPL_VERS_1 0x15

◆ CISTPL_ALTSTR

#define CISTPL_ALTSTR 0x16

◆ CISTPL_MANFID

#define CISTPL_MANFID 0x20

◆ CISTPL_FUNCID

#define CISTPL_FUNCID 0x21

◆ CISTPL_FUNCE

#define CISTPL_FUNCE 0x22

◆ CISTPL_SDIO_STD

#define CISTPL_SDIO_STD 0x91

◆ CISTPL_SDIO_EXT

#define CISTPL_SDIO_EXT 0x92

◆ CISTPL_END

#define CISTPL_END 0xFF

◆ SDIO_MAX_FUNCTIONS

#define SDIO_MAX_FUNCTIONS 7

◆ SDIO_READ_CIS_TIMEOUT_MS

#define SDIO_READ_CIS_TIMEOUT_MS (10 * 1000)

10 seconds

◆ SDHCI_NAME_PREFIX

#define SDHCI_NAME_PREFIX "SDHCI"

Name prefix for SDHCI Devices.

SDHCI specific constants

◆ SDHCI_TYPE_NONE

#define SDHCI_TYPE_NONE 0

SDHCI Host Types

◆ SDHCI_TYPE_MMC

#define SDHCI_TYPE_MMC 1

An MMC specification host controller.

◆ SDHCI_TYPE_SD

#define SDHCI_TYPE_SD 2

An SD specification host controller.

◆ SDHCI_TYPE_MMCI

#define SDHCI_TYPE_MMCI 3

An MMCI specification host controller.

◆ SDHCI_TYPE_MAX

#define SDHCI_TYPE_MAX 3

◆ SDHCI_STATE_DISABLED

#define SDHCI_STATE_DISABLED 0

SDHCI Host States

◆ SDHCI_STATE_ENABLED

#define SDHCI_STATE_ENABLED 1

◆ SDHCI_STATE_MAX

#define SDHCI_STATE_MAX 1

◆ SDHCI_FLAG_NONE

#define SDHCI_FLAG_NONE 0x00000000

SDHCI Host Flags

◆ SDHCI_FLAG_SDMA

#define SDHCI_FLAG_SDMA 0x00000001

Host Controller supports SDMA specification.

◆ SDHCI_FLAG_ADMA

#define SDHCI_FLAG_ADMA 0x00000002

Host Controller supports ADMA specification.

◆ SDHCI_FLAG_SPI

#define SDHCI_FLAG_SPI 0x00000004

Host Controller uses SPI interface.

◆ SDHCI_FLAG_CRC_ENABLE

#define SDHCI_FLAG_CRC_ENABLE 0x00000008

◆ SDHCI_FLAG_NON_STANDARD

#define SDHCI_FLAG_NON_STANDARD 0x00000010

Host Controller uses a non standard interface (not supporting SDHCI register layout).

◆ SDHCI_FLAG_AUTO_CMD12

#define SDHCI_FLAG_AUTO_CMD12 0x00000020

Host Controller supports Auto CMD12 (Stop Transmission).

◆ SDHCI_FLAG_AUTO_CMD23

#define SDHCI_FLAG_AUTO_CMD23 0x00000040

Host Controller supports Auto CMD23 (Set Block Count).

◆ SDHCI_FLAG_64_BIT_DMA

#define SDHCI_FLAG_64_BIT_DMA 0x00000080

Host Controller supports 64-bit ADMA.

◆ SDHCI_FLAG_EXTERNAL_DMA

#define SDHCI_FLAG_EXTERNAL_DMA 0x00000100

Host Controller requires external DMA engine to perform transfers.

◆ SDHCI_FLAG_BUS_ADDRESSES

#define SDHCI_FLAG_BUS_ADDRESSES 0x00000200

Host Controller requires use of bus addresses for SDMA/ADMA transfers.

◆ SDHCI_DMA_ADDRESS

#define SDHCI_DMA_ADDRESS 0x00

SDHCI Controller Registers

◆ SDHCI_ARGUMENT2

#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS

◆ SDHCI_32BIT_BLK_CNT

#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS

◆ SDHCI_BLOCK_SIZE

#define SDHCI_BLOCK_SIZE 0x04

◆ SDHCI_BLOCK_COUNT

#define SDHCI_BLOCK_COUNT 0x06

◆ SDHCI_ARGUMENT

#define SDHCI_ARGUMENT 0x08

◆ SDHCI_TRANSFER_MODE

#define SDHCI_TRANSFER_MODE 0x0C

◆ SDHCI_COMMAND

#define SDHCI_COMMAND 0x0E

◆ SDHCI_RESPONSE

#define SDHCI_RESPONSE 0x10

◆ SDHCI_BUFFER

#define SDHCI_BUFFER 0x20

◆ SDHCI_PRESENT_STATE

#define SDHCI_PRESENT_STATE 0x24

◆ SDHCI_HOST_CONTROL

#define SDHCI_HOST_CONTROL 0x28

◆ SDHCI_POWER_CONTROL

#define SDHCI_POWER_CONTROL 0x29

◆ SDHCI_BLOCK_GAP_CONTROL

#define SDHCI_BLOCK_GAP_CONTROL 0x2A

◆ SDHCI_WAKE_UP_CONTROL

#define SDHCI_WAKE_UP_CONTROL 0x2B

◆ SDHCI_CLOCK_CONTROL

#define SDHCI_CLOCK_CONTROL 0x2C

◆ SDHCI_TIMEOUT_CONTROL

#define SDHCI_TIMEOUT_CONTROL 0x2E

◆ SDHCI_SOFTWARE_RESET

#define SDHCI_SOFTWARE_RESET 0x2F

◆ SDHCI_INT_STATUS

#define SDHCI_INT_STATUS 0x30

◆ SDHCI_INT_ENABLE

#define SDHCI_INT_ENABLE 0x34

◆ SDHCI_SIGNAL_ENABLE

#define SDHCI_SIGNAL_ENABLE 0x38

◆ SDHCI_AUTO_CMD_STATUS

#define SDHCI_AUTO_CMD_STATUS 0x3C

SDHCI_ACMD12_ERR.

◆ SDHCI_HOST_CONTROL2

#define SDHCI_HOST_CONTROL2 0x3E

◆ SDHCI_CAPABILITIES

#define SDHCI_CAPABILITIES 0x40

◆ SDHCI_CAPABILITIES_1

#define SDHCI_CAPABILITIES_1 0x44

◆ SDHCI_MAX_CURRENT

#define SDHCI_MAX_CURRENT 0x48

◆ SDHCI_SET_ACMD12_ERROR

#define SDHCI_SET_ACMD12_ERROR 0x50

4C-4F reserved for more max current

◆ SDHCI_SET_INT_ERROR

#define SDHCI_SET_INT_ERROR 0x52

◆ SDHCI_ADMA_ERROR

#define SDHCI_ADMA_ERROR 0x54

◆ SDHCI_ADMA_ADDRESS

#define SDHCI_ADMA_ADDRESS 0x58

55-57 reserved

◆ SDHCI_ADMA_ADDRESS_HI

#define SDHCI_ADMA_ADDRESS_HI 0x5C

◆ SDHCI_PRESET_FOR_SDR12

#define SDHCI_PRESET_FOR_SDR12 0x66

5D-65 reserved

◆ SDHCI_PRESET_FOR_SDR25

#define SDHCI_PRESET_FOR_SDR25 0x68

◆ SDHCI_PRESET_FOR_SDR50

#define SDHCI_PRESET_FOR_SDR50 0x6A

◆ SDHCI_PRESET_FOR_SDR104

#define SDHCI_PRESET_FOR_SDR104 0x6C

◆ SDHCI_PRESET_FOR_DDR50

#define SDHCI_PRESET_FOR_DDR50 0x6E

◆ SDHCI_PRESET_FOR_HS400

#define SDHCI_PRESET_FOR_HS400 0x74

Non-standard.

6F-73 reserved

◆ SDHCI_SLOT_INT_STATUS

#define SDHCI_SLOT_INT_STATUS 0xFC

75-FB reserved

◆ SDHCI_HOST_VERSION

#define SDHCI_HOST_VERSION 0xFE

◆ SDHCI_TRNS_DMA

#define SDHCI_TRNS_DMA 0x01

SDHCI Transfer Modes

◆ SDHCI_TRNS_BLK_CNT_EN

#define SDHCI_TRNS_BLK_CNT_EN 0x02

◆ SDHCI_TRNS_AUTO_CMD12

#define SDHCI_TRNS_AUTO_CMD12 0x04

SDHCI_TRNS_ACMD12.

◆ SDHCI_TRNS_AUTO_CMD23

#define SDHCI_TRNS_AUTO_CMD23 0x08

◆ SDHCI_TRNS_AUTO_SEL

#define SDHCI_TRNS_AUTO_SEL SDHCI_TRNS_AUTO_CMD12 | SDHCI_TRNS_AUTO_CMD23

◆ SDHCI_TRNS_READ

#define SDHCI_TRNS_READ 0x10

◆ SDHCI_TRNS_MULTI

#define SDHCI_TRNS_MULTI 0x20

◆ SDHCI_CMD_RESP_MASK

#define SDHCI_CMD_RESP_MASK 0x03

SDHCI Command Values

◆ SDHCI_CMD_CRC

#define SDHCI_CMD_CRC 0x08

◆ SDHCI_CMD_INDEX

#define SDHCI_CMD_INDEX 0x10

◆ SDHCI_CMD_DATA

#define SDHCI_CMD_DATA 0x20

◆ SDHCI_CMD_ABORTCMD

#define SDHCI_CMD_ABORTCMD 0xC0

◆ SDHCI_CMD_RESP_NONE

#define SDHCI_CMD_RESP_NONE 0x00

SDHCI Command Response Values

◆ SDHCI_CMD_RESP_LONG

#define SDHCI_CMD_RESP_LONG 0x01

◆ SDHCI_CMD_RESP_SHORT

#define SDHCI_CMD_RESP_SHORT 0x02

◆ SDHCI_CMD_RESP_SHORT_BUSY

#define SDHCI_CMD_RESP_SHORT_BUSY 0x03

◆ SDHCI_CMD_INHIBIT

#define SDHCI_CMD_INHIBIT 0x00000001

SDHCI Present State Values

◆ SDHCI_DATA_INHIBIT

#define SDHCI_DATA_INHIBIT 0x00000002

◆ SDHCI_DOING_WRITE

#define SDHCI_DOING_WRITE 0x00000100

◆ SDHCI_DOING_READ

#define SDHCI_DOING_READ 0x00000200

◆ SDHCI_SPACE_AVAILABLE

#define SDHCI_SPACE_AVAILABLE 0x00000400

◆ SDHCI_DATA_AVAILABLE

#define SDHCI_DATA_AVAILABLE 0x00000800

◆ SDHCI_CARD_PRESENT

#define SDHCI_CARD_PRESENT 0x00010000

◆ SDHCI_CARD_STATE_STABLE

#define SDHCI_CARD_STATE_STABLE 0x00020000

SDHCI_CD_STABLE.

◆ SDHCI_CARD_DETECT_PIN_LEVEL

#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000

SDHCI_CD_LVL.

◆ SDHCI_WRITE_PROTECT

#define SDHCI_WRITE_PROTECT 0x00080000

Set if Write Enabled / Clear if Write Protected.

◆ SDHCI_DATA_LEVEL_MASK

#define SDHCI_DATA_LEVEL_MASK 0x00F00000

SDHCI_DATA_LVL_MASK.

◆ SDHCI_DATA_0_LEVEL_MASK

#define SDHCI_DATA_0_LEVEL_MASK 0x00100000

SDHCI_DATA_0_LVL_MASK.

◆ SDHCI_CMD_LEVEL

#define SDHCI_CMD_LEVEL 0x01000000

SDHCI_CMD_LVL.

◆ SDHCI_CTRL_LED

#define SDHCI_CTRL_LED 0x01

SDHCI Host Control Values

◆ SDHCI_CTRL_4BITBUS

#define SDHCI_CTRL_4BITBUS 0x02

◆ SDHCI_CTRL_HISPD

#define SDHCI_CTRL_HISPD 0x04

◆ SDHCI_CTRL_DMA_MASK

#define SDHCI_CTRL_DMA_MASK 0x18

◆ SDHCI_CTRL_SDMA

#define SDHCI_CTRL_SDMA 0x00

◆ SDHCI_CTRL_ADMA1

#define SDHCI_CTRL_ADMA1 0x08

◆ SDHCI_CTRL_ADMA32

#define SDHCI_CTRL_ADMA32 0x10

◆ SDHCI_CTRL_ADMA64

#define SDHCI_CTRL_ADMA64 0x18

◆ SDHCI_CTRL_ADMA3

#define SDHCI_CTRL_ADMA3 0x18

◆ SDHCI_CTRL_8BITBUS

#define SDHCI_CTRL_8BITBUS 0x20

◆ SDHCI_CTRL_CD_TEST_INS

#define SDHCI_CTRL_CD_TEST_INS 0x40

◆ SDHCI_CTRL_CD_TEST

#define SDHCI_CTRL_CD_TEST 0x80

◆ SDHCI_POWER_ON

#define SDHCI_POWER_ON 0x01

SDHCI Power Control Values

◆ SDHCI_POWER_180

#define SDHCI_POWER_180 0x0A

◆ SDHCI_POWER_300

#define SDHCI_POWER_300 0x0C

◆ SDHCI_POWER_330

#define SDHCI_POWER_330 0x0E

◆ SDHCI_WAKE_ON_INT

#define SDHCI_WAKE_ON_INT 0x01

SDHCI Wakeup Control Values

◆ SDHCI_WAKE_ON_INSERT

#define SDHCI_WAKE_ON_INSERT 0x02

◆ SDHCI_WAKE_ON_REMOVE

#define SDHCI_WAKE_ON_REMOVE 0x04

◆ SDHCI_DIVIDER_SHIFT

#define SDHCI_DIVIDER_SHIFT 8

SDHCI Clock Control Values

◆ SDHCI_DIVIDER_HI_SHIFT

#define SDHCI_DIVIDER_HI_SHIFT 6

◆ SDHCI_DIV_MASK

#define SDHCI_DIV_MASK 0xFF

◆ SDHCI_DIV_MASK_LEN

#define SDHCI_DIV_MASK_LEN 8

◆ SDHCI_DIV_HI_MASK

#define SDHCI_DIV_HI_MASK 0x0300

◆ SDHCI_PROG_CLOCK_MODE

#define SDHCI_PROG_CLOCK_MODE 0x0020

◆ SDHCI_CLOCK_CARD_EN

#define SDHCI_CLOCK_CARD_EN 0x0004

◆ SDHCI_CLOCK_PLL_EN

#define SDHCI_CLOCK_PLL_EN 0x0008

◆ SDHCI_CLOCK_INT_STABLE

#define SDHCI_CLOCK_INT_STABLE 0x0002

◆ SDHCI_CLOCK_INT_EN

#define SDHCI_CLOCK_INT_EN 0x0001

◆ SDHCI_RESET_ALL

#define SDHCI_RESET_ALL 0x01

SDHCI Software Reset Values

◆ SDHCI_RESET_CMD

#define SDHCI_RESET_CMD 0x02

◆ SDHCI_RESET_DATA

#define SDHCI_RESET_DATA 0x04

◆ SDHCI_INT_RESPONSE

#define SDHCI_INT_RESPONSE 0x00000001

SDHCI Interrupt Values

◆ SDHCI_INT_DATA_END

#define SDHCI_INT_DATA_END 0x00000002

◆ SDHCI_INT_BLK_GAP

#define SDHCI_INT_BLK_GAP 0x00000004

◆ SDHCI_INT_DMA_END

#define SDHCI_INT_DMA_END 0x00000008

◆ SDHCI_INT_SPACE_AVAIL

#define SDHCI_INT_SPACE_AVAIL 0x00000010

◆ SDHCI_INT_DATA_AVAIL

#define SDHCI_INT_DATA_AVAIL 0x00000020

◆ SDHCI_INT_CARD_INSERT

#define SDHCI_INT_CARD_INSERT 0x00000040

◆ SDHCI_INT_CARD_REMOVE

#define SDHCI_INT_CARD_REMOVE 0x00000080

◆ SDHCI_INT_CARD_INT

#define SDHCI_INT_CARD_INT 0x00000100

◆ SDHCI_INT_RETUNE

#define SDHCI_INT_RETUNE 0x00001000

◆ SDHCI_INT_CQE

#define SDHCI_INT_CQE 0x00004000

◆ SDHCI_INT_ERROR

#define SDHCI_INT_ERROR 0x00008000

◆ SDHCI_INT_TIMEOUT

#define SDHCI_INT_TIMEOUT 0x00010000

◆ SDHCI_INT_CRC

#define SDHCI_INT_CRC 0x00020000

◆ SDHCI_INT_END_BIT

#define SDHCI_INT_END_BIT 0x00040000

◆ SDHCI_INT_INDEX

#define SDHCI_INT_INDEX 0x00080000

◆ SDHCI_INT_DATA_TIMEOUT

#define SDHCI_INT_DATA_TIMEOUT 0x00100000

◆ SDHCI_INT_DATA_CRC

#define SDHCI_INT_DATA_CRC 0x00200000

◆ SDHCI_INT_DATA_END_BIT

#define SDHCI_INT_DATA_END_BIT 0x00400000

◆ SDHCI_INT_BUS_POWER

#define SDHCI_INT_BUS_POWER 0x00800000

◆ SDHCI_INT_AUTO_CMD_ERR

#define SDHCI_INT_AUTO_CMD_ERR 0x01000000

SDHCI_INT_ACMD12ERR.

◆ SDHCI_INT_ADMA_ERROR

#define SDHCI_INT_ADMA_ERROR 0x02000000

◆ SDHCI_INT_NORMAL_MASK

#define SDHCI_INT_NORMAL_MASK 0x00007FFF

◆ SDHCI_INT_ERROR_MASK

#define SDHCI_INT_ERROR_MASK 0xFFFF8000

◆ SDHCI_INT_CMD_MASK

◆ SDHCI_INT_DATA_MASK

◆ SDHCI_INT_ALL_MASK

#define SDHCI_INT_ALL_MASK (LongWord(-1))

◆ SDHCI_CQE_INT_ERR_MASK

◆ SDHCI_CQE_INT_MASK

#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)

◆ SDHCI_AUTO_CMD_TIMEOUT

#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002

SDHCI Auto CMD Status Values

◆ SDHCI_AUTO_CMD_CRC

#define SDHCI_AUTO_CMD_CRC 0x00000004

◆ SDHCI_AUTO_CMD_END_BIT

#define SDHCI_AUTO_CMD_END_BIT 0x00000008

◆ SDHCI_AUTO_CMD_INDEX

#define SDHCI_AUTO_CMD_INDEX 0x00000010

◆ SDHCI_CTRL_UHS_MASK

#define SDHCI_CTRL_UHS_MASK 0x0007

SDHCI Host Control 2 Values

◆ SDHCI_CTRL_UHS_SDR12

#define SDHCI_CTRL_UHS_SDR12 0x0000

◆ SDHCI_CTRL_UHS_SDR25

#define SDHCI_CTRL_UHS_SDR25 0x0001

◆ SDHCI_CTRL_UHS_SDR50

#define SDHCI_CTRL_UHS_SDR50 0x0002

◆ SDHCI_CTRL_UHS_SDR104

#define SDHCI_CTRL_UHS_SDR104 0x0003

◆ SDHCI_CTRL_UHS_DDR50

#define SDHCI_CTRL_UHS_DDR50 0x0004

◆ SDHCI_CTRL_HS400

#define SDHCI_CTRL_HS400 0x0005

Non-standard.

◆ SDHCI_CTRL_VDD_180

#define SDHCI_CTRL_VDD_180 0x0008

◆ SDHCI_CTRL_DRV_TYPE_MASK

#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030

◆ SDHCI_CTRL_DRV_TYPE_B

#define SDHCI_CTRL_DRV_TYPE_B 0x0000

◆ SDHCI_CTRL_DRV_TYPE_A

#define SDHCI_CTRL_DRV_TYPE_A 0x0010

◆ SDHCI_CTRL_DRV_TYPE_C

#define SDHCI_CTRL_DRV_TYPE_C 0x0020

◆ SDHCI_CTRL_DRV_TYPE_D

#define SDHCI_CTRL_DRV_TYPE_D 0x0030

◆ SDHCI_CTRL_EXEC_TUNING

#define SDHCI_CTRL_EXEC_TUNING 0x0040

◆ SDHCI_CTRL_TUNED_CLK

#define SDHCI_CTRL_TUNED_CLK 0x0080

◆ SDHCI_CMD23_ENABLE

#define SDHCI_CMD23_ENABLE 0x0800

◆ SDHCI_CTRL_V4_MODE

#define SDHCI_CTRL_V4_MODE 0x1000

◆ SDHCI_CTRL_64BIT_ADDR

#define SDHCI_CTRL_64BIT_ADDR 0x2000

◆ SDHCI_CTRL_PRESET_VAL_ENABLE

#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000

◆ SDHCI_TIMEOUT_CLK_MASK

#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F

SDHCI Capabilities Values

◆ SDHCI_TIMEOUT_CLK_SHIFT

#define SDHCI_TIMEOUT_CLK_SHIFT 0

◆ SDHCI_TIMEOUT_CLK_UNIT

#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080

◆ SDHCI_CLOCK_BASE_MASK

#define SDHCI_CLOCK_BASE_MASK 0x00003F00

◆ SDHCI_CLOCK_V3_BASE_MASK

#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00

◆ SDHCI_CLOCK_BASE_SHIFT

#define SDHCI_CLOCK_BASE_SHIFT 8

◆ SDHCI_CLOCK_BASE_MULTIPLIER

#define SDHCI_CLOCK_BASE_MULTIPLIER 1000000

◆ SDHCI_MAX_BLOCK_MASK

#define SDHCI_MAX_BLOCK_MASK 0x00030000

◆ SDHCI_MAX_BLOCK_SHIFT

#define SDHCI_MAX_BLOCK_SHIFT 16

◆ SDHCI_CAN_DO_8BIT

#define SDHCI_CAN_DO_8BIT 0x00040000

◆ SDHCI_CAN_DO_ADMA2

#define SDHCI_CAN_DO_ADMA2 0x00080000

◆ SDHCI_CAN_DO_ADMA1

#define SDHCI_CAN_DO_ADMA1 0x00100000

◆ SDHCI_CAN_DO_HISPD

#define SDHCI_CAN_DO_HISPD 0x00200000

◆ SDHCI_CAN_DO_SDMA

#define SDHCI_CAN_DO_SDMA 0x00400000

◆ SDHCI_CAN_VDD_330

#define SDHCI_CAN_VDD_330 0x01000000

◆ SDHCI_CAN_VDD_300

#define SDHCI_CAN_VDD_300 0x02000000

◆ SDHCI_CAN_VDD_180

#define SDHCI_CAN_VDD_180 0x04000000

◆ SDHCI_CAN_64BIT_V4

#define SDHCI_CAN_64BIT_V4 0x08000000

◆ SDHCI_CAN_64BIT

#define SDHCI_CAN_64BIT 0x10000000

◆ SDHCI_SUPPORT_SDR50

#define SDHCI_SUPPORT_SDR50 0x00000001

SDHCI Capabilities 1 Values

◆ SDHCI_SUPPORT_SDR104

#define SDHCI_SUPPORT_SDR104 0x00000002

◆ SDHCI_SUPPORT_DDR50

#define SDHCI_SUPPORT_DDR50 0x00000004

◆ SDHCI_DRIVER_TYPE_A

#define SDHCI_DRIVER_TYPE_A 0x00000010

◆ SDHCI_DRIVER_TYPE_C

#define SDHCI_DRIVER_TYPE_C 0x00000020

◆ SDHCI_DRIVER_TYPE_D

#define SDHCI_DRIVER_TYPE_D 0x00000040

◆ SDHCI_RETUNING_TIMER_COUNT_MASK

#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00

GENMASK(11,8).

◆ SDHCI_USE_SDR50_TUNING

#define SDHCI_USE_SDR50_TUNING 0x00002000

◆ SDHCI_RETUNING_MODE_MASK

#define SDHCI_RETUNING_MODE_MASK 0x0000C000

GENMASK(15,14).

◆ SDHCI_CLOCK_MUL_MASK

#define SDHCI_CLOCK_MUL_MASK 0x00FF0000

GENMASK(23,16).

◆ SDHCI_CAN_DO_ADMA3

#define SDHCI_CAN_DO_ADMA3 0x08000000

◆ SDHCI_SUPPORT_HS400

#define SDHCI_SUPPORT_HS400 0x80000000

Non-standard.

◆ SDHCI_MAX_CURRENT_LIMIT

#define SDHCI_MAX_CURRENT_LIMIT 0x000000FF

GENMASK(7,0).

SDHCI Max Current Values

◆ SDHCI_MAX_CURRENT_330_MASK

#define SDHCI_MAX_CURRENT_330_MASK 0x000000FF

GENMASK(7,0).

◆ SDHCI_MAX_CURRENT_300_MASK

#define SDHCI_MAX_CURRENT_300_MASK 0x0000FF00

GENMASK(15,8).

◆ SDHCI_MAX_CURRENT_180_MASK

#define SDHCI_MAX_CURRENT_180_MASK 0x00FF0000

GENMASK(23,16).

◆ SDHCI_MAX_CURRENT_MULTIPLIER

#define SDHCI_MAX_CURRENT_MULTIPLIER 4

◆ SDHCI_PRESET_DRV_MASK

#define SDHCI_PRESET_DRV_MASK 0x0000C000

GENMASK(15,14).

SDHCI Preset Values

◆ SDHCI_PRESET_DRV_SHIFT

#define SDHCI_PRESET_DRV_SHIFT 14

◆ SDHCI_PRESET_CLKGEN_SEL

#define SDHCI_PRESET_CLKGEN_SEL 1 << 10

BIT(10).

◆ SDHCI_PRESET_SDCLK_FREQ_MASK

#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x000003FF

GENMASK(9,0).

◆ SDHCI_VENDOR_VER_MASK

#define SDHCI_VENDOR_VER_MASK 0xFF00

SDHCI Host Version Values

◆ SDHCI_VENDOR_VER_SHIFT

#define SDHCI_VENDOR_VER_SHIFT 8

◆ SDHCI_SPEC_VER_MASK

#define SDHCI_SPEC_VER_MASK 0x00FF

◆ SDHCI_SPEC_VER_SHIFT

#define SDHCI_SPEC_VER_SHIFT 0

◆ SDHCI_SPEC_100

#define SDHCI_SPEC_100 0

◆ SDHCI_SPEC_200

#define SDHCI_SPEC_200 1

◆ SDHCI_SPEC_300

#define SDHCI_SPEC_300 2

◆ SDHCI_SPEC_400

#define SDHCI_SPEC_400 3

◆ SDHCI_SPEC_410

#define SDHCI_SPEC_410 4

◆ SDHCI_SPEC_420

#define SDHCI_SPEC_420 5

◆ SDHCI_MAX_CLOCK_DIV_SPEC_200

#define SDHCI_MAX_CLOCK_DIV_SPEC_200 256

SDHCI Clock Dividers

◆ SDHCI_MAX_CLOCK_DIV_SPEC_300

#define SDHCI_MAX_CLOCK_DIV_SPEC_300 2046

◆ SDHCI_QUIRK_CLOCK_BEFORE_RESET

#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)

Controller doesn't honor resets unless we touch the clock register.

SDHCI Quirks/Bugs From Linux /include/linux/mmc/sdhci.h

◆ SDHCI_QUIRK_FORCE_DMA

#define SDHCI_QUIRK_FORCE_DMA (1 << 1)

Controller has bad caps bits, but really supports DMA.

◆ SDHCI_QUIRK_NO_CARD_NO_RESET

#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2)

Controller doesn't like to be reset when there is no card inserted.

◆ SDHCI_QUIRK_SINGLE_POWER_WRITE

#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3)

Controller doesn't like clearing the power reg before a change.

◆ SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS

#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1 << 4)

Controller has flaky internal state so reset it on each ios change.

◆ SDHCI_QUIRK_BROKEN_DMA

#define SDHCI_QUIRK_BROKEN_DMA (1 << 5)

Controller has an unusable DMA engine.

◆ SDHCI_QUIRK_BROKEN_ADMA

#define SDHCI_QUIRK_BROKEN_ADMA (1 << 6)

Controller has an unusable ADMA engine.

◆ SDHCI_QUIRK_32BIT_DMA_ADDR

#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7)

Controller can only DMA from 32-bit aligned addresses.

◆ SDHCI_QUIRK_32BIT_DMA_SIZE

#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8)

Controller can only DMA chunk sizes that are a multiple of 32 bits.

◆ SDHCI_QUIRK_32BIT_ADMA_SIZE

#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9)

Controller can only ADMA chunks that are a multiple of 32 bits.

◆ SDHCI_QUIRK_RESET_AFTER_REQUEST

#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10)

Controller needs to be reset after each request to stay stable.

◆ SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER

#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11)

Controller needs voltage and power writes to happen separately.

◆ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL

#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12)

Controller provides an incorrect timeout value for transfers.

◆ SDHCI_QUIRK_BROKEN_SMALL_PIO

#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13)

Controller has an issue with buffer bits for small transfers.

◆ SDHCI_QUIRK_NO_BUSY_IRQ

#define SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14)

Controller does not provide transfer-complete interrupt when not busy.

◆ SDHCI_QUIRK_BROKEN_CARD_DETECTION

#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15)

Controller has unreliable card detection.

◆ SDHCI_QUIRK_INVERTED_WRITE_PROTECT

#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16)

Controller reports inverted write-protect state.

◆ SDHCI_QUIRK_PIO_NEEDS_DELAY

#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18)

Controller does not like fast PIO transfers.

◆ SDHCI_QUIRK_FORCE_BLK_SZ_2048

#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20)

Controller has to be forced to use block size of 2048 bytes.

◆ SDHCI_QUIRK_NO_MULTIBLOCK

#define SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21)

Controller cannot do multi-block transfers.

◆ SDHCI_QUIRK_FORCE_1_BIT_DATA

#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22)

Controller can only handle 1-bit data transfers.

◆ SDHCI_QUIRK_DELAY_AFTER_POWER

#define SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23)

Controller needs 10ms delay between applying power and clock.

◆ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK

#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)

Controller uses SDCLK instead of TMCLK for data timeouts.

◆ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN

#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25)

Controller reports wrong base clock capability.

◆ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC

#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26)

Controller cannot support End Attribute in NOP ADMA descriptor.

◆ SDHCI_QUIRK_MISSING_CAPS

#define SDHCI_QUIRK_MISSING_CAPS (1 << 27)

Controller is missing device caps. Use caps provided by host.

◆ SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28)

Controller uses Auto CMD12 command to stop the transfer.

◆ SDHCI_QUIRK_NO_HISPD_BIT

#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 29)

Controller doesn't have HISPD bit field in HI-SPEED SD card.

◆ SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC

#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30)

Controller treats ADMA descriptors with length 0000h incorrectly.

◆ SDHCI_QUIRK_UNSTABLE_RO_DETECT

#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31)

The read-only detection via SDHCI_PRESENT_STATE register is unstable.

◆ SDHCI_QUIRK2_HOST_OFF_CARD_ON

#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0)

SDHCI More Quirks/Bugs From Linux /include/linux/mmc/sdhci.h

◆ SDHCI_QUIRK2_HOST_NO_CMD23

#define SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1)

◆ SDHCI_QUIRK2_NO_1_8_V

#define SDHCI_QUIRK2_NO_1_8_V (1 << 2)

The system physically doesn't support 1.8v, even if the host does.

◆ SDHCI_QUIRK2_PRESET_VALUE_BROKEN

#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3)

◆ SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON

#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4)

◆ SDHCI_QUIRK2_BROKEN_HOST_CONTROL

#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5)

Controller has a non-standard host control register.

◆ SDHCI_QUIRK2_BROKEN_HS200

#define SDHCI_QUIRK2_BROKEN_HS200 (1 << 6)

Controller does not support HS200.

◆ SDHCI_QUIRK2_BROKEN_DDR50

#define SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7)

Controller does not support DDR50.

◆ SDHCI_QUIRK2_STOP_WITH_TC

#define SDHCI_QUIRK2_STOP_WITH_TC (1 << 8)

Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY.

◆ SDHCI_QUIRK2_BROKEN_64_BIT_DMA

#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9)

Controller does not support 64-bit DMA.

◆ SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD

#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10)

Need clear transfer mode register before send cmd.

◆ SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400

#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11)

Capability register bit-63 indicates HS400 support.

◆ SDHCI_QUIRK2_TUNING_WORK_AROUND

#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12)

Forced tuned clock.

◆ SDHCI_QUIRK2_SUPPORT_SINGLE

#define SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13)

Disable the block count for single block transactions.

◆ SDHCI_QUIRK2_ACMD23_BROKEN

#define SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14)

Controller broken with using ACMD23.

◆ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15)

Broken Clock divider zero in controller.

◆ SDHCI_QUIRK2_RSP_136_HAS_CRC

#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16)

Controller has CRC in 136 bit Command Response.

◆ SDHCI_QUIRK2_DISABLE_HW_TIMEOUT

#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17)

Disable HW timeout if the requested timeout is more than the maximum obtainable timeout.

◆ SDHCI_QUIRK2_USE_32BIT_BLK_CNT

#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18)

32-bit block count may not support eMMC where upper bits of CMD23 are used for other purposes

◆ SDHCI_DEFAULT_BOUNDARY_SIZE

#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)

Default to 512K boundary.

Support 16-bit block count by default otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit block count SDHCI Host SDMA buffer boundary (Valid values from 4K to 512K in powers of 2)

◆ SDHCI_DEFAULT_BOUNDARY_ARG

#define SDHCI_DEFAULT_BOUNDARY_ARG 7

(ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)

◆ SDHCI_ADMA2_32_DESC_SIZE

#define SDHCI_ADMA2_32_DESC_SIZE 8

ADMA2 32-bit DMA descriptor size

◆ SDHCI_ADMA2_ALIGN

#define SDHCI_ADMA2_ALIGN 4

ADMA2 data alignment

◆ SDHCI_ADMA2_MASK

#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)

◆ SDHCI_ADMA2_DESC_ALIGN

#define SDHCI_ADMA2_DESC_ALIGN 8

ADMA2 descriptor alignment

◆ SDHCI_ADMA2_64_DESC_SIZE

#define SDHCI_ADMA2_64_DESC_SIZE 12

ADMA2 64-bit DMA descriptor size

◆ SDHCI_ADMA2_64_DESC_V4_SIZE

#define SDHCI_ADMA2_64_DESC_V4_SIZE 16

Use 128-bit descriptor, if Host Version 4 Enable is set in the Host Control 2 register.

◆ SDHCI_ADMA2_DESC_ATTR_VALID

#define SDHCI_ADMA2_DESC_ATTR_VALID 0x01

ADMA2 descriptor attributes

◆ SDHCI_ADMA2_DESC_ATTR_END

#define SDHCI_ADMA2_DESC_ATTR_END 0x02

◆ SDHCI_ADMA2_DESC_ATTR_INT

#define SDHCI_ADMA2_DESC_ATTR_INT 0x04

◆ SDHCI_ADMA2_DESC_ATTR_NOP

#define SDHCI_ADMA2_DESC_ATTR_NOP 0x00

◆ SDHCI_ADMA2_DESC_ATTR_TRAN

#define SDHCI_ADMA2_DESC_ATTR_TRAN 0x20

◆ SDHCI_ADMA2_DESC_ATTR_LINK

#define SDHCI_ADMA2_DESC_ATTR_LINK 0x30

◆ SDHCI_ADMA2_DESC_TRAN_VALID

#define SDHCI_ADMA2_DESC_TRAN_VALID SDHCI_ADMA2_DESC_ATTR_TRAN | SDHCI_ADMA2_DESC_ATTR_VALID

0x21

◆ SDHCI_ADMA2_DESC_NOP_END_VALID

#define SDHCI_ADMA2_DESC_NOP_END_VALID SDHCI_ADMA2_DESC_ATTR_NOP | SDHCI_ADMA2_DESC_ATTR_END | SDHCI_ADMA2_DESC_ATTR_VALID

0x3

◆ SDHCI_ADMA2_DESC_END

#define SDHCI_ADMA2_DESC_END SDHCI_ADMA2_DESC_ATTR_END

0x2

◆ SDHCI_MAX_SEGS

#define SDHCI_MAX_SEGS 128

SDHCI maximum segments (assuming a 512KB maximum request size and a minimum 4KB page size)

◆ SDHCI_TIMEOUT_VALUE

#define SDHCI_TIMEOUT_VALUE 0x0E

SDHCI Timeout Value

Typedef Documentation

◆ MMC_DATA

typedef struct _MMC_DATA MMC_DATA

MMC specific types MMC Command

◆ MMC_COMMAND

typedef struct _MMC_COMMAND MMC_COMMAND

◆ MMC_CARD_IDENTIFICATION_DATA

typedef struct _MMC_CARD_IDENTIFICATION_DATA MMC_CARD_IDENTIFICATION_DATA

MMC Card Identification Data (CID)

◆ MMC_CARD_SPECIFIC_SD_ERASE_DATA

typedef struct _MMC_CARD_SPECIFIC_SD_ERASE_DATA MMC_CARD_SPECIFIC_SD_ERASE_DATA

MMC Card Specific Data (CSD)

◆ MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA

typedef struct _MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA

◆ MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA

typedef struct _MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA

◆ MMC_CARD_SPECIFIC_ERASE_DATA

typedef union _MMC_CARD_SPECIFIC_ERASE_DATA MMC_CARD_SPECIFIC_ERASE_DATA

◆ MMC_CARD_SPECIFIC_DATA

typedef struct _MMC_CARD_SPECIFIC_DATA MMC_CARD_SPECIFIC_DATA

◆ MMC_EXTENDED_CARD_SPECIFIC_DATA

typedef struct _MMC_EXTENDED_CARD_SPECIFIC_DATA MMC_EXTENDED_CARD_SPECIFIC_DATA

◆ SD_STATUS_DATA

typedef struct _SD_STATUS_DATA SD_STATUS_DATA

SD Status Data (SSR)

◆ SD_SWITCH_DATA

typedef struct _SD_SWITCH_DATA SD_SWITCH_DATA

SD Switch Data

◆ SD_CONFIGURATION_DATA

typedef struct _SD_CONFIGURATION_DATA SD_CONFIGURATION_DATA

SD Configuration Data (SCR)

◆ MMC_DEVICE

typedef struct _MMC_DEVICE MMC_DEVICE

MMC Device

◆ SDIO_CCCR

typedef struct _SDIO_CCCR SDIO_CCCR

Forward declared to satisfy MMCDevice.

◆ SDIO_CIS

typedef struct _SDIO_CIS SDIO_CIS

Forward declared to satisfy MMCDevice.

◆ SDIO_TUPLE

typedef struct _SDIO_TUPLE SDIO_TUPLE

Forward declared to satisfy MMCDevice.

◆ SDIO_FUNCTION

typedef struct _SDIO_FUNCTION SDIO_FUNCTION

Forward declared to satisfy MMCDevice.

◆ mmc_enumerate_cb

typedef uint32_t STDCALL(* mmc_enumerate_cb) (MMC_DEVICE *mmc, void *data)

MMC Enumeration Callback

◆ mmc_notification_cb

typedef uint32_t STDCALL(* mmc_notification_cb) (DEVICE *device, void *data, uint32_t notification)

MMC Notification Callback

◆ mmc_device_initialize_proc

typedef uint32_t STDCALL(* mmc_device_initialize_proc) (MMC_DEVICE *mmc)

MMC Device Methods

◆ mmc_device_deinitialize_proc

typedef uint32_t STDCALL(* mmc_device_deinitialize_proc) (MMC_DEVICE *mmc)

◆ mmc_device_get_card_detect_proc

typedef uint32_t STDCALL(* mmc_device_get_card_detect_proc) (MMC_DEVICE *mmc)

◆ mmc_device_get_write_protect_proc

typedef uint32_t STDCALL(* mmc_device_get_write_protect_proc) (MMC_DEVICE *mmc)

◆ mmc_device_send_command_proc

typedef uint32_t STDCALL(* mmc_device_send_command_proc) (MMC_DEVICE *mmc, MMC_COMMAND *command)

◆ mmc_device_set_ios_proc

typedef uint32_t STDCALL(* mmc_device_set_ios_proc) (MMC_DEVICE *mmc)

◆ SDIO_DRIVER

typedef struct _SDIO_DRIVER SDIO_DRIVER

Forward declared to satisfy SDIOFunction.

SDIO Function

◆ sdio_interrupt_handler

typedef void STDCALL(* sdio_interrupt_handler) (SDIO_FUNCTION *func)

SDIO Function Interrupt Handler

◆ sdio_function_enumerate_cb

typedef uint32_t STDCALL(* sdio_function_enumerate_cb) (SDIO_FUNCTION *func, void *data)

SDIO Function Enumeration Callback

◆ sdio_driver_enumerate_cb

typedef uint32_t STDCALL(* sdio_driver_enumerate_cb) (SDIO_DRIVER *driver, void *data)

SDIO Driver SDIO Driver Enumeration Callback

◆ sdio_driver_bind_proc

typedef uint32_t STDCALL(* sdio_driver_bind_proc) (MMC_DEVICE *mmc, SDIO_FUNCTION *func)

SDIO Driver Methods

◆ sdio_driver_unbind_proc

typedef uint32_t STDCALL(* sdio_driver_unbind_proc) (MMC_DEVICE *mmc, SDIO_FUNCTION *func)

◆ SDHCI_ADMA2_DESCRIPTOR32

typedef struct _SDHCI_ADMA2_DESCRIPTOR32 SDHCI_ADMA2_DESCRIPTOR32

SDHCI specific types ADMA2 32-bit descriptor (See ADMA2 Descriptor Format - SD Host Controller Simplified Specification Version 4.20)

◆ SDHCI_ADMA2_DESCRIPTOR64

typedef struct _SDHCI_ADMA2_DESCRIPTOR64 SDHCI_ADMA2_DESCRIPTOR64

ADMA2 64-bit descriptors (See ADMA2 Descriptor Format - SD Host Controller Simplified Specification Version 4.20) Note 12-byte descriptor can't always be 8-byte aligned

◆ SDHCI_ADMA2_DESCRIPTOR64_V4

typedef struct _SDHCI_ADMA2_DESCRIPTOR64_V4 SDHCI_ADMA2_DESCRIPTOR64_V4

◆ SDHCI_HOST

typedef struct _SDHCI_HOST SDHCI_HOST

SDHCI Host

◆ sdhci_enumerate_cb

typedef uint32_t STDCALL(* sdhci_enumerate_cb) (SDHCI_HOST *sdhci, void *data)

SDHCI Enumeration Callback

◆ sdhci_notification_cb

typedef uint32_t STDCALL(* sdhci_notification_cb) (DEVICE *device, void *data, uint32_t notification)

SDHCI Notification Callback

◆ sdhci_host_start_proc

typedef uint32_t STDCALL(* sdhci_host_start_proc) (SDHCI_HOST *sdhci)

SDHCI Host Methods

◆ sdhci_host_stop_proc

typedef uint32_t STDCALL(* sdhci_host_stop_proc) (SDHCI_HOST *sdhci)

◆ sdhci_host_lock_proc

typedef uint32_t STDCALL(* sdhci_host_lock_proc) (SDHCI_HOST *sdhci)

◆ sdhci_host_unlock_proc

typedef uint32_t STDCALL(* sdhci_host_unlock_proc) (SDHCI_HOST *sdhci)

◆ sdhci_host_signal_proc

typedef uint32_t STDCALL(* sdhci_host_signal_proc) (SDHCI_HOST *sdhci, SEMAPHORE_HANDLE semaphore)

◆ sdhci_host_read_byte_proc

typedef uint8_t STDCALL(* sdhci_host_read_byte_proc) (SDHCI_HOST *sdhci, uint32_t reg)

◆ sdhci_host_read_word_proc

typedef uint16_t STDCALL(* sdhci_host_read_word_proc) (SDHCI_HOST *sdhci, uint32_t reg)

◆ sdhci_host_read_long_proc

typedef uint32_t STDCALL(* sdhci_host_read_long_proc) (SDHCI_HOST *sdhci, uint32_t reg)

◆ sdhci_host_write_byte_proc

typedef void STDCALL(* sdhci_host_write_byte_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint8_t value)

◆ sdhci_host_write_word_proc

typedef void STDCALL(* sdhci_host_write_word_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint16_t value)

◆ sdhci_host_write_long_proc

typedef void STDCALL(* sdhci_host_write_long_proc) (SDHCI_HOST *sdhci, uint32_t reg, uint32_t value)

◆ sdhci_host_reset_proc

typedef uint32_t STDCALL(* sdhci_host_reset_proc) (SDHCI_HOST *sdhci, uint8_t mask)

◆ sdhci_host_hardware_reset_proc

typedef uint32_t STDCALL(* sdhci_host_hardware_reset_proc) (SDHCI_HOST *sdhci)

◆ sdhci_host_set_power_proc

typedef uint32_t STDCALL(* sdhci_host_set_power_proc) (SDHCI_HOST *sdhci, uint16_t power)

◆ sdhci_host_set_clock_proc

typedef uint32_t STDCALL(* sdhci_host_set_clock_proc) (SDHCI_HOST *sdhci, uint32_t clock)

◆ sdhci_host_set_timing_proc

typedef uint32_t STDCALL(* sdhci_host_set_timing_proc) (SDHCI_HOST *sdhci, uint32_t timing)

◆ sdhci_host_set_buswidth_proc

typedef uint32_t STDCALL(* sdhci_host_set_buswidth_proc) (SDHCI_HOST *sdhci, uint32_t buswidth)

◆ sdhci_host_set_clock_divider_proc

typedef uint32_t STDCALL(* sdhci_host_set_clock_divider_proc) (SDHCI_HOST *sdhci, int index, uint32_t divider)

◆ sdhci_host_set_control_register_proc

typedef uint32_t STDCALL(* sdhci_host_set_control_register_proc) (SDHCI_HOST *sdhci)

◆ sdhci_host_prepare_dma_proc

typedef uint32_t STDCALL(* sdhci_host_prepare_dma_proc) (SDHCI_HOST *sdhci, MMC_COMMAND *command)

◆ sdhci_host_start_dma_proc

typedef uint32_t STDCALL(* sdhci_host_start_dma_proc) (SDHCI_HOST *sdhci, MMC_COMMAND *command)

◆ sdhci_host_stop_dma_proc

typedef uint32_t STDCALL(* sdhci_host_stop_dma_proc) (SDHCI_HOST *sdhci, MMC_COMMAND *command)

◆ sdhci_host_setup_card_irq_proc

typedef uint32_t STDCALL(* sdhci_host_setup_card_irq_proc) (SDHCI_HOST *sdhci, LONGBOOL enable)

◆ sdhci_host_complete_card_irq_proc

typedef uint32_t STDCALL(* sdhci_host_complete_card_irq_proc) (SDHCI_HOST *sdhci)

Function Documentation

◆ mmc_start()

uint32_t STDCALL mmc_start ( void )

Initialization Functions

◆ mmc_stop()

uint32_t STDCALL mmc_stop ( void )

◆ mmc_async_start()

void STDCALL mmc_async_start ( SDHCI_HOST * sdhci )

◆ mmc_device_read_blocks()

uint32_t STDCALL mmc_device_read_blocks	(	MMC_DEVICE *	mmc,
		int64_t	start,
		int64_t	count,
		void *	buffer )

MMC Functions

◆ mmc_device_write_blocks()

uint32_t STDCALL mmc_device_write_blocks	(	MMC_DEVICE *	mmc,
		int64_t	start,
		int64_t	count,
		void *	buffer )

◆ mmc_device_erase_blocks()

uint32_t STDCALL mmc_device_erase_blocks	(	MMC_DEVICE *	mmc,
		int64_t	start,
		int64_t	count )

◆ mmc_device_go_idle()

uint32_t STDCALL mmc_device_go_idle ( MMC_DEVICE * mmc )

◆ mmc_device_set_clock()

uint32_t STDCALL mmc_device_set_clock	(	MMC_DEVICE *	mmc,
		uint32_t	clock )

◆ mmc_device_set_timing()

uint32_t STDCALL mmc_device_set_timing	(	MMC_DEVICE *	mmc,
		uint32_t	timing )

◆ mmc_device_set_bus_width()

uint32_t STDCALL mmc_device_set_bus_width	(	MMC_DEVICE *	mmc,
		uint32_t	width )

◆ mmc_device_set_block_length()

uint32_t STDCALL mmc_device_set_block_length	(	MMC_DEVICE *	mmc,
		uint32_t	length )

◆ mmc_device_set_block_count()

uint32_t STDCALL mmc_device_set_block_count	(	MMC_DEVICE *	mmc,
		uint32_t	count,
		BOOL	relative )

◆ mmc_device_set_driver_stage()

uint32_t STDCALL mmc_device_set_driver_stage	(	MMC_DEVICE *	mmc,
		uint32_t	driverstage )

◆ mmc_device_stop_transmission()

uint32_t STDCALL mmc_device_stop_transmission ( MMC_DEVICE * mmc )

◆ mmc_device_select_card()

uint32_t STDCALL mmc_device_select_card ( MMC_DEVICE * mmc )

◆ mmc_device_deselect_card()

uint32_t STDCALL mmc_device_deselect_card ( MMC_DEVICE * mmc )

◆ mmc_device_switch()

uint32_t STDCALL mmc_device_switch	(	MMC_DEVICE *	mmc,
		uint8_t	setting,
		uint8_t	index,
		uint8_t	value,
		uint32_t	timeout )

Modifies an Extended CSD register for the specificed MMC device.

Parameters

MMC	The MMC Device to modify
Setting	The Extended CSD command set (eg EXT_CSD_CMD_SET_NORMAL)
Index	The index of the Extended CSD register to be set
Value	The value to be set in the Extended CSD register
Timeout	Command timeout in milliseconds

◆ mmc_device_switch_ex()

uint32_t STDCALL mmc_device_switch_ex	(	MMC_DEVICE *	mmc,
		uint8_t	setting,
		uint8_t	index,
		uint8_t	value,
		uint32_t	timeout,
		uint32_t	timing,
		BOOL	sendstatus,
		BOOL	retrycrcerror )

Modifies an Extended CSD register for the specificed MMC device.

Parameters

MMC	The MMC Device to modify
Setting	The Extended CSD command set (eg EXT_CSD_CMD_SET_NORMAL)
Index	The index of the Extended CSD register to be set
Value	The value to be set in the Extended CSD register
Timeout	Command timeout in milliseconds
Timing	New timing to enable after change (eg MMC_TIMING_MMC_HS)
SendStatus	Use the MMC_CMD_SEND_STATUS command to poll for busy
RetryCRCError	Retry if CRC error occurs when polling for busy

◆ mmc_device_poll_for_busy()

uint32_t STDCALL mmc_device_poll_for_busy	(	MMC_DEVICE *	mmc,
		uint32_t	timeout,
		uint32_t	command )

Poll the specified MMC device for command completion using busy status.

◆ mmc_device_poll_for_busy_ex()

uint32_t STDCALL mmc_device_poll_for_busy_ex	(	MMC_DEVICE *	mmc,
		uint32_t	timeout,
		uint32_t	command,
		BOOL	sendstatus,
		BOOL	retrycrcerror )

Poll the specified MMC device for command completion using busy status.

◆ mmc_device_send_card_status()

uint32_t STDCALL mmc_device_send_card_status ( MMC_DEVICE * mmc )

◆ mmc_device_send_operation_condition()

uint32_t STDCALL mmc_device_send_operation_condition	(	MMC_DEVICE *	mmc,
		BOOL	probe )

◆ mmc_device_send_card_specific()

uint32_t STDCALL mmc_device_send_card_specific ( MMC_DEVICE * mmc )

◆ mmc_device_decode_card_specific()

uint32_t STDCALL mmc_device_decode_card_specific ( MMC_DEVICE * mmc )

Given a 128-bit response, decode to our card CSD structure.

◆ mmc_device_send_card_identification()

uint32_t STDCALL mmc_device_send_card_identification ( MMC_DEVICE * mmc )

◆ mmc_device_send_all_card_identification()

uint32_t STDCALL mmc_device_send_all_card_identification ( MMC_DEVICE * mmc )

◆ mmc_device_decode_card_identification()

uint32_t STDCALL mmc_device_decode_card_identification ( MMC_DEVICE * mmc )

Given a 128-bit response, decode to our card CID structure.

◆ mmc_device_get_extended_card_specific()

uint32_t STDCALL mmc_device_get_extended_card_specific ( MMC_DEVICE * mmc )

◆ mmc_device_send_extended_card_specific()

uint32_t STDCALL mmc_device_send_extended_card_specific ( MMC_DEVICE * mmc )

◆ mmc_device_decode_extended_card_specific()

uint32_t STDCALL mmc_device_decode_extended_card_specific ( MMC_DEVICE * mmc )

◆ mmc_device_set_relative_address()

uint32_t STDCALL mmc_device_set_relative_address ( MMC_DEVICE * mmc )

◆ mmc_device_spi_set_crc()

uint32_t STDCALL mmc_device_spi_set_crc	(	MMC_DEVICE *	mmc,
		BOOL	enable )

◆ mmc_device_spi_read_operation_condition()

uint32_t STDCALL mmc_device_spi_read_operation_condition	(	MMC_DEVICE *	mmc,
		BOOL	highcapacity )

◆ mmc_device_insert()

uint32_t STDCALL mmc_device_insert ( MMC_DEVICE * mmc )

◆ mmc_device_remove()

uint32_t STDCALL mmc_device_remove ( MMC_DEVICE * mmc )

◆ mmc_device_initialize()

uint32_t STDCALL mmc_device_initialize ( MMC_DEVICE * mmc )

◆ mmc_device_deinitialize()

uint32_t STDCALL mmc_device_deinitialize ( MMC_DEVICE * mmc )

◆ mmc_device_get_card_detect()

uint32_t STDCALL mmc_device_get_card_detect ( MMC_DEVICE * mmc )

◆ mmc_device_get_write_protect()

uint32_t STDCALL mmc_device_get_write_protect ( MMC_DEVICE * mmc )

◆ mmc_device_send_command()

uint32_t STDCALL mmc_device_send_command	(	MMC_DEVICE *	mmc,
		MMC_COMMAND *	command )

◆ mmc_device_set_ios()

uint32_t STDCALL mmc_device_set_ios ( MMC_DEVICE * mmc )

◆ mmc_device_create()

MMC_DEVICE *STDCALL mmc_device_create ( void )

Create a new MMC entry.

Returns: Pointer to new MMC entry or nil if MMC could not be created

◆ mmc_device_create_ex()

MMC_DEVICE *STDCALL mmc_device_create_ex ( uint32_t size )

Create a new MMC entry.

Parameters

Size	Size in bytes to allocate for new MMC (Including the MMC entry)

Returns: Pointer to new MMC entry or nil if MMC could not be created

◆ mmc_device_destroy()

uint32_t STDCALL mmc_device_destroy ( MMC_DEVICE * mmc )

Destroy an existing MMC entry.

◆ mmc_device_register()

uint32_t STDCALL mmc_device_register ( MMC_DEVICE * mmc )

Register a new MMC in the MMC table.

◆ mmc_device_deregister()

uint32_t STDCALL mmc_device_deregister ( MMC_DEVICE * mmc )

Deregister a MMC from the MMC table.

◆ mmc_device_find()

MMC_DEVICE *STDCALL mmc_device_find ( uint32_t mmcid )

◆ mmc_device_find_by_device()

MMC_DEVICE *STDCALL mmc_device_find_by_device ( DEVICE * device )

Find an MMC/SD device by the matching DeviceData property.

Parameters

Device The device entry to match with the DeviceData value

Returns: The MMC/SD device matched or nil if none found

◆ mmc_device_find_by_name()

MMC_DEVICE *STDCALL mmc_device_find_by_name ( const char * name )

◆ mmc_device_find_by_description()

MMC_DEVICE *STDCALL mmc_device_find_by_description ( const char * description )

◆ mmc_device_enumerate()

uint32_t STDCALL mmc_device_enumerate	(	mmc_enumerate_cb	callback,
		void *	data )

◆ mmc_device_notification()

uint32_t STDCALL mmc_device_notification	(	MMC_DEVICE *	mmc,
		mmc_notification_cb	callback,
		void *	data,
		uint32_t	notification,
		uint32_t	flags )

◆ sd_device_switch()

uint32_t STDCALL sd_device_switch	(	MMC_DEVICE *	mmc,
		int	mode,
		int	group,
		uint8_t	value,
		void *	buffer )

SD Functions

◆ sd_device_switch_highspeed()

uint32_t STDCALL sd_device_switch_highspeed ( MMC_DEVICE * mmc )

◆ sd_device_set_bus_width()

uint32_t STDCALL sd_device_set_bus_width	(	MMC_DEVICE *	mmc,
		uint32_t	width )

◆ sd_device_send_interface_condition()

uint32_t STDCALL sd_device_send_interface_condition ( MMC_DEVICE * mmc )

◆ sd_device_send_operation_condition()

uint32_t STDCALL sd_device_send_operation_condition	(	MMC_DEVICE *	mmc,
		BOOL	probe )

◆ sd_device_get_card_specific()

uint32_t STDCALL sd_device_get_card_specific ( MMC_DEVICE * mmc )

◆ sd_device_decode_card_specific()

uint32_t STDCALL sd_device_decode_card_specific ( MMC_DEVICE * mmc )

Given a 128-bit response, decode to our card CSD structure.

◆ sd_device_get_card_identification()

uint32_t STDCALL sd_device_get_card_identification ( MMC_DEVICE * mmc )

◆ sd_device_decode_card_identification()

uint32_t STDCALL sd_device_decode_card_identification ( MMC_DEVICE * mmc )

Given a 128-bit response, decode to our card CID structure.

◆ sd_device_send_sd_status()

uint32_t STDCALL sd_device_send_sd_status ( MMC_DEVICE * mmc )

◆ sd_device_decode_sd_status()

uint32_t STDCALL sd_device_decode_sd_status ( MMC_DEVICE * mmc )

◆ sd_device_send_sd_switch()

uint32_t STDCALL sd_device_send_sd_switch ( MMC_DEVICE * mmc )

◆ sd_device_decode_sd_switch()

uint32_t STDCALL sd_device_decode_sd_switch ( MMC_DEVICE * mmc )

◆ sd_device_send_sd_configuration()

uint32_t STDCALL sd_device_send_sd_configuration ( MMC_DEVICE * mmc )

◆ sd_device_decode_sd_configuration()

uint32_t STDCALL sd_device_decode_sd_configuration ( MMC_DEVICE * mmc )

Given a 64-bit response, decode to our card SCR structure.

◆ sd_device_send_relative_address()

uint32_t STDCALL sd_device_send_relative_address ( MMC_DEVICE * mmc )

◆ sd_device_send_application_command()

uint32_t STDCALL sd_device_send_application_command	(	MMC_DEVICE *	mmc,
		MMC_COMMAND *	command )

◆ sdio_device_reset()

uint32_t STDCALL sdio_device_reset ( MMC_DEVICE * mmc )

Device Methods.

SDIO Functions

◆ sdio_device_enable_wide_bus()

uint32_t STDCALL sdio_device_enable_wide_bus ( MMC_DEVICE * mmc )

◆ sdio_device_disable_wide_bus()

uint32_t STDCALL sdio_device_disable_wide_bus ( MMC_DEVICE * mmc )

◆ sdio_device_enable_highspeed()

uint32_t STDCALL sdio_device_enable_highspeed ( MMC_DEVICE * mmc )

◆ sdio_device_switch_highspeed()

uint32_t STDCALL sdio_device_switch_highspeed	(	MMC_DEVICE *	mmc,
		BOOL	enable )

◆ sdio_device_send_operation_condition()

uint32_t STDCALL sdio_device_send_operation_condition	(	MMC_DEVICE *	mmc,
		BOOL	probe )

◆ sdio_device_read_write_direct()

uint32_t STDCALL sdio_device_read_write_direct	(	MMC_DEVICE *	mmc,
		BOOL	write,
		uint32_t	operation,
		uint32_t	address,
		uint8_t	input,
		uint8_t *	output )

◆ sdio_device_read_write_extended()

uint32_t STDCALL sdio_device_read_write_extended	(	MMC_DEVICE *	mmc,
		BOOL	write,
		uint32_t	operation,
		uint32_t	address,
		BOOL	increment,
		void *	buffer,
		uint32_t	blockcount,
		uint32_t	blocksize )

◆ sdio_device_read_byte()

uint32_t STDCALL sdio_device_read_byte	(	MMC_DEVICE *	mmc,
		uint32_t	address,
		uint8_t *	output )

Wrapper for reading a single byte from Function 0.

◆ sdio_device_write_byte()

uint32_t STDCALL sdio_device_write_byte	(	MMC_DEVICE *	mmc,
		uint32_t	address,
		uint8_t	input )

Wrapper for writing a single byte to Function 0.

◆ sdio_device_read_cccr()

uint32_t STDCALL sdio_device_read_cccr ( MMC_DEVICE * mmc )

◆ sdio_device_read_fbr()

uint32_t STDCALL sdio_device_read_fbr ( SDIO_FUNCTION * func )

◆ sdio_device_read_cis()

uint32_t STDCALL sdio_device_read_cis	(	MMC_DEVICE *	mmc,
		SDIO_FUNCTION *	func )

◆ sdio_device_read_common_cis()

uint32_t STDCALL sdio_device_read_common_cis ( MMC_DEVICE * mmc )

◆ sdio_device_read_function_cis()

uint32_t STDCALL sdio_device_read_function_cis ( SDIO_FUNCTION * func )

◆ sdio_device_process_interrupts()

uint32_t STDCALL sdio_device_process_interrupts ( MMC_DEVICE * mmc )

◆ sdio_device_register_interrupt()

uint32_t STDCALL sdio_device_register_interrupt	(	MMC_DEVICE *	mmc,
		SDIO_FUNCTION *	func,
		sdio_interrupt_handler	handler )

◆ sdio_device_deregister_interrupt()

uint32_t STDCALL sdio_device_deregister_interrupt	(	MMC_DEVICE *	mmc,
		SDIO_FUNCTION *	func )

◆ sdio_device_bind_functions()

uint32_t STDCALL sdio_device_bind_functions ( MMC_DEVICE * mmc )

Attempt to bind SDIO functions on an MMC device to one of the registered drivers.

Parameters

MMC	The MMC device to attempt to bind a driver to

Returns: MMC_STATUS_SUCCESS if completed or another error code on failure

◆ sdio_device_unbind_functions()

uint32_t STDCALL sdio_device_unbind_functions	(	MMC_DEVICE *	mmc,
		SDIO_DRIVER *	driver )

Unbind SDIO functions on an MMC device from a driver.

Parameters

MMC	The MMC device to unbind a driver from
Driver	The driver to unbind the MMC device from (nil to unbind from current driver)

Returns: MMC_STATUS_SUCCESS if completed or another error code on failure

◆ sdio_function_allocate()

SDIO_FUNCTION *STDCALL sdio_function_allocate	(	MMC_DEVICE *	mmc,
		uint32_t	number )

Function Methods.

◆ sdio_function_release()

uint32_t STDCALL sdio_function_release ( SDIO_FUNCTION * func )

◆ sdio_function_find()

SDIO_FUNCTION *STDCALL sdio_function_find	(	MMC_DEVICE *	mmc,
		uint32_t	number )

◆ sdio_function_find_by_id()

SDIO_FUNCTION *STDCALL sdio_function_find_by_id	(	MMC_DEVICE *	mmc,
		uint16_t	vendorid,
		uint16_t	deviceid )

◆ sdio_function_enumerate()

uint32_t STDCALL sdio_function_enumerate	(	MMC_DEVICE *	mmc,
		sdio_function_enumerate_cb	callback,
		void *	data )

◆ sdio_function_bind()

uint32_t STDCALL sdio_function_bind	(	SDIO_FUNCTION *	func,
		SDIO_DRIVER *	driver )

◆ sdio_function_unbind()

uint32_t STDCALL sdio_function_unbind	(	SDIO_FUNCTION *	func,
		SDIO_DRIVER *	driver )

◆ sdio_function_enable()

uint32_t STDCALL sdio_function_enable ( SDIO_FUNCTION * func )

◆ sdio_function_disable()

uint32_t STDCALL sdio_function_disable ( SDIO_FUNCTION * func )

◆ sdio_function_set_block_size()

uint32_t STDCALL sdio_function_set_block_size	(	SDIO_FUNCTION *	func,
		uint32_t	blocksize )

◆ sdio_function_read_write_extended()

uint32_t STDCALL sdio_function_read_write_extended	(	SDIO_FUNCTION *	func,
		BOOL	write,
		uint32_t	address,
		BOOL	increment,
		void *	buffer,
		uint32_t	size )

Perform an SDIO read or write to the specified function at the specified address Handles splitting any size read or write into multiple IO_RW_EXTENDED requests, accounting for maximum block sizes.

◆ sdio_function_read()

uint32_t STDCALL sdio_function_read	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		void *	buffer,
		uint32_t	size )

Wrapper for reading multiple bytes from an SDIO function.

◆ sdio_function_write()

uint32_t STDCALL sdio_function_write	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		void *	buffer,
		uint32_t	size )

Wrapper for writing multiple bytes to an SDIO function.

◆ sdio_function_read_byte()

uint32_t STDCALL sdio_function_read_byte	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint8_t *	output )

Wrapper for reading a single byte from an SDIO function.

◆ sdio_function_write_byte()

uint32_t STDCALL sdio_function_write_byte	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint8_t	input )

Wrapper for writing a single byte to an SDIO function.

◆ sdio_function_write_read_byte()

uint32_t STDCALL sdio_function_write_read_byte	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint8_t	input,
		uint8_t *	output )

Wrapper for performing a read after write (RAW) operation on an SDIO function.

◆ sdio_function_read_word()

uint32_t STDCALL sdio_function_read_word	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint16_t *	output )

Wrapper for reading a single word from an SDIO function.

◆ sdio_function_write_word()

uint32_t STDCALL sdio_function_write_word	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint16_t	input )

Wrapper for writing a single word to an SDIO function.

◆ sdio_function_read_long()

uint32_t STDCALL sdio_function_read_long	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint32_t *	output )

Wrapper for reading a single longword from an SDIO function.

◆ sdio_function_write_long()

uint32_t STDCALL sdio_function_write_long	(	SDIO_FUNCTION *	func,
		uint32_t	address,
		uint32_t	input )

Wrapper for writing a single longword to an SDIO function.

◆ sdio_function_register_interrupt()

uint32_t STDCALL sdio_function_register_interrupt	(	SDIO_FUNCTION *	func,
		sdio_interrupt_handler	handler )

◆ sdio_function_deregister_interrupt()

uint32_t STDCALL sdio_function_deregister_interrupt ( SDIO_FUNCTION * func )

◆ sdio_host_dispatch_interrupt()

uint32_t STDCALL sdio_host_dispatch_interrupt	(	SDHCI_HOST *	sdhci,
		BOOL	irq,
		BOOL	fiq )

Host Methods.

◆ sdio_driver_create()

SDIO_DRIVER *STDCALL sdio_driver_create ( void )

Driver Methods.

Create a new SDIO Driver entry

Returns: Pointer to new Driver entry or nil if driver could not be created

◆ sdio_driver_create_ex()

SDIO_DRIVER *STDCALL sdio_driver_create_ex ( uint32_t size )

Create a new SDIO Driver entry.

Parameters

Size	Size in bytes to allocate for new driver (Including the driver entry)

Returns: Pointer to new Driver entry or nil if driver could not be created

◆ sdio_driver_destroy()

uint32_t STDCALL sdio_driver_destroy ( SDIO_DRIVER * driver )

Destroy an existing SDIO Driver entry.

◆ sdio_driver_register()

uint32_t STDCALL sdio_driver_register ( SDIO_DRIVER * driver )

Register a new Driver in the SDIO Driver table.

◆ sdio_driver_deregister()

uint32_t STDCALL sdio_driver_deregister ( SDIO_DRIVER * driver )

Deregister a Driver from the SDIO Driver table.

◆ sdio_driver_find()

SDIO_DRIVER *STDCALL sdio_driver_find ( uint32_t driverid )

Find a driver by Id in the SDIO Driver table.

◆ sdio_driver_find_by_name()

SDIO_DRIVER *STDCALL sdio_driver_find_by_name ( const char * name )

Find a driver by name in the Driver table.

◆ sdio_driver_enumerate()

uint32_t STDCALL sdio_driver_enumerate	(	sdio_driver_enumerate_cb	callback,
		void *	data )

◆ sdhci_host_reset()

uint32_t STDCALL sdhci_host_reset	(	SDHCI_HOST *	sdhci,
		uint8_t	mask )

Default software reset function for SDHCI host controllers.

SDHCI Functions

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

See also: Section 3.3 of SD Host Controller Simplified Specification V3.0 partA2_300.pdf

◆ sdhci_host_hardware_reset()

uint32_t STDCALL sdhci_host_hardware_reset ( SDHCI_HOST * sdhci )

Default hardware reset function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_power()

uint32_t STDCALL sdhci_host_set_power	(	SDHCI_HOST *	sdhci,
		uint16_t	power )

Default set power function for SDHCI host controllers.

Parameters

Power A shift value to indicate the first available value in the Voltages mask Caller can use FirstBitSet(SDHCI.Voltages) to obtain the value of Power If there are no values set then Power will be -1 ($FFFF) to indicate nothing or unknown

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

See also: Section 3.3 of SD Host Controller Simplified Specification V3.0 partA2_300.pdf

◆ sdhci_host_set_clock()

uint32_t STDCALL sdhci_host_set_clock	(	SDHCI_HOST *	sdhci,
		uint32_t	clock )

Default set clock function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

See also: Section 3.2 of SD Host Controller Simplified Specification V3.0 partA2_300.pdf

◆ sdhci_host_set_timing()

uint32_t STDCALL sdhci_host_set_timing	(	SDHCI_HOST *	sdhci,
		uint32_t	timing )

Default set timing function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_bus_width()

uint32_t STDCALL sdhci_host_set_bus_width	(	SDHCI_HOST *	sdhci,
		uint32_t	buswidth )

Default set bus width function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_prepare_dma()

uint32_t STDCALL sdhci_host_prepare_dma	(	SDHCI_HOST *	sdhci,
		MMC_COMMAND *	command )

Default DMA transfer prepare function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_start_dma()

uint32_t STDCALL sdhci_host_start_dma	(	SDHCI_HOST *	sdhci,
		MMC_COMMAND *	command )

Default DMA transfer start function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_stop_dma()

uint32_t STDCALL sdhci_host_stop_dma	(	SDHCI_HOST *	sdhci,
		MMC_COMMAND *	command )

Default DMA transfer stop function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_complete_dma()

void STDCALL sdhci_host_complete_dma ( DMA_REQUEST * request )

Default DMA request completion callback for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_setup_card_irq()

uint32_t STDCALL sdhci_host_setup_card_irq	(	SDHCI_HOST *	sdhci,
		LONGBOOL	enable )

Default Card IRQ setup function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_complete_card_irq()

uint32_t STDCALL sdhci_host_complete_card_irq ( SDHCI_HOST * sdhci )

Default Card IRQ completion function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_transfer_pio()

uint32_t STDCALL sdhci_host_transfer_pio ( SDHCI_HOST * sdhci )

Default PIO transfer function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_transfer_dma()

uint32_t STDCALL sdhci_host_transfer_dma ( SDHCI_HOST * sdhci )

Default DMA transfer function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_finish_command()

uint32_t STDCALL sdhci_host_finish_command ( SDHCI_HOST * sdhci )

Default finish command function for SDHCI host controllers Called by Interrupt Command handler when an SDHCI_INT_RESPONSE is received.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_finish_data()

uint32_t STDCALL sdhci_host_finish_data ( SDHCI_HOST * sdhci )

Default finish data function for SDHCI host controllers Called by Interrupt Data handler when data is received.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_command_interrupt()

uint32_t STDCALL sdhci_host_command_interrupt	(	SDHCI_HOST *	sdhci,
		uint32_t	interruptmask,
		uint32_t *	returnmask )

Default command interrupt processing function for SDHCI host controllers Called by SDHCI controller interrupt handler when a command interrupt is received.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_data_interrupt()

uint32_t STDCALL sdhci_host_data_interrupt	(	SDHCI_HOST *	sdhci,
		uint32_t	interruptmask )

Default data interrupt processing function for SDHCI host controllers Called by SDHCI controller interrupt handler when a data interrupt is received.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_start()

uint32_t STDCALL sdhci_host_start ( SDHCI_HOST * sdhci )

Default host start function for SDHCI host controllers Called automatically to start each registered SDHCI controller when required.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_stop()

uint32_t STDCALL sdhci_host_stop ( SDHCI_HOST * sdhci )

Default host stop function for SDHCI host controllers Called automatically to stop each registered SDHCI controller when required.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_lock()

uint32_t STDCALL sdhci_host_lock ( SDHCI_HOST * sdhci )

Default host lock function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_unlock()

uint32_t STDCALL sdhci_host_unlock ( SDHCI_HOST * sdhci )

Default host unlock function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_signal()

uint32_t STDCALL sdhci_host_signal	(	SDHCI_HOST *	sdhci,
		SEMAPHORE_HANDLE	semaphore )

Default host semaphore signal function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_read_byte()

uint8_t STDCALL sdhci_host_read_byte	(	SDHCI_HOST *	sdhci,
		uint32_t	reg )

Default read byte function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_read_word()

uint16_t STDCALL sdhci_host_read_word	(	SDHCI_HOST *	sdhci,
		uint32_t	reg )

Default read word function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_read_long()

uint32_t STDCALL sdhci_host_read_long	(	SDHCI_HOST *	sdhci,
		uint32_t	reg )

Default read longword function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_write_byte()

void STDCALL sdhci_host_write_byte	(	SDHCI_HOST *	sdhci,
		uint32_t	reg,
		uint8_t	value )

Default write byte function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_write_word()

void STDCALL sdhci_host_write_word	(	SDHCI_HOST *	sdhci,
		uint32_t	reg,
		uint16_t	value )

Default write word function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_write_long()

void STDCALL sdhci_host_write_long	(	SDHCI_HOST *	sdhci,
		uint32_t	reg,
		uint32_t	value )

Default write longword function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_clock_divider()

uint32_t STDCALL sdhci_host_set_clock_divider	(	SDHCI_HOST *	sdhci,
		int	index,
		uint32_t	divider )

Default set clock divider function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_control_register()

uint32_t STDCALL sdhci_host_set_control_register ( SDHCI_HOST * sdhci )

Default set control register function for SDHCI host controllers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_get_adma_address()

size_t STDCALL sdhci_host_get_adma_address ( SDHCI_HOST * sdhci )

Get the DMA address of the ADMA table for the current request.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_adma_address()

void STDCALL sdhci_host_set_adma_address	(	SDHCI_HOST *	sdhci,
		size_t	address )

Set the address of the transfer data in the Advanced DMA (ADMA) registers.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_get_sdma_address()

size_t STDCALL sdhci_host_get_sdma_address	(	SDHCI_HOST *	sdhci,
		MMC_COMMAND *	command )

Get the DMA address of the transfer data for the current request.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_set_sdma_address()

void STDCALL sdhci_host_set_sdma_address	(	SDHCI_HOST *	sdhci,
		size_t	address )

Set the address of the transfer data in the Simple DMA (SDMA) register.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_write_adma_descriptor()

void STDCALL sdhci_host_write_adma_descriptor	(	SDHCI_HOST *	sdhci,
		void *	descriptor,
		uint16_t	command,
		uint16_t	len,
		size_t	address )

Write the properties to an ADMA descriptor.

Note: Not intended to be called directly by applications, may be used by SDHCI drivers

◆ sdhci_host_create()

SDHCI_HOST *STDCALL sdhci_host_create ( void )

Create a new SDHCI entry.

Returns: Pointer to new SDHCI entry or nil if SDHCI could not be created

◆ sdhci_host_create_ex()

SDHCI_HOST *STDCALL sdhci_host_create_ex ( uint32_t size )

Create a new SDHCI entry.

Parameters

Size	Size in bytes to allocate for new SDHCI (Including the SDHCI entry)

Returns: Pointer to new SDHCI entry or nil if SDHCI could not be created

◆ sdhci_host_destroy()

uint32_t STDCALL sdhci_host_destroy ( SDHCI_HOST * sdhci )

Destroy an existing SDHCI entry.

◆ sdhci_host_register()

uint32_t STDCALL sdhci_host_register ( SDHCI_HOST * sdhci )

Register a new SDHCI in the SDHCI table.

◆ sdhci_host_deregister()

uint32_t STDCALL sdhci_host_deregister ( SDHCI_HOST * sdhci )

Deregister a SDHCI from the SDHCI table.

◆ sdhci_host_find()

SDHCI_HOST *STDCALL sdhci_host_find ( uint32_t sdhciid )

◆ sdhci_host_enumerate()

uint32_t STDCALL sdhci_host_enumerate	(	sdhci_enumerate_cb	callback,
		void *	data )

◆ sdhci_host_notification()

uint32_t STDCALL sdhci_host_notification	(	SDHCI_HOST *	sdhci,
		sdhci_notification_cb	callback,
		void *	data,
		uint32_t	notification,
		uint32_t	flags )

◆ mmc_get_count()

uint32_t STDCALL mmc_get_count ( void )

Get the current MMC count.

MMC Helper Functions

◆ mmc_device_check()

MMC_DEVICE *STDCALL mmc_device_check ( MMC_DEVICE * mmc )

◆ mmc_is_sd()

BOOL STDCALL mmc_is_sd ( MMC_DEVICE * mmc )

◆ mmc_is_sdio()

BOOL STDCALL mmc_is_sdio ( MMC_DEVICE * mmc )

◆ mmc_get_sdhci()

SDHCI_HOST *STDCALL mmc_get_sdhci ( MMC_DEVICE * mmc )

◆ mmc_get_cid_value()

uint32_t STDCALL mmc_get_cid_value	(	MMC_DEVICE *	mmc,
		uint32_t	version,
		uint32_t	value )

Extract a CID field value from the 128 bit Card Identification register.

◆ mmc_get_csd_value()

uint32_t STDCALL mmc_get_csd_value	(	MMC_DEVICE *	mmc,
		uint32_t	value )

Extract a CSD field value from the 128 bit Card Specific register.

◆ mmc_extract_bits()

uint32_t STDCALL mmc_extract_bits	(	void *	buffer,
		uint32_t	start,
		uint32_t	size )

Start is the starting bit to extract, Size is the number of bits to extract Start is the LSB so to extract 8 bits from 127 to 120 then Start would be 120 and Size would be 8.

◆ mmc_extract_bits_ex()

uint32_t STDCALL mmc_extract_bits_ex	(	void *	buffer,
		uint32_t	length,
		uint32_t	start,
		uint32_t	size )

Length is the size of the buffer in LongWords, Start is the starting bit to extract, Size is the number of bits to extract Start is the LSB so to extract 8 bits from 127 to 120 then Start would be 120 and Size would be 8 For a 128 bit buffer (16 bytes) Length would be 4 For a 512 bit buffer (64 bytes) Length would be 16.

◆ mmc_is_multi_command()

BOOL STDCALL mmc_is_multi_command ( uint16_t command )

◆ mmc_is_non_removable()

BOOL STDCALL mmc_is_non_removable ( MMC_DEVICE * mmc )

◆ mmc_has_extended_csd()

BOOL STDCALL mmc_has_extended_csd ( MMC_DEVICE * mmc )

◆ mmc_has_set_block_count()

BOOL STDCALL mmc_has_set_block_count ( MMC_DEVICE * mmc )

◆ mmc_has_auto_block_count()

BOOL STDCALL mmc_has_auto_block_count ( MMC_DEVICE * mmc )

◆ mmc_has_auto_command_stop()

BOOL STDCALL mmc_has_auto_command_stop ( MMC_DEVICE * mmc )

◆ mmc_status_to_string()

uint32_t STDCALL mmc_status_to_string	(	uint32_t	status,
		char *	string,
		uint32_t	len )

Translates an MMC status code into a string describing it.

◆ mmc_version_to_string()

uint32_t STDCALL mmc_version_to_string	(	uint32_t	version,
		char *	string,
		uint32_t	len )

Translates an MMC version into a string.

◆ mmc_timing_to_string()

uint32_t STDCALL mmc_timing_to_string	(	uint32_t	timing,
		char *	string,
		uint32_t	len )

Translates an MMC timing into a string.

◆ mmc_bus_width_to_string()

uint32_t STDCALL mmc_bus_width_to_string	(	uint32_t	buswidth,
		char *	string,
		uint32_t	len )

Translates an MMC bus width into a string.

◆ mmc_driver_type_to_string()

uint32_t STDCALL mmc_driver_type_to_string	(	uint32_t	drivertype,
		char *	string,
		uint32_t	len )

Translates an MMC driver type into a string.

◆ mmc_signal_voltage_to_string()

uint32_t STDCALL mmc_signal_voltage_to_string	(	uint32_t	signalvoltage,
		char *	string,
		uint32_t	len )

Translates an MMC signal voltage into a string.

◆ mmc_device_type_to_string()

uint32_t STDCALL mmc_device_type_to_string	(	uint32_t	mmctype,
		char *	string,
		uint32_t	len )

◆ mmc_device_state_to_string()

uint32_t STDCALL mmc_device_state_to_string	(	uint32_t	mmcstate,
		char *	string,
		uint32_t	len )

◆ mmc_device_state_to_notification()

uint32_t STDCALL mmc_device_state_to_notification ( uint32_t state )

Convert a Device state value into the notification code for device notifications.

◆ sd_get_max_clock()

uint32_t STDCALL sd_get_max_clock ( MMC_DEVICE * mmc )

Determine the Maximum Clock (DTR) for the current card.

SD Helper Functions

◆ sd_get_cid_value()

uint32_t STDCALL sd_get_cid_value	(	MMC_DEVICE *	mmc,
		uint32_t	value )

Extract a CID field value from the 128 bit Card Identification register.

◆ sd_get_csd_value()

uint32_t STDCALL sd_get_csd_value	(	MMC_DEVICE *	mmc,
		uint32_t	version,
		uint32_t	value )

Extract a CSD field value from the 128 bit Card Specific register.

◆ sd_get_scr_value()

uint32_t STDCALL sd_get_scr_value	(	MMC_DEVICE *	mmc,
		uint32_t	value )

Extract an SCR field value from the 64 bit SD Configuration register.

◆ sd_get_ssr_value()

uint32_t STDCALL sd_get_ssr_value	(	MMC_DEVICE *	mmc,
		uint32_t	value )

Extract an SCR field value from the 512 bit SD Status register.

◆ sd_get_switch_value()

uint32_t STDCALL sd_get_switch_value	(	MMC_DEVICE *	mmc,
		uint32_t	value )

Extract a Switch field value from the 512 bit SD Switch status.

◆ sd_version_to_string()

uint32_t STDCALL sd_version_to_string	(	uint32_t	version,
		char *	string,
		uint32_t	len )

Translates an SD version into a string.

◆ sd_bus_width_to_string()

uint32_t STDCALL sd_bus_width_to_string	(	uint32_t	buswidth,
		char *	string,
		uint32_t	len )

Translates an SD bus width into a string.

◆ sdio_driver_get_count()

uint32_t STDCALL sdio_driver_get_count ( void )

Get the current SDIO driver count.

SDIO Helper Functions

◆ sdio_driver_check()

SDIO_DRIVER *STDCALL sdio_driver_check ( SDIO_DRIVER * driver )

Check if the supplied SDIO Driver is in the driver table.

◆ sdio_device_get_max_clock()

uint32_t STDCALL sdio_device_get_max_clock ( MMC_DEVICE * mmc )

Determine the Maximum Clock (DTR) for the current SDIO device.

◆ sdio_function_get_mmc()

MMC_DEVICE *STDCALL sdio_function_get_mmc ( SDIO_FUNCTION * func )

◆ sdio_function_get_sdhci()

SDHCI_HOST *STDCALL sdio_function_get_sdhci ( SDIO_FUNCTION * func )

◆ sdio_version_to_string()

uint32_t STDCALL sdio_version_to_string	(	uint32_t	version,
		char *	string,
		uint32_t	len )

Translates an SDIO version into a string.

◆ sdio_function_state_to_string()

uint32_t STDCALL sdio_function_state_to_string	(	uint32_t	sdiostate,
		char *	string,
		uint32_t	len )

◆ sdio_function_status_to_string()

uint32_t STDCALL sdio_function_status_to_string	(	uint32_t	sdiostatus,
		char *	string,
		uint32_t	len )

◆ sdio_function_state_to_notification()

uint32_t STDCALL sdio_function_state_to_notification ( uint32_t state )

Convert a Device state value into the notification code for device notifications.

◆ sdio_function_status_to_notification()

uint32_t STDCALL sdio_function_status_to_notification ( uint32_t status )

Convert a Device status value into the notification code for device notifications.

◆ sdhci_get_count()

uint32_t STDCALL sdhci_get_count ( void )

Get the current SDHCI count.

SDHCI Helper Functions

◆ sdhci_host_check()

SDHCI_HOST *STDCALL sdhci_host_check ( SDHCI_HOST * sdhci )

Check if the supplied SDHCI is in the SDHCI table.

◆ sdhci_is_spi()

BOOL STDCALL sdhci_is_spi ( SDHCI_HOST * sdhci )

◆ sdhci_has_dma()

BOOL STDCALL sdhci_has_dma ( SDHCI_HOST * sdhci )

◆ sdhci_has_cmd23()

BOOL STDCALL sdhci_has_cmd23 ( SDHCI_HOST * sdhci )

◆ sdhci_auto_cmd12()

BOOL STDCALL sdhci_auto_cmd12 ( SDHCI_HOST * sdhci )

◆ sdhci_auto_cmd23()

BOOL STDCALL sdhci_auto_cmd23 ( SDHCI_HOST * sdhci )

◆ sdhci_get_version()

uint16_t STDCALL sdhci_get_version ( SDHCI_HOST * sdhci )

◆ sdhci_get_command()

uint16_t STDCALL sdhci_get_command ( uint16_t command )

◆ sdhci_make_command()

uint16_t STDCALL sdhci_make_command	(	uint16_t	command,
		uint16_t	flags )

◆ sdhci_make_block_size()

uint16_t STDCALL sdhci_make_block_size	(	uint16_t	dma,
		uint16_t	blocksize )

◆ sdhci_version_to_string()

uint32_t STDCALL sdhci_version_to_string	(	uint32_t	version,
		char *	name,
		uint32_t	len )

Translate an SDHCI version into a string.

◆ sdhci_power_to_string()

uint32_t STDCALL sdhci_power_to_string	(	uint32_t	power,
		char *	name,
		uint32_t	len )

Translate an SDHCI power value into a string.

◆ sdhci_device_type_to_string()

uint32_t STDCALL sdhci_device_type_to_string	(	uint32_t	sdhcitype,
		char *	name,
		uint32_t	len )

◆ sdhci_host_type_to_string()

uint32_t STDCALL sdhci_host_type_to_string	(	uint32_t	sdhcitype,
		char *	name,
		uint32_t	len )

◆ sdhci_device_state_to_string()

uint32_t STDCALL sdhci_device_state_to_string	(	uint32_t	sdhcistate,
		char *	name,
		uint32_t	len )

◆ sdhci_host_state_to_string()

uint32_t STDCALL sdhci_host_state_to_string	(	uint32_t	sdhcistate,
		char *	name,
		uint32_t	len )

◆ sdhci_host_state_to_notification()

uint32_t STDCALL sdhci_host_state_to_notification ( uint32_t state )

Convert a Host state value into the notification code for device notifications.

Variable Documentation

◆ PACKED

struct _SDHCI_ADMA2_DESCRIPTOR64_V4 PACKED

Data Structures

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ MMC_NAME_PREFIX

◆ MMC_DEVICE_DESCRIPTION

◆ MMC_STORAGE_DESCRIPTION

◆ MMC_STATUS_TIMER_INTERVAL

◆ MMC_DEFAULT_BLOCKSIZE

◆ MMC_DEFAULT_BLOCKSHIFT

◆ MMC_TYPE_NONE

◆ MMC_TYPE_MMC

◆ MMC_TYPE_SD

◆ MMC_TYPE_SDIO

◆ MMC_TYPE_SD_COMBO

◆ MMC_TYPE_MAX

◆ MMC_STATE_EJECTED

◆ MMC_STATE_INSERTED

◆ MMC_STATE_MAX

◆ MMC_FLAG_NONE

◆ MMC_FLAG_CARD_PRESENT

◆ MMC_FLAG_WRITE_PROTECT

◆ MMC_FLAG_HIGH_CAPACITY

◆ MMC_FLAG_EXT_CAPACITY

◆ MMC_FLAG_UHS_I

◆ MMC_FLAG_UHS_II

◆ MMC_FLAG_BLOCK_ADDRESSED

◆ MMC_FLAG_AUTO_BLOCK_COUNT

◆ MMC_FLAG_AUTO_COMMAND_STOP

◆ MMC_FLAG_DDR_MODE

◆ MMC_FLAG_NON_REMOVABLE

◆ MMC_FLAG_SET_BLOCK_COUNT

◆ MMC_STATUS_SUCCESS

◆ MMC_STATUS_TIMEOUT

◆ MMC_STATUS_NO_MEDIA

◆ MMC_STATUS_HARDWARE_ERROR

◆ MMC_STATUS_INVALID_DATA

◆ MMC_STATUS_INVALID_PARAMETER

◆ MMC_STATUS_INVALID_SEQUENCE

◆ MMC_STATUS_OUT_OF_MEMORY

◆ MMC_STATUS_UNSUPPORTED_REQUEST

◆ MMC_STATUS_NOT_PROCESSED

◆ MMC_STATUS_OPERATION_FAILED

◆ MMC_STATUS_DEVICE_DETACHED

◆ MMC_STATUS_DEVICE_UNSUPPORTED

◆ MMC_STATUS_NOT_BOUND

◆ MMC_STATUS_ALREADY_BOUND

◆ MMC_STATUS_NOT_READY

◆ SDIO_VERSION_SDIO

◆ SDIO_VERSION_1_00

◆ SDIO_VERSION_1_10

◆ SDIO_VERSION_1_20

◆ SDIO_VERSION_2_00

◆ SDIO_VERSION_3_00

◆ SD_VERSION_SD

◆ SD_VERSION_1_0

◆ SD_VERSION_1_10

◆ SD_VERSION_2

◆ SD_VERSION_3

◆ SD_VERSION_4

◆ MMC_VERSION_MMC

◆ MMC_VERSION_1_2

◆ MMC_VERSION_1_4

◆ MMC_VERSION_2_2

◆ MMC_VERSION_3

◆ MMC_VERSION_4

◆ MMC_VERSION_4_1

◆ MMC_VERSION_4_2

◆ MMC_VERSION_4_3

◆ MMC_VERSION_4_41

◆ MMC_VERSION_4_5

◆ MMC_VERSION_5_0

◆ MMC_VERSION_5_1

◆ MMC_VERSION_UNKNOWN

◆ MMC_CAP_4_BIT_DATA

◆ MMC_CAP_MMC_HIGHSPEED

◆ MMC_CAP_SD_HIGHSPEED

◆ MMC_CAP_SDIO_IRQ