mmc.h

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/*
 * This file is part of the Ultibo project, https://ultibo.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2026 Garry Wood <garry@softoz.com.au>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef _ULTIBO_MMC_H
#define _ULTIBO_MMC_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "ultibo/globaltypes.h"
#include "ultibo/globalconst.h"
#include "ultibo/devices.h"
#include "ultibo/storage.h"
#include "ultibo/dma.h"

#define MMC_NAME_PREFIX "MMC" 
 
#define MMC_DEVICE_DESCRIPTION  "MMC/SD Device" 
#define MMC_STORAGE_DESCRIPTION "MMC/SD Storage Device" 
 
#define MMC_STATUS_TIMER_INTERVAL   1000
 
#define MMC_DEFAULT_BLOCKSIZE   512
#define MMC_DEFAULT_BLOCKSHIFT  9

#define MMC_TYPE_NONE   0
#define MMC_TYPE_MMC    1 
#define MMC_TYPE_SD 2 
#define MMC_TYPE_SDIO   3 
#define MMC_TYPE_SD_COMBO   4 
 
#define MMC_TYPE_MAX    4

#define MMC_STATE_EJECTED   0
#define MMC_STATE_INSERTED  1
 
#define MMC_STATE_MAX   1

#define MMC_FLAG_NONE   0x00000000
#define MMC_FLAG_CARD_PRESENT   0x00000001 
#define MMC_FLAG_WRITE_PROTECT  0x00000002 
#define MMC_FLAG_HIGH_CAPACITY  0x00000004 
#define MMC_FLAG_EXT_CAPACITY   0x00000008 
#define MMC_FLAG_UHS_I  0x00000010 
#define MMC_FLAG_UHS_II 0x00000020 
#define MMC_FLAG_BLOCK_ADDRESSED    0x00000040 
#define MMC_FLAG_AUTO_BLOCK_COUNT   0x00000080 
#define MMC_FLAG_AUTO_COMMAND_STOP  0x00000100 
#define MMC_FLAG_DDR_MODE   0x00000200 
#define MMC_FLAG_NON_REMOVABLE  0x00000400 
#define MMC_FLAG_SET_BLOCK_COUNT    0x00000800 

#define MMC_STATUS_SUCCESS  0 
#define MMC_STATUS_TIMEOUT  1 
#define MMC_STATUS_NO_MEDIA 2 
#define MMC_STATUS_HARDWARE_ERROR   3 
#define MMC_STATUS_INVALID_DATA 4 
#define MMC_STATUS_INVALID_PARAMETER    5 
#define MMC_STATUS_INVALID_SEQUENCE 6 
#define MMC_STATUS_OUT_OF_MEMORY    7 
#define MMC_STATUS_UNSUPPORTED_REQUEST  8 
#define MMC_STATUS_NOT_PROCESSED    9 
#define MMC_STATUS_OPERATION_FAILED 10 
#define MMC_STATUS_DEVICE_DETACHED  11 
#define MMC_STATUS_DEVICE_UNSUPPORTED   12 
#define MMC_STATUS_NOT_BOUND    13 
#define MMC_STATUS_ALREADY_BOUND    14 
#define MMC_STATUS_NOT_READY    15 

#define SDIO_VERSION_SDIO   0x00040000
#define SDIO_VERSION_1_00   (SDIO_VERSION_SDIO | 0x0100)
#define SDIO_VERSION_1_10   (SDIO_VERSION_SDIO | 0x010a)
#define SDIO_VERSION_1_20   (SDIO_VERSION_SDIO | 0x0114)
#define SDIO_VERSION_2_00   (SDIO_VERSION_SDIO | 0x0200)
#define SDIO_VERSION_3_00   (SDIO_VERSION_SDIO | 0x0300)
 
#define SD_VERSION_SD   0x00020000
#define SD_VERSION_1_0  (SD_VERSION_SD | 0x0100)
#define SD_VERSION_1_10 (SD_VERSION_SD | 0x010a)
#define SD_VERSION_2    (SD_VERSION_SD | 0x0200)
#define SD_VERSION_3    (SD_VERSION_SD | 0x0300)
#define SD_VERSION_4    (SD_VERSION_SD | 0x0400)
 
#define MMC_VERSION_MMC 0x00010000
#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x0102)
#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x0104)
#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x0202)
#define MMC_VERSION_3   (MMC_VERSION_MMC | 0x0300)
#define MMC_VERSION_4   (MMC_VERSION_MMC | 0x0400)
#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x0401)
#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x0402)
#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x0403)
#define MMC_VERSION_4_41    (MMC_VERSION_MMC | 0x0429)
#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x0405)
#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x0500)
#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x0501)
#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)

#define MMC_CAP_4_BIT_DATA  (1 << 0) 
#define MMC_CAP_MMC_HIGHSPEED   (1 << 1) 
#define MMC_CAP_SD_HIGHSPEED    (1 << 2) 
#define MMC_CAP_SDIO_IRQ    (1 << 3) 
#define MMC_CAP_SPI (1 << 4) 
#define MMC_CAP_NEEDS_POLL  (1 << 5) 
#define MMC_CAP_8_BIT_DATA  (1 << 6) 
#define MMC_CAP_AGGRESSIVE_PM   (1 << 7) 
#define MMC_CAP_NONREMOVABLE    (1 << 8) 
#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) 
#define MMC_CAP_3_3V_DDR    (1 << 11) 
#define MMC_CAP_1_8V_DDR    (1 << 12) 
#define MMC_CAP_1_2V_DDR    (1 << 13) 
#define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)
#define MMC_CAP_POWER_OFF_CARD  (1 << 14) 
#define MMC_CAP_BUS_WIDTH_TEST  (1 << 15) 
#define MMC_CAP_UHS_SDR12   (1 << 16) 
#define MMC_CAP_UHS_SDR25   (1 << 17) 
#define MMC_CAP_UHS_SDR50   (1 << 18) 
#define MMC_CAP_UHS_SDR104  (1 << 19) 
#define MMC_CAP_UHS_DDR50   (1 << 20) 
#define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50)
#define MMC_CAP_SYNC_RUNTIME_PM (1 << 21) 
#define MMC_CAP_NEED_RSP_BUSY   (1 << 22) 
#define MMC_CAP_DRIVER_TYPE_A   (1 << 23) 
#define MMC_CAP_DRIVER_TYPE_C   (1 << 24) 
#define MMC_CAP_DRIVER_TYPE_D   (1 << 25) 
#define MMC_CAP_DONE_COMPLETE   (1 << 27) 
#define MMC_CAP_CD_WAKE (1 << 28) 
#define MMC_CAP_CMD_DURING_TFR  (1 << 29) 
#define MMC_CAP_CMD23   (1 << 30) 
#define MMC_CAP_HW_RESET    (1 << 31) 

#define MMC_CAP2_BOOTPART_NOACC (1 << 0) 
#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) 
#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND  (1 << 3) 
#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) 
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) 
#define MMC_CAP2_HS200  (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR)
#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) 
#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) 
#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) 
#define MMC_CAP2_HS400_1_8V (1 << 15) 
#define MMC_CAP2_HS400_1_2V (1 << 16) 
#define MMC_CAP2_HS400  (MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
#define MMC_CAP2_SDIO_IRQ_NOTHREAD  (1 << 17) 
#define MMC_CAP2_NO_WRITE_PROTECT   (1 << 18) 
#define MMC_CAP2_NO_SDIO    (1 << 19) 
#define MMC_CAP2_HS400_ES   (1 << 20) 
#define MMC_CAP2_NO_SD  (1 << 21) 
#define MMC_CAP2_NO_MMC (1 << 22) 
#define MMC_CAP2_CQE    (1 << 23) 
#define MMC_CAP2_CQE_DCMD   (1 << 24) 
#define MMC_CAP2_AVOID_3_3V (1 << 25) 
#define MMC_CAP2_MERGE_CAPABLE  (1 << 26) 

#define MMC_DATA_READ   1
#define MMC_DATA_WRITE  2

#define MMC_BUS_WIDTH_1 0
#define MMC_BUS_WIDTH_4 2
#define MMC_BUS_WIDTH_8 3

#define MMC_BUS_SPEED_DEFAULT   0
#define MMC_BUS_SPEED_HS26  26000000
#define MMC_BUS_SPEED_HS52  52000000
#define MMC_BUS_SPEED_DDR   52000000
#define MMC_BUS_SPEED_HS200 200000000

#define MMC_TIMING_LEGACY   0
#define MMC_TIMING_MMC_HS   1
#define MMC_TIMING_SD_HS    2
#define MMC_TIMING_UHS_SDR12    3
#define MMC_TIMING_UHS_SDR25    4
#define MMC_TIMING_UHS_SDR50    5
#define MMC_TIMING_UHS_SDR104   6
#define MMC_TIMING_UHS_DDR50    7
#define MMC_TIMING_MMC_DDR52    8
#define MMC_TIMING_MMC_HS200    9
#define MMC_TIMING_MMC_HS400    10

#define MMC_SIGNAL_VOLTAGE_330  0
#define MMC_SIGNAL_VOLTAGE_180  1
#define MMC_SIGNAL_VOLTAGE_120  2

#define MMC_SET_DRIVER_TYPE_B   0
#define MMC_SET_DRIVER_TYPE_A   1
#define MMC_SET_DRIVER_TYPE_C   2
#define MMC_SET_DRIVER_TYPE_D   3

#define MMC_CMD_GO_IDLE_STATE   0
#define MMC_CMD_SEND_OP_COND    1
#define MMC_CMD_ALL_SEND_CID    2
#define MMC_CMD_SET_RELATIVE_ADDR   3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SLEEP_AWAKE 5
#define MMC_CMD_SWITCH  6
#define MMC_CMD_SELECT_CARD 7
#define MMC_CMD_SEND_EXT_CSD    8
#define MMC_CMD_SEND_CSD    9
#define MMC_CMD_SEND_CID    10
#define MMC_CMD_READ_DAT_UNTIL_STOP 11
#define MMC_CMD_STOP_TRANSMISSION   12
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_BUS_TEST_R  14
#define MMC_CMD_GO_INACTIVE_STATE   15
#define MMC_CMD_BUS_TEST_W  19
#define MMC_CMD_SPI_READ_OCR    58
#define MMC_CMD_SPI_CRC_ON_OFF  59

#define MMC_CMD_SET_BLOCKLEN    16
#define MMC_CMD_READ_SINGLE_BLOCK   17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_SEND_TUNING_BLOCK   19
#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21

#define MMC_CMD_WRITE_DAT_UNTIL_STOP    20

#define MMC_CMD_SET_BLOCK_COUNT 23
#define MMC_CMD_WRITE_SINGLE_BLOCK  24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
#define MMC_CMD_PROGRAM_CID 26
#define MMC_CMD_PROGRAM_CSD 27

#define MMC_CMD_SET_WRITE_PROT  28
#define MMC_CMD_CLR_WRITE_PROT  29
#define MMC_CMD_SEND_WRITE_PROT 30

#define MMC_CMD_ERASE_GROUP_START   35
#define MMC_CMD_ERASE_GROUP_END 36
#define MMC_CMD_ERASE   38

#define MMC_CMD_FAST_IO 39
#define MMC_CMD_GO_IRQ_STATE    40

#define MMC_CMD_LOCK_UNLOCK 42

#define MMC_CMD_APP_CMD 55
#define MMC_CMD_GEN_CMD 56
#define MMC_CMD_RES_MAN 62
 
#define MMC_CMD62_ARG1  0xEFAC62EC
#define MMC_CMD62_ARG2  0x00CBAEA7

#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136 (1 << 1) 
#define MMC_RSP_CRC (1 << 2) 
#define MMC_RSP_BUSY    (1 << 3) 
#define MMC_RSP_OPCODE  (1 << 4) 

#define MMC_RSP_NONE    (0)
#define MMC_RSP_R1  (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
#define MMC_RSP_R2  (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
#define MMC_RSP_R3  (MMC_RSP_PRESENT)
#define MMC_RSP_R4  (MMC_RSP_PRESENT)
#define MMC_RSP_R5  (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R6  (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R7  (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)

#define MMC_CMD_MASK    (3 << 5)
#define MMC_CMD_AC  (0 << 5) 
#define MMC_CMD_ADTC    (1 << 5) 
#define MMC_CMD_BC  (2 << 5) 
#define MMC_CMD_BCR (3 << 5) 

#define MMC_RSP_SPI_S1  (1 << 7) 
#define MMC_RSP_SPI_S2  (1 << 8) 
#define MMC_RSP_SPI_B4  (1 << 9) 
#define MMC_RSP_SPI_BUSY    (1 << 10) 

#define MMC_RSP_SPI_R1  (MMC_RSP_SPI_S1)
#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1 | MMC_RSP_SPI_BUSY)
#define MMC_RSP_SPI_R2  (MMC_RSP_SPI_S1 | MMC_RSP_SPI_S2)
#define MMC_RSP_SPI_R3  (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)
#define MMC_RSP_SPI_R4  (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)
#define MMC_RSP_SPI_R5  (MMC_RSP_SPI_S1 | MMC_RSP_SPI_S2)
#define MMC_RSP_SPI_R7  (MMC_RSP_SPI_S1 | MMC_RSP_SPI_B4)

#define MMC_RSP_R1_OUT_OF_RANGE (1 << 31)
#define MMC_RSP_R1_ADDRESS_ERROR    (1 << 30)
#define MMC_RSP_R1_BLOCK_LEN_ERROR  (1 << 29)
#define MMC_RSP_R1_ERASE_SEQ_ERROR  (1 << 28)
#define MMC_RSP_R1_ERASE_PARAM  (1 << 27)
#define MMC_RSP_R1_WP_VIOLATION (1 << 26)
#define MMC_RSP_R1_CARD_IS_LOCKED   (1 << 25)
#define MMC_RSP_R1_LOCK_UNLOCK_FAILED   (1 << 24)
#define MMC_RSP_R1_COM_CRC_ERROR    (1 << 23)
#define MMC_RSP_R1_ILLEGAL_COMMAND  (1 << 22)
#define MMC_RSP_R1_CARD_ECC_FAILED  (1 << 21)
#define MMC_RSP_R1_CC_ERROR (1 << 20)
#define MMC_RSP_R1_ERROR    (1 << 19)
#define MMC_RSP_R1_UNDERRUN (1 << 18)
#define MMC_RSP_R1_OVERRUN  (1 << 17)
#define MMC_RSP_R1_CID_CSD_OVERWRITE    (1 << 16)
#define MMC_RSP_R1_WP_ERASE_SKIP    (1 << 15)
#define MMC_RSP_R1_CARD_ECC_DISABLED    (1 << 14)
#define MMC_RSP_R1_ERASE_RESET  (1 << 13)
#define MMC_RSP_R1_READY_FOR_DATA   (1 << 8)
#define MMC_RSP_R1_SWITCH_ERROR (1 << 7)
#define MMC_RSP_R1_EXCEPTION_EVENT  (1 << 6)
#define MMC_RSP_R1_APP_CMD  (1 << 5)
#define MMC_RSP_R1_AKE_SEQ_ERROR    (1 << 3)

#define MMC_RSP_R1_SPI_IDLE (1 << 0)
#define MMC_RSP_R1_SPI_ERASE_RESET  (1 << 1)
#define MMC_RSP_R1_SPI_ILLEGAL_COMMAND  (1 << 2)
#define MMC_RSP_R1_SPI_COM_CRC  (1 << 3)
#define MMC_RSP_R1_SPI_ERASE_SEQ    (1 << 4)
#define MMC_RSP_R1_SPI_ADDRESS  (1 << 5)
#define MMC_RSP_R1_SPI_PARAMETER    (1 << 6)

#define MMC_RSP_R2_SPI_CARD_LOCKED  (1 << 8)
#define MMC_RSP_R2_SPI_WP_ERASE_SKIP    (1 << 9) 
#define MMC_RSP_R2_SPI_LOCK_UNLOCK_FAIL MMC_RSP_R2_SPI_WP_ERASE_SKIP
#define MMC_RSP_R2_SPI_ERROR    (1 << 10)
#define MMC_RSP_R2_SPI_CC_ERROR (1 << 11)
#define MMC_RSP_R2_SPI_CARD_ECC_ERROR   (1 << 12)
#define MMC_RSP_R2_SPI_WP_VIOLATION (1 << 13)
#define MMC_RSP_R2_SPI_ERASE_PARAM  (1 << 14)
#define MMC_RSP_R2_SPI_OUT_OF_RANGE (1 << 15) 
#define MMC_RSP_R2_SPI_CSD_OVERWRITE    MMC_RSP_R2_SPI_OUT_OF_RANGE

#define MMC_OCR_BUSY    0x80000000 
#define MMC_OCR_HCS 0x40000000 
#define MMC_OCR_UHS_II  0x20000000 
#define MMC_OCR_S18A    0x01000000 
#define MMC_OCR_VOLTAGE_MASK    0x007FFF80
#define MMC_OCR_ACCESS_MODE 0x60000000

#define MMC_CARD_STATUS_MASK    (~0x0206BF7F)
#define MMC_CARD_STATUS_ERROR   (1 << 19)
#define MMC_CARD_STATUS_CURRENT_STATE   (0x0F << 9) 
#define MMC_CARD_STATUS_READY_FOR_DATA  (1 << 8)
#define MMC_CARD_STATUS_SWITCH_ERROR    (1 << 7)

#define MMC_CURRENT_STATE_IDLE  (0 << 9)
#define MMC_CURRENT_STATE_READY (1 << 9)
#define MMC_CURRENT_STATE_IDENT (2 << 9)
#define MMC_CURRENT_STATE_STBY  (3 << 9)
#define MMC_CURRENT_STATE_TRAN  (4 << 9)
#define MMC_CURRENT_STATE_DATA  (5 << 9)
#define MMC_CURRENT_STATE_RCV   (6 << 9)
#define MMC_CURRENT_STATE_PRG   (7 << 9)
#define MMC_CURRENT_STATE_DIS   (8 << 9)

#define MMC_CID_MID 1 
#define MMC_CID_OID 2 
#define MMC_CID_PNM0    3 
#define MMC_CID_PNM1    4 
#define MMC_CID_PNM2    5 
#define MMC_CID_PNM3    6 
#define MMC_CID_PNM4    7 
#define MMC_CID_PNM5    8 
#define MMC_CID_PNM6    9 
#define MMC_CID_PRV 10 
#define MMC_CID_HRV 11 
#define MMC_CID_FRV 12 
#define MMC_CID_PSN 13 
#define MMC_CID_MDT_YEAR    14 
#define MMC_CID_MDT_MONTH   15 
#define MMC_CID_CRC 16 

#define MMC_CSD_STRUCTURE   1
#define MMC_CSD_SPECVER 2 
#define MMC_CSD_TAAC_UNIT   3
#define MMC_CSD_TAAC_VALUE  4
#define MMC_CSD_NSAC    5
#define MMC_CSD_TRAN_SPEED_UNIT 6
#define MMC_CSD_TRAN_SPEED_VALUE    37
#define MMC_CSD_CCC 7
#define MMC_CSD_READ_BL_LEN 8
#define MMC_CSD_READ_BL_PARTIAL 9
#define MMC_CSD_WRITE_BLK_MISALIGN  10
#define MMC_CSD_READ_BLK_MISALIGN   11
#define MMC_CSD_DSR_IMP 12
#define MMC_CSD_C_SIZE  13
#define MMC_CSD_VDD_R_CURR_MIN  14
#define MMC_CSD_VDD_R_CURR_MAX  15
#define MMC_CSD_VDD_W_CURR_MIN  16
#define MMC_CSD_VDD_W_CURR_MAX  17
#define MMC_CSD_C_SIZE_MULT 18
#define MMC_CSD_ERASE_BLK_EN    19 
#define MMC_CSD_SECTOR_SIZE 20 
#define MMC_CSD_ERASE_GRP_SIZE  21 
#define MMC_CSD_ERASE_GRP_MULT  22 
#define MMC_CSD_WP_GRP_SIZE 23
#define MMC_CSD_WP_GRP_ENABLE   24
#define MMC_CSD_DEFAULT_ECC 25 
#define MMC_CSD_R2W_FACTOR  26
#define MMC_CSD_WRITE_BL_LEN    27
#define MMC_CSD_WRITE_BL_PARTIAL    28
#define MMC_CSD_CONTENT_PROT_APP    29 
#define MMC_CSD_FILE_FORMAT_GRP 30
#define MMC_CSD_COPY    31
#define MMC_CSD_PERM_WRITE_PROTECT  32
#define MMC_CSD_TMP_WRITE_PROTECT   33
#define MMC_CSD_FILE_FORMAT 34
#define MMC_CSD_ECC 35 
#define MMC_CSD_CRC 36

#define MMC_CSD_STRUCT_VER_1_0  0 
#define MMC_CSD_STRUCT_VER_1_1  1 
#define MMC_CSD_STRUCT_VER_1_2  2 
#define MMC_CSD_STRUCT_EXT_CSD  3 

#define MMC_CSD_SPEC_VER_0  0 
#define MMC_CSD_SPEC_VER_1  1 
#define MMC_CSD_SPEC_VER_2  2 
#define MMC_CSD_SPEC_VER_3  3 
#define MMC_CSD_SPEC_VER_4  4 

static const uint32_t MMC_CSD_TAAC_UNITS[] = {
    1,
    10,
    100,
    1000,
    10000,
    100000,
    1000000,
    10000000};

static const uint32_t MMC_CSD_TAAC_VALUES[] = {
    0,
    10,
    12,
    13,
    15,
    20,
    25,
    30,
    35,
    40,
    45,
    50,
    55,
    60,
    70,
    80};

#define MMC_CCC_BASIC   (1 << 0) 
#define MMC_CCC_STREAM_READ (1 << 1) 
#define MMC_CCC_BLOCK_READ  (1 << 2) 
#define MMC_CCC_STREAM_WRITE    (1 << 3) 
#define MMC_CCC_BLOCK_WRITE (1 << 4) 
#define MMC_CCC_ERASE   (1 << 5) 
#define MMC_CCC_WRITE_PROT  (1 << 6) 
#define MMC_CCC_LOCK_CARD   (1 << 7) 
#define MMC_CCC_APP_SPEC    (1 << 8) 
#define MMC_CCC_IO_MODE (1 << 9) 
#define MMC_CCC_SWITCH  (1 << 10) 
#define MMC_CCC_EXTENSION   (1 << 11) 

static const uint32_t MMC_CSD_TRAN_SPEED_UNITS[] = {
    10000,
    100000,
    1000000,
    10000000,
    0,
    0,
    0,
    0};

static const uint32_t MMC_CSD_TRAN_SPEED_VALUES[] = {
    0,
    10,
    12,
    13,
    15,
    20,
    25,
    30,
    35,
    40,
    45,
    50,
    55,
    60,
    70,
    80};
 
#define SECURE_ERASE    0x80000000

#define MMC_VDD_165_195 0x00000080 
#define MMC_VDD_20_21   0x00000100 
#define MMC_VDD_21_22   0x00000200 
#define MMC_VDD_22_23   0x00000400 
#define MMC_VDD_23_24   0x00000800 
#define MMC_VDD_24_25   0x00001000 
#define MMC_VDD_25_26   0x00002000 
#define MMC_VDD_26_27   0x00004000 
#define MMC_VDD_27_28   0x00008000 
#define MMC_VDD_28_29   0x00010000 
#define MMC_VDD_29_30   0x00020000 
#define MMC_VDD_30_31   0x00040000 
#define MMC_VDD_31_32   0x00080000 
#define MMC_VDD_32_33   0x00100000 
#define MMC_VDD_33_34   0x00200000 
#define MMC_VDD_34_35   0x00400000 
#define MMC_VDD_35_36   0x00800000 

#define MMC_SWITCH_MODE_CMD_SET 0x00 
#define MMC_SWITCH_MODE_SET_BITS    0x01 
#define MMC_SWITCH_MODE_CLEAR_BITS  0x02 
#define MMC_SWITCH_MODE_WRITE_BYTE  0x03 

#define EXT_CSD_CMDQ_MODE_EN    15 
#define EXT_CSD_FLUSH_CACHE 32 
#define EXT_CSD_CACHE_CTRL  33 
#define EXT_CSD_POWER_OFF_NOTIFICATION  34 
#define EXT_CSD_PACKED_FAILURE_INDEX    35 
#define EXT_CSD_PACKED_CMD_STATUS   36 
#define EXT_CSD_EXP_EVENTS_STATUS   54 
#define EXT_CSD_EXP_EVENTS_CTRL 56 
#define EXT_CSD_DATA_SECTOR_SIZE    61 
#define EXT_CSD_ENH_START_ADDR  136 
#define EXT_CSD_ENH_SIZE_MULT   140 
#define EXT_CSD_GP_SIZE_MULT    143 
#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 
#define EXT_CSD_PARTITION_ATTRIBUTE 156 
#define EXT_CSD_MAX_ENH_SIZE_MULT   157 
#define EXT_CSD_PARTITION_SUPPORT   160 
#define EXT_CSD_HPI_MGMT    161 
#define EXT_CSD_RST_N_FUNCTION  162 
#define EXT_CSD_BKOPS_EN    163 
#define EXT_CSD_BKOPS_START 164 
#define EXT_CSD_SANITIZE_START  165 
#define EXT_CSD_WR_REL_PARAM    166 
#define EXT_CSD_WR_REL_SET  167 
#define EXT_CSD_RPMB_MULT   168 
#define EXT_CSD_FW_CONFIG   169 
#define EXT_CSD_BOOT_WP 173 
#define EXT_CSD_ERASE_GROUP_DEF 175 
#define EXT_CSD_BOOT_BUS_CONDITIONS 177 
#define EXT_CSD_PART_CONFIG 179 
#define EXT_CSD_ERASED_MEM_CONT 181 
#define EXT_CSD_BUS_WIDTH   183 
#define EXT_CSD_STROBE_SUPPORT  184 
#define EXT_CSD_HS_TIMING   185 
#define EXT_CSD_POWER_CLASS 187 
#define EXT_CSD_REV 192 
#define EXT_CSD_STRUCTURE   194 
#define EXT_CSD_CARD_TYPE   196 
#define EXT_CSD_DRIVER_STRENGTH 197 
#define EXT_CSD_OUT_OF_INTERRUPT_TIME   198 
#define EXT_CSD_PART_SWITCH_TIME    199 
#define EXT_CSD_PWR_CL_52_195   200 
#define EXT_CSD_PWR_CL_26_195   201 
#define EXT_CSD_PWR_CL_52_360   202 
#define EXT_CSD_PWR_CL_26_360   203 
#define EXT_CSD_SEC_CNT 212 
#define EXT_CSD_S_A_TIMEOUT 217 
#define EXT_CSD_REL_WR_SEC_C    222 
#define EXT_CSD_HC_WP_GRP_SIZE  221 
#define EXT_CSD_ERASE_TIMEOUT_MULT  223 
#define EXT_CSD_HC_ERASE_GRP_SIZE   224 
#define EXT_CSD_BOOT_SIZE_MULT  226 
#define EXT_CSD_SEC_TRIM_MULT   229 
#define EXT_CSD_SEC_ERASE_MULT  230 
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 
#define EXT_CSD_TRIM_MULT   232 
#define EXT_CSD_PWR_CL_200_195  236 
#define EXT_CSD_PWR_CL_200_360  237 
#define EXT_CSD_PWR_CL_DDR_52_195   238 
#define EXT_CSD_PWR_CL_DDR_52_360   239 
#define EXT_CSD_BKOPS_STATUS    246 
#define EXT_CSD_POWER_OFF_LONG_TIME 247 
#define EXT_CSD_GENERIC_CMD6_TIME   248 
#define EXT_CSD_CACHE_SIZE  249 
#define EXT_CSD_PWR_CL_DDR_200_360  253 
#define EXT_CSD_FIRMWARE_VERSION    254 
#define EXT_CSD_PRE_EOL_INFO    267 
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A  268 
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B  269 
#define EXT_CSD_CMDQ_DEPTH  307 
#define EXT_CSD_CMDQ_SUPPORT    308 
#define EXT_CSD_SUPPORTED_MODE  493 
#define EXT_CSD_TAG_UNIT_SIZE   498 
#define EXT_CSD_DATA_TAG_SUPPORT    499 
#define EXT_CSD_MAX_PACKED_WRITES   500 
#define EXT_CSD_MAX_PACKED_READS    501 
#define EXT_CSD_BKOPS_SUPPORT   502 
#define EXT_CSD_HPI_FEATURES    503 

#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_4   0x10
#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_3   0x08
#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_2   0x04
#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_1   0x02
#define EXT_CSD_PARTITION_ATTRIBUTE_ENH_USR 0x01
 
#define EXT_CSD_PARTITION_EXT_ATTRIBUTE_EN  0x04
#define EXT_CSD_PARTITION_ENH_ATTRIBUTE_EN  0x02
#define EXT_CSD_PARTITION_PARTITIONING_EN   0x01
 
#define EXT_CSD_WR_REL_PARAM_EN (1 << 2)
#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1 << 4)
 
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    0x40
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   0x10
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    0x04
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN 0x01
 
#define EXT_CSD_PART_CONFIG_ACC_MASK    0x07
#define EXT_CSD_PART_CONFIG_ACC_BOOT0   0x01
#define EXT_CSD_PART_CONFIG_ACC_RPMB    0x03
#define EXT_CSD_PART_CONFIG_ACC_GP0 0x04
 
#define EXT_CSD_PART_SETTING_COMPLETED  0x01
#define EXT_CSD_PART_SUPPORT_PART_EN    0x01
 
#define EXT_CSD_CMD_SET_NORMAL  (1 << 0)
#define EXT_CSD_CMD_SET_SECURE  (1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE    (1 << 2)
 
#define EXT_CSD_CARD_TYPE_HS_26 (1 << 0) 
#define EXT_CSD_CARD_TYPE_HS_52 (1 << 1) 
#define EXT_CSD_CARD_TYPE_HS    (EXT_CSD_CARD_TYPE_HS_26 | EXT_CSD_CARD_TYPE_HS_52)
#define EXT_CSD_CARD_TYPE_DDR_1_8V  (1 << 2) 
#define EXT_CSD_CARD_TYPE_DDR_1_2V  (1 << 3) 
#define EXT_CSD_CARD_TYPE_DDR_52    (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_HS200_1_8V    (1 << 4) 
#define EXT_CSD_CARD_TYPE_HS200_1_2V    (1 << 5) 
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | EXT_CSD_CARD_TYPE_HS200_1_2V)
#define EXT_CSD_CARD_TYPE_HS400_1_8V    (1 << 6) 
#define EXT_CSD_CARD_TYPE_HS400_1_2V    (1 << 7) 
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | EXT_CSD_CARD_TYPE_HS400_1_2V)
#define EXT_CSD_CARD_TYPE_HS400ES   (1 << 8) 
 
#define EXT_CSD_BUS_WIDTH_1 0 
#define EXT_CSD_BUS_WIDTH_4 1 
#define EXT_CSD_BUS_WIDTH_8 2 
#define EXT_CSD_DDR_BUS_WIDTH_4 5 
#define EXT_CSD_DDR_BUS_WIDTH_8 6 
#define EXT_CSD_BUS_WIDTH_STROBE    1 << 7 
 
#define EXT_CSD_TIMING_BC   0 
#define EXT_CSD_TIMING_HS   1 
#define EXT_CSD_TIMING_HS200    2 
#define EXT_CSD_TIMING_HS400    3 
#define EXT_CSD_DRV_STR_SHIFT   4 
 
#define EXT_CSD_SEC_ER_EN   1 << 0
#define EXT_CSD_SEC_BD_BLK_EN   1 << 2
#define EXT_CSD_SEC_GB_CL_EN    1 << 4
#define EXT_CSD_SEC_SANITIZE    1 << 6 
 
#define EXT_CSD_RST_N_EN_MASK   0x03
#define EXT_CSD_RST_N_ENABLED   1 
 
#define EXT_CSD_NO_POWER_NOTIFICATION   0
#define EXT_CSD_POWER_ON    1
#define EXT_CSD_POWER_OFF_SHORT 2
#define EXT_CSD_POWER_OFF_LONG  3
 
#define EXT_CSD_PWR_CL_8BIT_MASK    0xF0 
#define EXT_CSD_PWR_CL_4BIT_MASK    0x0F 
#define EXT_CSD_PWR_CL_8BIT_SHIFT   4
#define EXT_CSD_PWR_CL_4BIT_SHIFT   0
 
#define EXT_CSD_PACKED_EVENT_EN 1 << 3

#define EXT_CSD_URGENT_BKOPS    1 << 0
#define EXT_CSD_DYNCAP_NEEDED   1 << 1
#define EXT_CSD_SYSPOOL_EXHAUSTED   1 << 2
#define EXT_CSD_PACKED_FAILURE  1 << 3
 
#define EXT_CSD_PACKED_GENERIC_ERROR    1 << 0
#define EXT_CSD_PACKED_INDEXED_ERROR    1 << 1

#define EXT_CSD_BKOPS_LEVEL_2   0x02

#define EXT_CSD_MANUAL_BKOPS_MASK   0x01
#define EXT_CSD_AUTO_BKOPS_MASK 0x02

#define EXT_CSD_CMDQ_MODE_ENABLED   1 << 0
#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
#define EXT_CSD_CMDQ_SUPPORTED  1 << 0

#define MMC_HIGH_26_MAX_DTR 26000000
#define MMC_HIGH_52_MAX_DTR 52000000
#define MMC_HIGH_DDR_MAX_DTR    52000000
#define MMC_HS200_MAX_DTR   200000000

#define MMC_MIN_PART_SWITCH_TIME    300 

#define MMCPART_NOAVAILABLE (0xff)
#define PART_ACCESS_MASK    (0x07)
#define PART_SUPPORT    (0x01)
#define ENHNCD_SUPPORT  (0x02)
#define PART_ENH_ATTRIB (0x1f)

#define MMC_MAX_BLOCK_LEN   512

#define MMC_MAX_BLOCK_COUNT 65535

#define MMC_NUM_BOOT_PARTITION  2
#define MMC_NUM_GP_PARTITION    4
#define MMC_NUM_PHY_PARTITION   7

#define MMC_DEFAULT_CMD6_TIMEOUT_MS 500
#define MMC_MIN_CACHE_EN_TIMEOUT_MS 1600

#define MMC_FIRMWARE_VERSION_LEN    8

#define MMC_DISCARD_FEATURE 0x01

#define MMC_BUSY_CMD6   0
#define MMC_BUSY_ERASE  1
#define MMC_BUSY_HPI    2

#define MMC_ERASE_ARG   0x00000000
#define MMC_SECURE_ERASE_ARG    0x80000000
#define MMC_TRIM_ARG    0x00000001
#define MMC_DISCARD_ARG 0x00000003
#define MMC_SECURE_TRIM1_ARG    0x80000001
#define MMC_SECURE_TRIM2_ARG    0x80008000
#define MMC_SECURE_ARGS 0x80000000
#define MMC_TRIM_ARGS   0x00008001

#define SD_DEFAULT_BLOCKSIZE    512
#define SD_DEFAULT_BLOCKSHIFT   9

#define SD_BUS_WIDTH_1  0
#define SD_BUS_WIDTH_4  2

#define SD_BUS_SPEED_DEFAULT    25000000
#define SD_BUS_SPEED_HS 50000000
#define SD_BUS_SPEED_UHS_SDR12  25000000
#define SD_BUS_SPEED_UHS_SDR25  50000000
#define SD_BUS_SPEED_UHS_DDR50  50000000
#define SD_BUS_SPEED_UHS_SDR50  100000000
#define SD_BUS_SPEED_UHS_SDR104 208000000

#define SD_CMD_SEND_RELATIVE_ADDR   3
#define SD_CMD_SEND_IF_COND 8
#define SD_CMD_SWITCH_VOLTAGE   11

#define SD_CMD_SWITCH   6 

#define SD_CMD_ERASE_WR_BLK_START   32
#define SD_CMD_ERASE_WR_BLK_END 33

#define SD_CMD_APP_SET_BUS_WIDTH    6
#define SD_CMD_APP_SD_STATUS    13
#define SD_CMD_APP_SEND_NUM_WR_BLKS 22
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51


#define SD_SWITCH_MODE_CHECK    0
#define SD_SWITCH_MODE_SWITCH   1

#define SD_SWITCH_FUNCTION_GROUP_ACCESS 0 
#define SD_SWITCH_FUNCTION_GROUP_COMMAND    1 
#define SD_SWITCH_FUNCTION_GROUP_DRIVER 2 
#define SD_SWITCH_FUNCTION_GROUP_POWER  3 

#define SD_SWITCH_ACCESS_MODE_DEF   0 
#define SD_SWITCH_ACCESS_MODE_HS    1 
#define SD_SWITCH_ACCESS_MODE_SDR50 2 
#define SD_SWITCH_ACCESS_MODE_SDR104    3 
#define SD_SWITCH_ACCESS_MODE_DDR50 4 

#define SD_SWITCH_COMMAND_SYSTEM_DEF    0 
#define SD_SWITCH_COMMAND_SYSTEM_EC 1 
#define SD_SWITCH_COMMAND_SYSTEM_OTP    3 
#define SD_SWITCH_COMMAND_SYSTEM_ASSD   4 

#define SD_SWITCH_DRIVER_STRENGTH_DEF   0 
#define SD_SWITCH_DRIVER_STRENGTH_TYPE_A    1 
#define SD_SWITCH_DRIVER_STRENGTH_TYPE_C    2 
#define SD_SWITCH_DRIVER_STRENGTH_TYPE_D    3 

#define SD_SWITCH_POWER_LIMIT_DEF   0 
#define SD_SWITCH_POWER_LIMIT_144   1 
#define SD_SWITCH_POWER_LIMIT_216   2 
#define SD_SWITCH_POWER_LIMIT_288   3 
#define SD_SWITCH_POWER_LIMIT_180   4 


#define SD_SEND_IF_COND_CHECK_PATTERN   0xAA
#define SD_SEND_IF_COND_VOLTAGE_MASK    0x00FF8000 

#define SD_SEND_OP_COND_VOLTAGE_MASK    0x00FF8000 

#define SD_OCR_CCS  0x40000000 
#define SD_OCR_UHS_II   0x20000000 
#define SD_OCR_XPC  0x10000000 
#define SD_OCR_S18A 0x01000000 

#define SD_CSD_STRUCT_VER_1_0   0 
#define SD_CSD_STRUCT_VER_2_0   1 

#define SD_SSR_DAT_BUS_WIDTH    1
#define SD_SSR_SECURED_MODE 2
#define SD_SSR_SD_CARD_TYPE 3
#define SD_SSR_SIZE_OF_PROTECTED_AREA   4
#define SD_SSR_SPEED_CLASS  5
#define SD_SSR_PERFORMANCE_MOVE 6
#define SD_SSR_AU_SIZE  7
#define SD_SSR_ERASE_SIZE   8
#define SD_SSR_ERASE_TIMEOUT    9
#define SD_SSR_ERASE_OFFSET 10
#define SD_SSR_UHS_SPEED_GRADE  11
#define SD_SSR_UHS_AU_SIZE  12

#define SD_SSR_BUS_WIDTH_1  0 
#define SD_SSR_BUS_WIDTH_4  2 

#define SD_SSR_CARD_TYPE_RW 0x0000 
#define SD_SSR_CARD_TYPE_ROM    0x0001 
#define SD_SSR_CARD_TYPE_OTP    0x0002 

#define SD_SSR_SPEED_CLASS_0    0x00 
#define SD_SSR_SPEED_CLASS_2    0x01 
#define SD_SSR_SPEED_CLASS_4    0x02 
#define SD_SSR_SPEED_CLASS_6    0x03 
#define SD_SSR_SPEED_CLASS_10   0x04 

static const uint32_t SD_SSR_AU_SIZE_VALUES[] = {
    0, 
    0x00004000, 
    0x00008000, 
    0x00010000, 
    0x00020000, 
    0x00040000, 
    0x00080000, 
    0x00100000, 
    0x00200000, 
    0x00400000, 
    0x00800000, 
    0x00800000 + 0x00400000, 
    0x01000000, 
    0x01000000 + 0x00800000, 
    0x02000000, 
    0x04000000}; 

#define SD_SSR_UHS_SPEED_GRADE_0    0 
#define SD_SSR_UHS_SPEED_GRADE_1    1 

static const uint32_t SD_SSR_UHS_AU_SIZE_VALUES[] = {
    0, 
    0, 
    0, 
    0, 
    0, 
    0, 
    0, 
    0x00100000, 
    0x00200000, 
    0x00400000, 
    0x00800000, 
    0x00800000 + 0x00400000, 
    0x01000000, 
    0x01000000 + 0x00800000, 
    0x02000000, 
    0x04000000}; 

#define SD_SWITCH_MAXIMUM_CURRENT   1
#define SD_SWITCH_GROUP6_SUPPORT    2
#define SD_SWITCH_GROUP5_SUPPORT    3
#define SD_SWITCH_GROUP4_SUPPORT    4
#define SD_SWITCH_GROUP3_SUPPORT    5
#define SD_SWITCH_GROUP2_SUPPORT    6
#define SD_SWITCH_GROUP1_SUPPORT    7
#define SD_SWITCH_GROUP6_SELECTION  8
#define SD_SWITCH_GROUP5_SELECTION  9
#define SD_SWITCH_GROUP4_SELECTION  10
#define SD_SWITCH_GROUP3_SELECTION  11
#define SD_SWITCH_GROUP2_SELECTION  12
#define SD_SWITCH_GROUP1_SELECTION  13
#define SD_SWITCH_STRUCT_VERSION    14
#define SD_SWITCH_GROUP6_BUSY_STATUS    15
#define SD_SWITCH_GROUP5_BUSY_STATUS    16
#define SD_SWITCH_GROUP4_BUSY_STATUS    17
#define SD_SWITCH_GROUP3_BUSY_STATUS    18
#define SD_SWITCH_GROUP2_BUSY_STATUS    19
#define SD_SWITCH_GROUP1_BUSY_STATUS    20

#define SD_SWITCH_GROUP1_SDR12  (1 << 0)
#define SD_SWITCH_GROUP1_HS (1 << 1)
#define SD_SWITCH_GROUP1_SDR25  (1 << 1)
#define SD_SWITCH_GROUP1_SDR50  (1 << 2)
#define SD_SWITCH_GROUP1_SDR104 (1 << 3)
#define SD_SWITCH_GROUP1_DDR50  (1 << 4)

#define SD_SWITCH_GROUP3_TYPE_B (1 << 0)
#define SD_SWITCH_GROUP3_TYPE_A (1 << 1)
#define SD_SWITCH_GROUP3_TYPE_C (1 << 2)
#define SD_SWITCH_GROUP3_TYPE_D (1 << 3)

#define SD_SWITCH_STRUCT_VER_0  0 
#define SD_SWITCH_STRUCT_VER_1  1 

#define SD_SCR_STRUCTURE    1
#define SD_SCR_SD_SPEC  2
#define SD_SCR_DATA_STAT_AFTER_ERASE    3
#define SD_SCR_SD_SECURITY  4
#define SD_SCR_SD_BUS_WIDTHS    5
#define SD_SCR_SD_SPEC3 6
#define SD_SCR_EX_SECURITY  7
#define SD_SCR_SD_SPEC4 8
#define SD_SCR_CMD_SUPPORT  9

#define SD_SCR_STRUCT_VER_1_0   0 

#define SD_SCR_SPEC_VER_0   0 
#define SD_SCR_SPEC_VER_1   1 
#define SD_SCR_SPEC_VER_2   2 

#define SD_SCR_SECURITY_VER_0   0 
#define SD_SCR_SECURITY_VER_2   2 
#define SD_SCR_SECURITY_VER_3   3 
#define SD_SCR_SECURITY_VER_4   4 

#define SD_SCR_BUS_WIDTH_1  (1 << 0) 
#define SD_SCR_BUS_WIDTH_4  (1 << 2) 

#define SD_SCR_EX_SECURITY_VER_0    0 

#define SD_SCR_CMD20_SUPPORT    (1 << 0) 
#define SD_SCR_CMD23_SUPPORT    (1 << 1) 
#define SD_SCR_CMD48_49_SUPPORT (1 << 2) 
#define SD_SCR_CMD58_59_SUPPORT (1 << 3) 

#define SDIO_STATE_DETACHED 0
#define SDIO_STATE_DETACHING    1
#define SDIO_STATE_ATTACHING    2
#define SDIO_STATE_ATTACHED 3
 
#define SDIO_STATE_MAX  3

#define SDIO_STATUS_UNBOUND 0
#define SDIO_STATUS_BOUND   1
 
#define SDIO_STATUS_MAX 1

#define SDIO_CMD_SEND_OP_COND   5
#define SDIO_CMD_RW_DIRECT  52
#define SDIO_CMD_RW_EXTENDED    53


 

#define SDIO_RSP_R4_18V_PRESENT (1 << 24)
#define SDIO_RSP_R4_MEMORY_PRESENT  (1 << 27)

#define SDIO_RSP_R5_COM_CRC_ERROR   (1 << 15)
#define SDIO_RSP_R5_ILLEGAL_COMMAND (1 << 14)
#define SDIO_RSP_R5_ERROR   (1 << 11)
#define SDIO_RSP_R5_FUNCTION_NUMBER (1 << 9)
#define SDIO_RSP_R5_OUT_OF_RANGE    (1 << 8)


#define SDIO_CCCR_CCCR  0x00
#define SDIO_CCCR_SD    0x01
#define SDIO_CCCR_IOEx  0x02
#define SDIO_CCCR_IORx  0x03
#define SDIO_CCCR_IENx  0x04 
#define SDIO_CCCR_INTx  0x05 
#define SDIO_CCCR_ABORT 0x06 
#define SDIO_CCCR_IF    0x07 
#define SDIO_CCCR_CAPS  0x08
#define SDIO_CCCR_CIS   0x09 
#define SDIO_CCCR_SUSPEND   0x0c
#define SDIO_CCCR_SELx  0x0d
#define SDIO_CCCR_EXECx 0x0e
#define SDIO_CCCR_READYx    0x0f
#define SDIO_CCCR_BLKSIZE   0x10
#define SDIO_CCCR_POWER 0x12
#define SDIO_CCCR_SPEED 0x13
#define SDIO_CCCR_UHS   0x14
#define SDIO_CCCR_DRIVE_STRENGTH    0x15

#define SDIO_CCCR_REV_1_00  0 
#define SDIO_CCCR_REV_1_10  1 
#define SDIO_CCCR_REV_1_20  2 
#define SDIO_CCCR_REV_3_00  3 
 
#define SDIO_SDIO_REV_1_00  0 
#define SDIO_SDIO_REV_1_10  1 
#define SDIO_SDIO_REV_1_20  2 
#define SDIO_SDIO_REV_2_00  3 
#define SDIO_SDIO_REV_3_00  4 

#define SDIO_SD_REV_1_01    0 
#define SDIO_SD_REV_1_10    1 
#define SDIO_SD_REV_2_00    2 
#define SDIO_SD_REV_3_00    3 

#define SDIO_BUS_WIDTH_MASK 0x03 
#define SDIO_BUS_WIDTH_1BIT 0x00
#define SDIO_BUS_WIDTH_RESERVED 0x01
#define SDIO_BUS_WIDTH_4BIT 0x02
#define SDIO_BUS_ECSI   0x20 
#define SDIO_BUS_SCSI   0x40 
 
#define SDIO_BUS_ASYNC_INT  0x20
 
#define SDIO_BUS_CD_DISABLE 0x80 

#define SDIO_CCCR_CAP_SDC   0x01 
#define SDIO_CCCR_CAP_SMB   0x02 
#define SDIO_CCCR_CAP_SRW   0x04 
#define SDIO_CCCR_CAP_SBS   0x08 
#define SDIO_CCCR_CAP_S4MI  0x10 
#define SDIO_CCCR_CAP_E4MI  0x20 
#define SDIO_CCCR_CAP_LSC   0x40 
#define SDIO_CCCR_CAP_4BLS  0x80 

#define SDIO_POWER_SMPC 0x01 
#define SDIO_POWER_EMPC 0x02 

#define SDIO_SPEED_SHS  0x01 
#define SDIO_SPEED_BSS_SHIFT    1
#define SDIO_SPEED_BSS_MASK (7 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_SDR12    (0 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_SDR25    (1 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_SDR50    (2 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_SDR104   (3 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_DDR50    (4 << SDIO_SPEED_BSS_SHIFT)
#define SDIO_SPEED_EHS  SDIO_SPEED_SDR25 

#define SDIO_UHS_SDR50  0x01
#define SDIO_UHS_SDR104 0x02
#define SDIO_UHS_DDR50  0x04

#define SDIO_SDTx_MASK  0x07
#define SDIO_DRIVE_SDTA (1 << 0)
#define SDIO_DRIVE_SDTC (1 << 1)
#define SDIO_DRIVE_SDTD (1 << 2)
#define SDIO_DRIVE_DTSx_MASK    0x03
#define SDIO_DRIVE_DTSx_SHIFT   4
#define SDIO_DTSx_SET_TYPE_B    (0 << SDIO_DRIVE_DTSx_SHIFT)
#define SDIO_DTSx_SET_TYPE_A    (1 << SDIO_DRIVE_DTSx_SHIFT)
#define SDIO_DTSx_SET_TYPE_C    (2 << SDIO_DRIVE_DTSx_SHIFT)
#define SDIO_DTSx_SET_TYPE_D    (3 << SDIO_DRIVE_DTSx_SHIFT)

#define SDIO_FBR_BASE(f)    ((f) * 0x100) /* base of function f's FBRs */
#define SDIO_FBR_STD_IF 0x00
#define SDIO_FBR_STD_IF_EXT 0x01
#define SDIO_FBR_POWER  0x02
#define SDIO_FBR_CIS    0x09 
#define SDIO_FBR_CSA    0x0C 
#define SDIO_FBR_CSA_DATA   0x0F
#define SDIO_FBR_BLKSIZE    0x10 

#define SDIO_FBR_SUPPORTS_CSA   0x40 
#define SDIO_FBR_ENABLE_CSA 0x80 

#define SDIO_FBR_POWER_SPS  0x01 
#define SDIO_FBR_POWER_EPS  0x02 

#define SDIO_CLASS_NONE 0x00 
#define SDIO_CLASS_UART 0x01 
#define SDIO_CLASS_BT_A 0x02 
#define SDIO_CLASS_BT_B 0x03 
#define SDIO_CLASS_GPS  0x04 
#define SDIO_CLASS_CAMERA   0x05 
#define SDIO_CLASS_PHS  0x06 
#define SDIO_CLASS_WLAN 0x07 
#define SDIO_CLASS_ATA  0x08 
#define SDIO_CLASS_BT_AMP   0x09 

#define SDIO_VENDOR_ID_STE  0x0020
#define SDIO_VENDOR_ID_INTEL    0x0089
#define SDIO_VENDOR_ID_CGUYS    0x0092
#define SDIO_VENDOR_ID_TI   0x0097
#define SDIO_VENDOR_ID_ATHEROS  0x0271
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
#define SDIO_VENDOR_ID_MARVELL  0x02df
#define SDIO_VENDOR_ID_MEDIATEK 0x037a
#define SDIO_VENDOR_ID_MICROCHIP_WILC   0x0296
#define SDIO_VENDOR_ID_SIANO    0x039a
#define SDIO_VENDOR_ID_RSI  0x041b
#define SDIO_VENDOR_ID_TI_WL1251    0x104c

#define SDIO_DEVICE_ID_STE_CW1200   0x2280
 
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX  0x1402
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIFI   0x1403
#define SDIO_DEVICE_ID_INTEL_IWMC3200TOP    0x1404
#define SDIO_DEVICE_ID_INTEL_IWMC3200GPS    0x1405
#define SDIO_DEVICE_ID_INTEL_IWMC3200BT 0x1406
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX_2G5  0x1407
 
#define SDIO_DEVICE_ID_CGUYS_EW_CG1102GC    0x0004
 
#define SDIO_DEVICE_ID_TI_WL1271    0x4076
 
#define SDIO_DEVICE_ID_ATHEROS_AR6003_00    0x0300
#define SDIO_DEVICE_ID_ATHEROS_AR6003_01    0x0301
#define SDIO_DEVICE_ID_ATHEROS_AR6004_00    0x0400
#define SDIO_DEVICE_ID_ATHEROS_AR6004_01    0x0401
#define SDIO_DEVICE_ID_ATHEROS_AR6004_02    0x0402
#define SDIO_DEVICE_ID_ATHEROS_AR6004_18    0x0418
#define SDIO_DEVICE_ID_ATHEROS_AR6004_19    0x0419
#define SDIO_DEVICE_ID_ATHEROS_AR6005   0x050A
#define SDIO_DEVICE_ID_ATHEROS_QCA9377  0x0701
 
#define SDIO_DEVICE_ID_BROADCOM_NINTENDO_WII    0x044b
#define SDIO_DEVICE_ID_BROADCOM_43241   0x4324
#define SDIO_DEVICE_ID_BROADCOM_4329    0x4329
#define SDIO_DEVICE_ID_BROADCOM_4330    0x4330
#define SDIO_DEVICE_ID_BROADCOM_4334    0x4334
#define SDIO_DEVICE_ID_BROADCOM_4335_4339   0x4335
#define SDIO_DEVICE_ID_BROADCOM_4339    0x4339
#define SDIO_DEVICE_ID_BROADCOM_4345    0x4345
#define SDIO_DEVICE_ID_BROADCOM_4354    0x4354
#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_89359   0x4355
#define SDIO_DEVICE_ID_BROADCOM_4356    0x4356
#define SDIO_DEVICE_ID_BROADCOM_4359    0x4359
#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373    0x4373
#define SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012   0xa804
#define SDIO_DEVICE_ID_BROADCOM_43143   0xa887
#define SDIO_DEVICE_ID_BROADCOM_43340   0xa94c
#define SDIO_DEVICE_ID_BROADCOM_43341   0xa94d
#define SDIO_DEVICE_ID_BROADCOM_43362   0xa962
#define SDIO_DEVICE_ID_BROADCOM_43364   0xa9a4
#define SDIO_DEVICE_ID_BROADCOM_43430   0xa9a6
#define SDIO_DEVICE_ID_BROADCOM_43455   0xa9bf
 
#define SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103
#define SDIO_DEVICE_ID_MARVELL_8688_WLAN    0x9104
#define SDIO_DEVICE_ID_MARVELL_8688_BT  0x9105
#define SDIO_DEVICE_ID_MARVELL_8786_WLAN    0x9116
#define SDIO_DEVICE_ID_MARVELL_8787_WLAN    0x9119
#define SDIO_DEVICE_ID_MARVELL_8787_BT  0x911a
#define SDIO_DEVICE_ID_MARVELL_8787_BT_AMP  0x911b
#define SDIO_DEVICE_ID_MARVELL_8797_F0  0x9128
#define SDIO_DEVICE_ID_MARVELL_8797_WLAN    0x9129
#define SDIO_DEVICE_ID_MARVELL_8797_BT  0x912a
#define SDIO_DEVICE_ID_MARVELL_8897_WLAN    0x912d
#define SDIO_DEVICE_ID_MARVELL_8897_BT  0x912e
#define SDIO_DEVICE_ID_MARVELL_8887_F0  0x9134
#define SDIO_DEVICE_ID_MARVELL_8887_WLAN    0x9135
#define SDIO_DEVICE_ID_MARVELL_8887_BT  0x9136
#define SDIO_DEVICE_ID_MARVELL_8801_WLAN    0x9139
#define SDIO_DEVICE_ID_MARVELL_8997_F0  0x9140
#define SDIO_DEVICE_ID_MARVELL_8997_WLAN    0x9141
#define SDIO_DEVICE_ID_MARVELL_8997_BT  0x9142
#define SDIO_DEVICE_ID_MARVELL_8977_WLAN    0x9145
#define SDIO_DEVICE_ID_MARVELL_8977_BT  0x9146
#define SDIO_DEVICE_ID_MARVELL_8987_WLAN    0x9149
#define SDIO_DEVICE_ID_MARVELL_8987_BT  0x914a
 
#define SDIO_DEVICE_ID_MEDIATEK_MT7663  0x7663
#define SDIO_DEVICE_ID_MEDIATEK_MT7668  0x7668
 
#define SDIO_DEVICE_ID_MICROCHIP_WILC1000   0x5347
 
#define SDIO_DEVICE_ID_SIANO_NOVA_B0    0x0201
#define SDIO_DEVICE_ID_SIANO_NICE   0x0202
#define SDIO_DEVICE_ID_SIANO_VEGA_A0    0x0300
#define SDIO_DEVICE_ID_SIANO_VENICE 0x0301
#define SDIO_DEVICE_ID_SIANO_MING   0x0302
#define SDIO_DEVICE_ID_SIANO_PELE   0x0500
#define SDIO_DEVICE_ID_SIANO_RIO    0x0600
#define SDIO_DEVICE_ID_SIANO_DENVER_2160    0x0700
#define SDIO_DEVICE_ID_SIANO_DENVER_1530    0x0800
#define SDIO_DEVICE_ID_SIANO_NOVA_A0    0x1100
#define SDIO_DEVICE_ID_SIANO_STELLAR    0x5347
 
#define SDIO_DEVICE_ID_TI_WL1251    0x9066

#define CISTPL_NULL 0x00
#define CISTPL_CHECKSUM 0x10
#define CISTPL_VERS_1   0x15
#define CISTPL_ALTSTR   0x16
#define CISTPL_MANFID   0x20
#define CISTPL_FUNCID   0x21
#define CISTPL_FUNCE    0x22
#define CISTPL_SDIO_STD 0x91
#define CISTPL_SDIO_EXT 0x92
#define CISTPL_END  0xFF
 
#define SDIO_MAX_FUNCTIONS  7
 
#define SDIO_READ_CIS_TIMEOUT_MS    (10 * 1000) 

#define SDHCI_NAME_PREFIX   "SDHCI" 

#define SDHCI_TYPE_NONE 0
#define SDHCI_TYPE_MMC  1 
#define SDHCI_TYPE_SD   2 
#define SDHCI_TYPE_MMCI 3 
 
#define SDHCI_TYPE_MAX  3

#define SDHCI_STATE_DISABLED    0
#define SDHCI_STATE_ENABLED 1
 
#define SDHCI_STATE_MAX 1

#define SDHCI_FLAG_NONE 0x00000000
#define SDHCI_FLAG_SDMA 0x00000001 
#define SDHCI_FLAG_ADMA 0x00000002 
#define SDHCI_FLAG_SPI  0x00000004 
#define SDHCI_FLAG_CRC_ENABLE   0x00000008
#define SDHCI_FLAG_NON_STANDARD 0x00000010 
#define SDHCI_FLAG_AUTO_CMD12   0x00000020 
#define SDHCI_FLAG_AUTO_CMD23   0x00000040 
#define SDHCI_FLAG_64_BIT_DMA   0x00000080 
#define SDHCI_FLAG_EXTERNAL_DMA 0x00000100 
#define SDHCI_FLAG_BUS_ADDRESSES    0x00000200 

#define SDHCI_DMA_ADDRESS   0x00
#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
#define SDHCI_BLOCK_SIZE    0x04
#define SDHCI_BLOCK_COUNT   0x06
#define SDHCI_ARGUMENT  0x08
#define SDHCI_TRANSFER_MODE 0x0C
#define SDHCI_COMMAND   0x0E
#define SDHCI_RESPONSE  0x10
#define SDHCI_BUFFER    0x20
#define SDHCI_PRESENT_STATE 0x24
#define SDHCI_HOST_CONTROL  0x28
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
#define SDHCI_WAKE_UP_CONTROL   0x2B
#define SDHCI_CLOCK_CONTROL 0x2C
#define SDHCI_TIMEOUT_CONTROL   0x2E
#define SDHCI_SOFTWARE_RESET    0x2F
#define SDHCI_INT_STATUS    0x30
#define SDHCI_INT_ENABLE    0x34
#define SDHCI_SIGNAL_ENABLE 0x38
#define SDHCI_AUTO_CMD_STATUS   0x3C 
#define SDHCI_HOST_CONTROL2 0x3E
#define SDHCI_CAPABILITIES  0x40
#define SDHCI_CAPABILITIES_1    0x44
#define SDHCI_MAX_CURRENT   0x48
#define SDHCI_SET_ACMD12_ERROR  0x50
#define SDHCI_SET_INT_ERROR 0x52
#define SDHCI_ADMA_ERROR    0x54
#define SDHCI_ADMA_ADDRESS  0x58
#define SDHCI_ADMA_ADDRESS_HI   0x5C
#define SDHCI_PRESET_FOR_SDR12  0x66
#define SDHCI_PRESET_FOR_SDR25  0x68
#define SDHCI_PRESET_FOR_SDR50  0x6A
#define SDHCI_PRESET_FOR_SDR104 0x6C
#define SDHCI_PRESET_FOR_DDR50  0x6E
#define SDHCI_PRESET_FOR_HS400  0x74 
#define SDHCI_SLOT_INT_STATUS   0xFC
#define SDHCI_HOST_VERSION  0xFE

#define SDHCI_TRNS_DMA  0x01
#define SDHCI_TRNS_BLK_CNT_EN   0x02
#define SDHCI_TRNS_AUTO_CMD12   0x04 
#define SDHCI_TRNS_AUTO_CMD23   0x08
#define SDHCI_TRNS_AUTO_SEL SDHCI_TRNS_AUTO_CMD12 | SDHCI_TRNS_AUTO_CMD23
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI    0x20

#define SDHCI_CMD_RESP_MASK 0x03
#define SDHCI_CMD_CRC   0x08
#define SDHCI_CMD_INDEX 0x10
#define SDHCI_CMD_DATA  0x20
#define SDHCI_CMD_ABORTCMD  0xC0

#define SDHCI_CMD_RESP_NONE 0x00
#define SDHCI_CMD_RESP_LONG 0x01
#define SDHCI_CMD_RESP_SHORT    0x02
#define SDHCI_CMD_RESP_SHORT_BUSY   0x03

#define SDHCI_CMD_INHIBIT   0x00000001
#define SDHCI_DATA_INHIBIT  0x00000002
#define SDHCI_DOING_WRITE   0x00000100
#define SDHCI_DOING_READ    0x00000200
#define SDHCI_SPACE_AVAILABLE   0x00000400
#define SDHCI_DATA_AVAILABLE    0x00000800
#define SDHCI_CARD_PRESENT  0x00010000
#define SDHCI_CARD_STATE_STABLE 0x00020000 
#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 
#define SDHCI_WRITE_PROTECT 0x00080000 
#define SDHCI_DATA_LEVEL_MASK   0x00F00000 
#define SDHCI_DATA_0_LEVEL_MASK 0x00100000 
#define SDHCI_CMD_LEVEL 0x01000000 

#define SDHCI_CTRL_LED  0x01
#define SDHCI_CTRL_4BITBUS  0x02
#define SDHCI_CTRL_HISPD    0x04
#define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1    0x08
#define SDHCI_CTRL_ADMA32   0x10
#define SDHCI_CTRL_ADMA64   0x18
#define SDHCI_CTRL_ADMA3    0x18
#define SDHCI_CTRL_8BITBUS  0x20
#define SDHCI_CTRL_CD_TEST_INS  0x40
#define SDHCI_CTRL_CD_TEST  0x80

#define SDHCI_POWER_ON  0x01
#define SDHCI_POWER_180 0x0A
#define SDHCI_POWER_300 0x0C
#define SDHCI_POWER_330 0x0E

#define SDHCI_WAKE_ON_INT   0x01
#define SDHCI_WAKE_ON_INSERT    0x02
#define SDHCI_WAKE_ON_REMOVE    0x04

#define SDHCI_DIVIDER_SHIFT 8
#define SDHCI_DIVIDER_HI_SHIFT  6
#define SDHCI_DIV_MASK  0xFF
#define SDHCI_DIV_MASK_LEN  8
#define SDHCI_DIV_HI_MASK   0x0300
#define SDHCI_PROG_CLOCK_MODE   0x0020
#define SDHCI_CLOCK_CARD_EN 0x0004
#define SDHCI_CLOCK_PLL_EN  0x0008
#define SDHCI_CLOCK_INT_STABLE  0x0002
#define SDHCI_CLOCK_INT_EN  0x0001

#define SDHCI_RESET_ALL 0x01
#define SDHCI_RESET_CMD 0x02
#define SDHCI_RESET_DATA    0x04

#define SDHCI_INT_RESPONSE  0x00000001
#define SDHCI_INT_DATA_END  0x00000002
#define SDHCI_INT_BLK_GAP   0x00000004
#define SDHCI_INT_DMA_END   0x00000008
#define SDHCI_INT_SPACE_AVAIL   0x00000010
#define SDHCI_INT_DATA_AVAIL    0x00000020
#define SDHCI_INT_CARD_INSERT   0x00000040
#define SDHCI_INT_CARD_REMOVE   0x00000080
#define SDHCI_INT_CARD_INT  0x00000100
#define SDHCI_INT_RETUNE    0x00001000
#define SDHCI_INT_CQE   0x00004000
#define SDHCI_INT_ERROR 0x00008000
#define SDHCI_INT_TIMEOUT   0x00010000
#define SDHCI_INT_CRC   0x00020000
#define SDHCI_INT_END_BIT   0x00040000
#define SDHCI_INT_INDEX 0x00080000
#define SDHCI_INT_DATA_TIMEOUT  0x00100000
#define SDHCI_INT_DATA_CRC  0x00200000
#define SDHCI_INT_DATA_END_BIT  0x00400000
#define SDHCI_INT_BUS_POWER 0x00800000
#define SDHCI_INT_AUTO_CMD_ERR  0x01000000 
#define SDHCI_INT_ADMA_ERROR    0x02000000
 
#define SDHCI_INT_NORMAL_MASK   0x00007FFF
#define SDHCI_INT_ERROR_MASK    0xFFFF8000
 
#define SDHCI_INT_CMD_MASK  (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_AUTO_CMD_ERR)
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BLK_GAP)
#define SDHCI_INT_ALL_MASK  (LongWord(-1))
 
#define SDHCI_CQE_INT_ERR_MASK  (SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
#define SDHCI_CQE_INT_MASK  (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)

#define SDHCI_AUTO_CMD_TIMEOUT  0x00000002
#define SDHCI_AUTO_CMD_CRC  0x00000004
#define SDHCI_AUTO_CMD_END_BIT  0x00000008
#define SDHCI_AUTO_CMD_INDEX    0x00000010

#define SDHCI_CTRL_UHS_MASK 0x0007
#define SDHCI_CTRL_UHS_SDR12    0x0000
#define SDHCI_CTRL_UHS_SDR25    0x0001
#define SDHCI_CTRL_UHS_SDR50    0x0002
#define SDHCI_CTRL_UHS_SDR104   0x0003
#define SDHCI_CTRL_UHS_DDR50    0x0004
#define SDHCI_CTRL_HS400    0x0005 
#define SDHCI_CTRL_VDD_180  0x0008
#define SDHCI_CTRL_DRV_TYPE_MASK    0x0030
#define SDHCI_CTRL_DRV_TYPE_B   0x0000
#define SDHCI_CTRL_DRV_TYPE_A   0x0010
#define SDHCI_CTRL_DRV_TYPE_C   0x0020
#define SDHCI_CTRL_DRV_TYPE_D   0x0030
#define SDHCI_CTRL_EXEC_TUNING  0x0040
#define SDHCI_CTRL_TUNED_CLK    0x0080
#define SDHCI_CMD23_ENABLE  0x0800
#define SDHCI_CTRL_V4_MODE  0x1000
#define SDHCI_CTRL_64BIT_ADDR   0x2000
#define SDHCI_CTRL_PRESET_VAL_ENABLE    0x8000

#define SDHCI_TIMEOUT_CLK_MASK  0x0000003F
#define SDHCI_TIMEOUT_CLK_SHIFT 0
#define SDHCI_TIMEOUT_CLK_UNIT  0x00000080
#define SDHCI_CLOCK_BASE_MASK   0x00003F00
#define SDHCI_CLOCK_V3_BASE_MASK    0x0000FF00
#define SDHCI_CLOCK_BASE_SHIFT  8
#define SDHCI_CLOCK_BASE_MULTIPLIER 1000000
#define SDHCI_MAX_BLOCK_MASK    0x00030000
#define SDHCI_MAX_BLOCK_SHIFT   16
#define SDHCI_CAN_DO_8BIT   0x00040000
#define SDHCI_CAN_DO_ADMA2  0x00080000
#define SDHCI_CAN_DO_ADMA1  0x00100000
#define SDHCI_CAN_DO_HISPD  0x00200000
#define SDHCI_CAN_DO_SDMA   0x00400000
#define SDHCI_CAN_VDD_330   0x01000000
#define SDHCI_CAN_VDD_300   0x02000000
#define SDHCI_CAN_VDD_180   0x04000000
#define SDHCI_CAN_64BIT_V4  0x08000000
#define SDHCI_CAN_64BIT 0x10000000

#define SDHCI_SUPPORT_SDR50 0x00000001
#define SDHCI_SUPPORT_SDR104    0x00000002
#define SDHCI_SUPPORT_DDR50 0x00000004
#define SDHCI_DRIVER_TYPE_A 0x00000010
#define SDHCI_DRIVER_TYPE_C 0x00000020
#define SDHCI_DRIVER_TYPE_D 0x00000040
#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 
#define SDHCI_USE_SDR50_TUNING  0x00002000
#define SDHCI_RETUNING_MODE_MASK    0x0000C000 
#define SDHCI_CLOCK_MUL_MASK    0x00FF0000 
#define SDHCI_CAN_DO_ADMA3  0x08000000
#define SDHCI_SUPPORT_HS400 0x80000000 

#define SDHCI_MAX_CURRENT_LIMIT 0x000000FF 
#define SDHCI_MAX_CURRENT_330_MASK  0x000000FF 
#define SDHCI_MAX_CURRENT_300_MASK  0x0000FF00 
#define SDHCI_MAX_CURRENT_180_MASK  0x00FF0000 
#define SDHCI_MAX_CURRENT_MULTIPLIER    4

#define SDHCI_PRESET_DRV_MASK   0x0000C000 
#define SDHCI_PRESET_DRV_SHIFT  14
#define SDHCI_PRESET_CLKGEN_SEL 1 << 10 
#define SDHCI_PRESET_SDCLK_FREQ_MASK    0x000003FF 

#define SDHCI_VENDOR_VER_MASK   0xFF00
#define SDHCI_VENDOR_VER_SHIFT  8
#define SDHCI_SPEC_VER_MASK 0x00FF
#define SDHCI_SPEC_VER_SHIFT    0
#define SDHCI_SPEC_100  0
#define SDHCI_SPEC_200  1
#define SDHCI_SPEC_300  2
#define SDHCI_SPEC_400  3
#define SDHCI_SPEC_410  4
#define SDHCI_SPEC_420  5

#define SDHCI_MAX_CLOCK_DIV_SPEC_200    256
#define SDHCI_MAX_CLOCK_DIV_SPEC_300    2046

#define SDHCI_QUIRK_CLOCK_BEFORE_RESET  (1 << 0) 
#define SDHCI_QUIRK_FORCE_DMA   (1 << 1) 
#define SDHCI_QUIRK_NO_CARD_NO_RESET    (1 << 2) 
#define SDHCI_QUIRK_SINGLE_POWER_WRITE  (1 << 3) 
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS   (1 << 4) 
#define SDHCI_QUIRK_BROKEN_DMA  (1 << 5) 
#define SDHCI_QUIRK_BROKEN_ADMA (1 << 6) 
#define SDHCI_QUIRK_32BIT_DMA_ADDR  (1 << 7) 
#define SDHCI_QUIRK_32BIT_DMA_SIZE  (1 << 8) 
#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9) 
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10) 
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11) 
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL  (1 << 12) 
#define SDHCI_QUIRK_BROKEN_SMALL_PIO    (1 << 13) 
#define SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14) 
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION   (1 << 15) 
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT  (1 << 16) 
#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18) 
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048   (1 << 20) 
#define SDHCI_QUIRK_NO_MULTIBLOCK   (1 << 21) 
#define SDHCI_QUIRK_FORCE_1_BIT_DATA    (1 << 22) 
#define SDHCI_QUIRK_DELAY_AFTER_POWER   (1 << 23) 
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24) 
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN   (1 << 25) 
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC   (1 << 26) 
#define SDHCI_QUIRK_MISSING_CAPS    (1 << 27) 
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12  (1 << 28) 
#define SDHCI_QUIRK_NO_HISPD_BIT    (1 << 29) 
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC    (1 << 30) 
#define SDHCI_QUIRK_UNSTABLE_RO_DETECT  (1 << 31) 

#define SDHCI_QUIRK2_HOST_OFF_CARD_ON   (1 << 0)
#define SDHCI_QUIRK2_HOST_NO_CMD23  (1 << 1)
#define SDHCI_QUIRK2_NO_1_8_V   (1 << 2) 
#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN    (1 << 3)
#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON   (1 << 4)
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL    (1 << 5) 
#define SDHCI_QUIRK2_BROKEN_HS200   (1 << 6) 
#define SDHCI_QUIRK2_BROKEN_DDR50   (1 << 7) 
#define SDHCI_QUIRK2_STOP_WITH_TC   (1 << 8) 
#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA  (1 << 9) 
#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD  (1 << 10) 
#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400   (1 << 11) 
#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12) 
#define SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13) 
#define SDHCI_QUIRK2_ACMD23_BROKEN  (1 << 14) 
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN  (1 << 15) 
#define SDHCI_QUIRK2_RSP_136_HAS_CRC    (1 << 16) 
#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17) 
#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT  (1 << 18) 

#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 
#define SDHCI_DEFAULT_BOUNDARY_ARG  7 

#define SDHCI_ADMA2_32_DESC_SIZE    8

#define SDHCI_ADMA2_ALIGN   4
#define SDHCI_ADMA2_MASK    (SDHCI_ADMA2_ALIGN - 1)

#define SDHCI_ADMA2_DESC_ALIGN  8

#define SDHCI_ADMA2_64_DESC_SIZE    12
#define SDHCI_ADMA2_64_DESC_V4_SIZE 16 

#define SDHCI_ADMA2_DESC_ATTR_VALID 0x01
#define SDHCI_ADMA2_DESC_ATTR_END   0x02
#define SDHCI_ADMA2_DESC_ATTR_INT   0x04
#define SDHCI_ADMA2_DESC_ATTR_NOP   0x00
#define SDHCI_ADMA2_DESC_ATTR_TRAN  0x20
#define SDHCI_ADMA2_DESC_ATTR_LINK  0x30
 
#define SDHCI_ADMA2_DESC_TRAN_VALID SDHCI_ADMA2_DESC_ATTR_TRAN | SDHCI_ADMA2_DESC_ATTR_VALID 
#define SDHCI_ADMA2_DESC_NOP_END_VALID  SDHCI_ADMA2_DESC_ATTR_NOP | SDHCI_ADMA2_DESC_ATTR_END | SDHCI_ADMA2_DESC_ATTR_VALID 
#define SDHCI_ADMA2_DESC_END    SDHCI_ADMA2_DESC_ATTR_END 

#define SDHCI_MAX_SEGS  128

#define SDHCI_TIMEOUT_VALUE 0x0E


typedef struct _MMC_DATA MMC_DATA;
typedef struct _MMC_COMMAND MMC_COMMAND;
struct _MMC_COMMAND
{
    // Command Properties
    uint16_t command;
    uint32_t argument;
    uint32_t responsetype;
    uint32_t response[4];
    uint32_t status;
    MMC_DATA *data;
    uint32_t timeout; 
    // Host Properties
    BOOL datacompleted;
    BOOL busycompleted;
    BOOL tuningcompleted;
    BOOL commandcompleted;
};

struct _MMC_DATA
{
    // Data Properties
    void *data;
    uint32_t flags;
    uint32_t blocksize;
    uint32_t blockcount;
    // Host Properties
    uint32_t blockoffset;
    uint32_t blocksremaining;
    uint32_t bytesremaining;
    uint32_t bytestransfered;
};

typedef struct _MMC_CARD_IDENTIFICATION_DATA
{
    // Card Values
    uint8_t manufacturerid;
    uint16_t oemid;
    char productname[8]; 
    uint8_t productrevision;
    uint8_t hardwarerevision;
    uint8_t firmwarerevision;
    uint32_t productserialnumber;
    uint8_t manufacturingmonth;
    uint16_t manufacturingyear;
    uint8_t crc; 
} MMC_CARD_IDENTIFICATION_DATA;

typedef struct _MMC_CARD_SPECIFIC_SD_ERASE_DATA
{
    BOOL eraseblockenable; 
    uint8_t sectorsize; 
} MMC_CARD_SPECIFIC_SD_ERASE_DATA;
 
typedef struct _MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA
{
    uint8_t sectorsize; 
    uint8_t erasegroupsize; 
} MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA;
 
typedef struct _MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA
{
    uint8_t erasegroupsize; 
    uint8_t erasegroupmultiplier; 
} MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA;
 
typedef union _MMC_CARD_SPECIFIC_ERASE_DATA
{
    struct {
     MMC_CARD_SPECIFIC_MM_C22_ERASE_DATA MMC22;
    };
    struct {
     MMC_CARD_SPECIFIC_MM_C31_ERASE_DATA MMC31;
    };
    struct {
     MMC_CARD_SPECIFIC_SD_ERASE_DATA SD;
    };
} MMC_CARD_SPECIFIC_ERASE_DATA;
 
typedef struct _MMC_CARD_SPECIFIC_DATA MMC_CARD_SPECIFIC_DATA;
struct _MMC_CARD_SPECIFIC_DATA
{
    // Card Values
    uint8_t csdstructure; 
    uint8_t specversion; 
    //uint8_t taac; // Data read access-time-1
    //uint8_t nsac; // Data read access-time-2 in CLK cycles (NSAC*100)
    //uint8_t transferspeed; // Max. data transfer rate
    uint16_t ccc; 
    uint8_t readblocklength; 
    BOOL readblockpartial; 
    BOOL writeblockmisalign; 
    BOOL readblockmisalign; 
    BOOL dsrimplemented; 
    uint16_t devicesize; 
    uint8_t vddreadcurrentmin; 
    uint8_t vddreadcurrentmax; 
    uint8_t vddwritecurrentmin; 
    uint8_t vddwritecurrentmax; 
    uint8_t devicesizemultiplier; 
    MMC_CARD_SPECIFIC_ERASE_DATA erase; 
    uint8_t writeprotectgroupsize; 
    BOOL writeprotectgroupenable; 
    uint8_t defaultecc; 
    uint8_t readtowritefactor; 
    uint8_t writeblocklength; 
    BOOL writeblockpartial; 
    BOOL contentprotectapplication; 
    uint8_t fileformatgroup; 
    BOOL copyflag; 
    BOOL permanentwriteprotect; 
    BOOL temporarywriteprotect; 
    uint8_t fileformat; 
    uint8_t ecc; 
    uint8_t crc; 
    // Calculated Values
    uint32_t dataaccesstime; 
    uint16_t dataaccessclocks; 
    uint32_t datatransferrate; 
    uint32_t erasesize; 
    uint32_t blocksize; 
    uint32_t blockcount; 
    uint32_t blockshift; 
};
 
typedef struct _MMC_EXTENDED_CARD_SPECIFIC_DATA MMC_EXTENDED_CARD_SPECIFIC_DATA;
struct _MMC_EXTENDED_CARD_SPECIFIC_DATA
{
    // Card Values
    uint8_t revision; 
    uint8_t cachecontrol; 
    uint8_t poweroffnotification; 
    uint8_t partitionsupport; 
    uint8_t hardwareresetfunction; 
    uint8_t writereliabilityparameter; 
    uint8_t rpmbsizemult; 
    uint8_t erasegroupdef; 
    uint8_t partconfig; 
    uint8_t erasedmemorycontent; 
    uint8_t strobesupport; 
    uint8_t csdstructure; 
    uint8_t cardtype; 
    uint8_t driverstrength; 
    uint8_t outofinterrupttime; 
    uint8_t sectorcount[4]; 
    uint8_t satimeout; 
    uint8_t hcerasegapsize; 
    uint8_t reliablesectors; 
    uint8_t erasetimeoutmult; 
    uint8_t hcerasegrpsize; 
    uint8_t sectrimmult; 
    uint8_t secerasemult; 
    uint8_t secfeaturesupport; 
    uint8_t trimmult; 
    uint8_t powerclass52mhz195; 
    uint8_t powerclass26mhz195; 
    uint8_t powerclass52mhz360; 
    uint8_t powerclass26mhz360; 
    uint8_t powerclass200mhz195; 
    uint8_t powerclass200mhz360; 
    uint8_t powerclassddr52mhz195; 
    uint8_t powerclassddr52mhz360; 
    uint8_t powerclassddr200mhz360; 
    uint8_t bkopsstatus; 
    uint8_t firmwareversion[MMC_FIRMWARE_VERSION_LEN]; 
    uint8_t preendoflifeinfo; 
    uint8_t devicelifetimeestimatea; 
    uint8_t devicelifetimeestimateb; 
    uint8_t maxpackedwrites; 
    uint8_t maxpackedreads; 
    // Calculated Values
    uint32_t sectors;
    uint32_t sleepawaketime; 
    uint32_t partitionswitchtime; 
    uint32_t genericcmd6time; 
    uint32_t powerofflongtime; 
    uint32_t hcerasesize; 
    uint32_t hcerasetimeout; 
    uint32_t datasectorsize; 
    uint32_t datatagunitsize;
    uint32_t hsmaxrate; 
    uint32_t hs200maxrate; 
    uint32_t availabletypes;
    uint64_t bootpartitionsize; 
    uint64_t enhancedareaoffset; 
    uint64_t enhancedareasize; 
    uint32_t cachesize; 
    BOOL partitionsettingcompleted; 
    uint32_t trimtimeout; 
    uint64_t partitionsizes[MMC_NUM_GP_PARTITION]; 
    uint32_t bootreadonlysupport; 
    BOOL bootreadonlylockable;
    BOOL fieldfirmwareupdate; 
    BOOL commandqueuesupport; 
    uint32_t commandqueuedepth; 
    BOOL backgroundoperations; 
    BOOL manualbkopsenable; 
    BOOL autobkopsenable; 
    BOOL hpi; 
    BOOL hpienable; 
    uint32_t hpicommand; 
    uint64_t rpmbsize; 
    BOOL enhancedrpmbsupport;
    uint8_t erasedbyte; 
    uint32_t featuresupport; 
};

typedef struct _SD_STATUS_DATA SD_STATUS_DATA;
struct _SD_STATUS_DATA
{
    // Card Values
    uint8_t buswidth; 
    BOOL securedmode; 
    uint16_t cardtype; 
    uint32_t protectedsize; 
    uint8_t speedclass; 
    uint8_t performancemove; 
    uint16_t erasesize; 
    uint8_t erasetimeout; 
    uint8_t eraseoffset; 
    uint8_t uhsspeedgrade; 
    // Calculated Values
    uint8_t allocationunitsize; 
    uint8_t uhsallocationunitsize; 
};

typedef struct _SD_SWITCH_DATA SD_SWITCH_DATA;
struct _SD_SWITCH_DATA
{
    // Card Values
    uint16_t maximumcurrent; 
    uint16_t group6support; 
    uint16_t group5support; 
    uint16_t group4support; 
    uint16_t group3support; 
    uint16_t group2support; 
    uint16_t group1support; 
    uint8_t group6selection; 
    uint8_t group5selection; 
    uint8_t group4selection; 
    uint8_t group3selection; 
    uint8_t group2selection; 
    uint8_t group1selection; 
    uint8_t structureversion; 
    uint16_t group6busystatus; 
    uint16_t group5busystatus; 
    uint16_t group4busystatus; 
    uint16_t group3busystatus; 
    uint16_t group2busystatus; 
    uint16_t group1busystatus; 
};

typedef struct _SD_CONFIGURATION_DATA SD_CONFIGURATION_DATA;
struct _SD_CONFIGURATION_DATA
{
    // Card Values
    uint8_t scrstructure; 
    uint8_t specversion; 
    uint8_t dataaftererase; 
    uint8_t security; 
    uint8_t buswidths; 
    BOOL specversion3; 
    uint8_t extendedsecurity; 
    BOOL specversion4; 
    uint8_t commandsupport; 
    // Calculated Values
    uint8_t erasedbyte; 
};

typedef struct _MMC_DEVICE MMC_DEVICE;
typedef struct _SDIO_CCCR SDIO_CCCR; 
typedef struct _SDIO_CIS SDIO_CIS; 
typedef struct _SDIO_TUPLE SDIO_TUPLE; 
typedef struct _SDIO_FUNCTION SDIO_FUNCTION; 

typedef uint32_t STDCALL (*mmc_enumerate_cb)(MMC_DEVICE *mmc, void *data);
typedef uint32_t STDCALL (*mmc_notification_cb)(DEVICE *device, void *data, uint32_t notification);

typedef uint32_t STDCALL (*mmc_device_initialize_proc)(MMC_DEVICE *mmc);
typedef uint32_t STDCALL (*mmc_device_deinitialize_proc)(MMC_DEVICE *mmc);
typedef uint32_t STDCALL (*mmc_device_get_card_detect_proc)(MMC_DEVICE *mmc);
typedef uint32_t STDCALL (*mmc_device_get_write_protect_proc)(MMC_DEVICE *mmc);
typedef uint32_t STDCALL (*mmc_device_send_command_proc)(MMC_DEVICE *mmc, MMC_COMMAND *command);
typedef uint32_t STDCALL (*mmc_device_set_ios_proc)(MMC_DEVICE *mmc);
 
struct _MMC_DEVICE
{
    // Device Properties
    DEVICE device; 
    // MMC Properties
    uint32_t mmcid; 
    uint32_t mmcstate; 
    mmc_device_initialize_proc deviceinitialize; 
    mmc_device_deinitialize_proc devicedeinitialize; 
    mmc_device_get_card_detect_proc devicegetcarddetect; 
    mmc_device_get_write_protect_proc devicegetwriteprotect; 
    mmc_device_send_command_proc devicesendcommand; 
    mmc_device_set_ios_proc devicesetios; 
    // Statistics Properties
    uint32_t commandcount;
    uint32_t commanderrors;
    // Driver Properties
    MUTEX_HANDLE lock; 
    uint32_t version;
    uint32_t clock;
    uint32_t timing;
    uint32_t buswidth;
    uint32_t drivertype;
    uint32_t signalvoltage;
    uint32_t voltages;
    uint32_t capabilities;
    uint32_t capabilities2;
    uint32_t erasesize; 
    uint32_t eraseshift;
    uint32_t eraseargument;
    uint32_t preferrederasesize; 
    LONGBOOL enhancedstrobe;
    // Register Properties
    uint32_t interfacecondition; 
    uint32_t operationcondition; 
    uint32_t relativecardaddress; 
    uint32_t cardspecific[4]; 
    uint32_t cardidentification[4]; 
    uint8_t *extendedcardspecific; 
    uint32_t cardstatus; 
    uint32_t driverstage; 
    uint32_t sdstatus[16]; 
    uint32_t sdswitch[16]; 
    uint32_t sdconfiguration[2]; 
    // Configuration Properties
    MMC_CARD_SPECIFIC_DATA cardspecificdata;
    MMC_CARD_IDENTIFICATION_DATA cardidentificationdata;
    MMC_EXTENDED_CARD_SPECIFIC_DATA extendedcardspecificdata;
    SD_STATUS_DATA sdstatusdata;
    SD_SWITCH_DATA sdswitchdata;
    SD_CONFIGURATION_DATA sdconfigurationdata;
    // SDIO Properties
    SDIO_CCCR *cccr; 
    SDIO_CIS *cis; 
    SDIO_TUPLE *tuples; 
    uint32_t sdiocount; 
    SDIO_FUNCTION *sdiofunctions[SDIO_MAX_FUNCTIONS]; 
    SDIO_FUNCTION *sdiointerruptfunction; 
    // Storage Properties
    STORAGE_DEVICE *storage; 
    // Internal Properties
    MMC_DEVICE *prev; 
    MMC_DEVICE *next; 
};


struct _SDIO_CCCR
{
    // SDIO Properties
    uint8_t cccrversion; 
    uint8_t sdioversion; 
    uint8_t sdversion; 
    uint8_t cccrcapabilities; 
    uint8_t cccrpowercontrol; 
    uint8_t cccrbusspeed; 
    uint8_t cccruhssupport; 
    uint8_t cccrdriverstrength; 
    // Driver Properties
    BOOL multiblock; 
    BOOL lowspeed; 
    BOOL widebus; 
    BOOL highpower; 
    BOOL highspeed; 
};

struct _SDIO_CIS
{
    uint16_t vendor;
    uint16_t device;
    uint16_t blocksize;
    uint32_t maxclock;
};

struct _SDIO_TUPLE
{
    SDIO_TUPLE *next;
    uint8_t code;
    uint8_t size;
    uint8_t data[];
};

typedef struct _SDIO_DRIVER SDIO_DRIVER; 

typedef void STDCALL (*sdio_interrupt_handler)(SDIO_FUNCTION *func);

typedef uint32_t STDCALL (*sdio_function_enumerate_cb)(SDIO_FUNCTION *func, void *data);
 
struct _SDIO_FUNCTION
{
    // Function Properties
    uint32_t sdiostate; 
    uint32_t sdiostatus; 
    MMC_DEVICE *mmc; 
    uint32_t number; 
    uint8_t classid; 
    uint16_t vendorid; 
    uint16_t deviceid; 
    uint32_t blocksize; 
    uint32_t maxblocksize; 
    uint32_t enabletimeout; 
    sdio_interrupt_handler handler; 
    void *dmabuffer; 
    SDIO_TUPLE *tuples; 
    SDIO_DRIVER *driver; 
    void *driverdata; 
};


typedef uint32_t STDCALL (*sdio_driver_enumerate_cb)(SDIO_DRIVER *driver, void *data);

typedef uint32_t STDCALL (*sdio_driver_bind_proc)(MMC_DEVICE *mmc, SDIO_FUNCTION *func);
typedef uint32_t STDCALL (*sdio_driver_unbind_proc)(MMC_DEVICE *mmc, SDIO_FUNCTION *func);
 
struct _SDIO_DRIVER
{
    // Driver Properties
    DRIVER driver; 
    // SDIO Properties
    sdio_driver_bind_proc driverbind; 
    sdio_driver_unbind_proc driverunbind; 
    // Interface Properties
    MUTEX_HANDLE lock; 
    // Internal Properties
    SDIO_DRIVER *prev; 
    SDIO_DRIVER *next; 
};

typedef struct _SDHCI_ADMA2_DESCRIPTOR32 SDHCI_ADMA2_DESCRIPTOR32;
struct _SDHCI_ADMA2_DESCRIPTOR32
{
    uint16_t command;
    uint16_t len;
    uint32_t address;
} PACKED;
 

typedef struct _SDHCI_ADMA2_DESCRIPTOR64 SDHCI_ADMA2_DESCRIPTOR64;
struct _SDHCI_ADMA2_DESCRIPTOR64
{
    uint16_t command;
    uint16_t len;
    uint32_t addresslow;
    uint32_t addresshigh;
} PACKED;
 
 
typedef struct _SDHCI_ADMA2_DESCRIPTOR64_V4 SDHCI_ADMA2_DESCRIPTOR64_V4;
struct _SDHCI_ADMA2_DESCRIPTOR64_V4
{
    uint16_t command;
    uint16_t len;
    uint32_t addresslow;
    uint32_t addresshigh;
    uint32_t reserved;
} PACKED;

typedef struct _SDHCI_HOST SDHCI_HOST;

typedef uint32_t STDCALL (*sdhci_enumerate_cb)(SDHCI_HOST *sdhci, void *data);
typedef uint32_t STDCALL (*sdhci_notification_cb)(DEVICE *device, void *data, uint32_t notification);

typedef uint32_t STDCALL (*sdhci_host_start_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_stop_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_lock_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_unlock_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_signal_proc)(SDHCI_HOST *sdhci, SEMAPHORE_HANDLE semaphore);
typedef uint8_t STDCALL (*sdhci_host_read_byte_proc)(SDHCI_HOST *sdhci, uint32_t reg);
typedef uint16_t STDCALL (*sdhci_host_read_word_proc)(SDHCI_HOST *sdhci, uint32_t reg);
typedef uint32_t STDCALL (*sdhci_host_read_long_proc)(SDHCI_HOST *sdhci, uint32_t reg);
typedef void STDCALL (*sdhci_host_write_byte_proc)(SDHCI_HOST *sdhci, uint32_t reg, uint8_t value);
typedef void STDCALL (*sdhci_host_write_word_proc)(SDHCI_HOST *sdhci, uint32_t reg, uint16_t value);
typedef void STDCALL (*sdhci_host_write_long_proc)(SDHCI_HOST *sdhci, uint32_t reg, uint32_t value);
typedef uint32_t STDCALL (*sdhci_host_reset_proc)(SDHCI_HOST *sdhci, uint8_t mask);
typedef uint32_t STDCALL (*sdhci_host_hardware_reset_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_set_power_proc)(SDHCI_HOST *sdhci, uint16_t power);
typedef uint32_t STDCALL (*sdhci_host_set_clock_proc)(SDHCI_HOST *sdhci, uint32_t clock);
typedef uint32_t STDCALL (*sdhci_host_set_timing_proc)(SDHCI_HOST *sdhci, uint32_t timing);
typedef uint32_t STDCALL (*sdhci_host_set_buswidth_proc)(SDHCI_HOST *sdhci, uint32_t buswidth);
typedef uint32_t STDCALL (*sdhci_host_set_clock_divider_proc)(SDHCI_HOST *sdhci, int index, uint32_t divider);
typedef uint32_t STDCALL (*sdhci_host_set_control_register_proc)(SDHCI_HOST *sdhci);
typedef uint32_t STDCALL (*sdhci_host_prepare_dma_proc)(SDHCI_HOST *sdhci, MMC_COMMAND *command);
typedef uint32_t STDCALL (*sdhci_host_start_dma_proc)(SDHCI_HOST *sdhci, MMC_COMMAND *command);
typedef uint32_t STDCALL (*sdhci_host_stop_dma_proc)(SDHCI_HOST *sdhci, MMC_COMMAND *command);
typedef uint32_t STDCALL (*sdhci_host_setup_card_irq_proc)(SDHCI_HOST *sdhci, LONGBOOL enable);
typedef uint32_t STDCALL (*sdhci_host_complete_card_irq_proc)(SDHCI_HOST *sdhci);
 
struct _SDHCI_HOST
{
    // Device Properties
    DEVICE device; 
    // SDHCI Properties
    uint32_t sdhciid; 
    uint32_t sdhcistate; 
    sdhci_host_start_proc hoststart; 
    sdhci_host_stop_proc hoststop; 
    sdhci_host_lock_proc hostlock; 
    sdhci_host_unlock_proc hostunlock; 
    sdhci_host_signal_proc hostsignal; 
    sdhci_host_read_byte_proc hostreadbyte; 
    sdhci_host_read_word_proc hostreadword; 
    sdhci_host_read_long_proc hostreadlong; 
    sdhci_host_write_byte_proc hostwritebyte; 
    sdhci_host_write_word_proc hostwriteword; 
    sdhci_host_write_long_proc hostwritelong; 
    sdhci_host_reset_proc hostreset; 
    sdhci_host_hardware_reset_proc hosthardwarereset; 
    sdhci_host_set_power_proc hostsetpower; 
    sdhci_host_set_clock_proc hostsetclock; 
    sdhci_host_set_timing_proc hostsettiming; 
    sdhci_host_set_buswidth_proc hostsetbuswidth; 
    sdhci_host_set_clock_divider_proc hostsetclockdivider;
    sdhci_host_set_control_register_proc hostsetcontrolregister;
    sdhci_host_prepare_dma_proc hostpreparedma; 
    sdhci_host_start_dma_proc hoststartdma; 
    sdhci_host_stop_dma_proc hoststopdma; 
    sdhci_host_setup_card_irq_proc hostsetupcardirq; 
    sdhci_host_complete_card_irq_proc hostcompletecardirq; 
    mmc_device_initialize_proc deviceinitialize; 
    mmc_device_deinitialize_proc devicedeinitialize; 
    mmc_device_get_card_detect_proc devicegetcarddetect; 
    mmc_device_get_write_protect_proc devicegetwriteprotect; 
    mmc_device_send_command_proc devicesendcommand; 
    mmc_device_set_ios_proc devicesetios; 
    // Driver Properties
    SPIN_HANDLE spin; 
    MUTEX_HANDLE lock; 
    void *address; 
    uint32_t version; 
    uint32_t quirks; 
    uint32_t quirks2; 
    uint32_t clock; 
    uint32_t power; 
    uint32_t timing; 
    uint32_t buswidth; 
    uint32_t interrupts; 
    uint32_t voltages; 
    uint32_t capabilities; 
    uint32_t capabilities2; 
    uint32_t timeoutfrequency; 
    uint32_t minimumfrequency; 
    uint32_t maximumfrequency; 
    uint32_t maximumblocksize; 
    uint32_t maximumblockcount; 
    uint32_t maximumrequestsize; 
    uint32_t maximumbusytimeout; 
    uint32_t minimumdmasize; 
    uint32_t maximumpioblocks; 
    LONGBOOL presetenabled; 
    LONGBOOL cardirqenabled; 
    WORKER_HANDLE cardirqworker; 
    MMC_DEVICE *cardirqdevice; 
    uint32_t cardirqcount; 
    MMC_COMMAND *command; 
    SEMAPHORE_HANDLE wait; 
    LONGBOOL usedma; 
    DMA_DATA dmadata; 
    SEMAPHORE_HANDLE dmawait; 
    uint32_t dmaslave; 
    void *dmabuffer; 
    uint32_t dmadirection; 
    uint32_t sdmaboundary; 
    SDHCI_ADMA2_DESCRIPTOR64_V4 *admatable; 
    void *admabuffer; 
    uint32_t admatablesize; 
    uint32_t admatablecount; 
    uint32_t admabuffersize; 
    uint32_t admadescriptorsize; 
    // Configuration Properties
    uint32_t presetvoltages; 
    uint32_t presetcapabilities; 
    uint32_t presetcapabilities2; 
    uint32_t clockminimum; 
    uint32_t clockmaximum; 
    uint32_t driverstageregister; 
    LONGBOOL enablev4mode; 
    // Statistics Properties
    uint32_t requestcount; 
    uint32_t requesterrors; 
    uint32_t datarequestcount; 
    uint32_t commandrequestcount; 
    uint32_t piodatatransfercount; 
    uint32_t dmadatatransfercount; 
    uint32_t interruptcount; 
    uint32_t datainterruptcount; 
    uint32_t commandinterruptcount; 
    // Internal Properties
    SDHCI_HOST *prev; 
    SDHCI_HOST *next; 
};

uint32_t STDCALL mmc_start(void);
uint32_t STDCALL mmc_stop(void);
 
void STDCALL mmc_async_start(SDHCI_HOST *sdhci);

uint32_t STDCALL mmc_device_read_blocks(MMC_DEVICE *mmc, int64_t start, int64_t count, void *buffer);
uint32_t STDCALL mmc_device_write_blocks(MMC_DEVICE *mmc, int64_t start, int64_t count, void *buffer);
 
uint32_t STDCALL mmc_device_erase_blocks(MMC_DEVICE *mmc, int64_t start, int64_t count);
 
uint32_t STDCALL mmc_device_go_idle(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_set_clock(MMC_DEVICE *mmc, uint32_t clock);
uint32_t STDCALL mmc_device_set_timing(MMC_DEVICE *mmc, uint32_t timing);
uint32_t STDCALL mmc_device_set_bus_width(MMC_DEVICE *mmc, uint32_t width);
 
uint32_t STDCALL mmc_device_set_block_length(MMC_DEVICE *mmc, uint32_t length);
uint32_t STDCALL mmc_device_set_block_count(MMC_DEVICE *mmc, uint32_t count, BOOL relative);
uint32_t STDCALL mmc_device_set_driver_stage(MMC_DEVICE *mmc, uint32_t driverstage);
 
uint32_t STDCALL mmc_device_stop_transmission(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_select_card(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_deselect_card(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_device_switch(MMC_DEVICE *mmc, uint8_t setting, uint8_t index, uint8_t value, uint32_t timeout);

uint32_t STDCALL mmc_device_switch_ex(MMC_DEVICE *mmc, uint8_t setting, uint8_t index, uint8_t value, uint32_t timeout, uint32_t timing, BOOL sendstatus, BOOL retrycrcerror);

uint32_t STDCALL mmc_device_poll_for_busy(MMC_DEVICE *mmc, uint32_t timeout, uint32_t command);

uint32_t STDCALL mmc_device_poll_for_busy_ex(MMC_DEVICE *mmc, uint32_t timeout, uint32_t command, BOOL sendstatus, BOOL retrycrcerror);
 
uint32_t STDCALL mmc_device_send_card_status(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_send_operation_condition(MMC_DEVICE *mmc, BOOL probe);
 
uint32_t STDCALL mmc_device_send_card_specific(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_device_decode_card_specific(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_send_card_identification(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_send_all_card_identification(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_device_decode_card_identification(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_get_extended_card_specific(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_send_extended_card_specific(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_decode_extended_card_specific(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_set_relative_address(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_spi_set_crc(MMC_DEVICE *mmc, BOOL enable);
uint32_t STDCALL mmc_device_spi_read_operation_condition(MMC_DEVICE *mmc, BOOL highcapacity);
 
uint32_t STDCALL mmc_device_insert(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_remove(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_initialize(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_deinitialize(MMC_DEVICE *mmc);
 
uint32_t STDCALL mmc_device_get_card_detect(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_get_write_protect(MMC_DEVICE *mmc);
uint32_t STDCALL mmc_device_send_command(MMC_DEVICE *mmc, MMC_COMMAND *command);
uint32_t STDCALL mmc_device_set_ios(MMC_DEVICE *mmc);

MMC_DEVICE * STDCALL mmc_device_create(void);

MMC_DEVICE * STDCALL mmc_device_create_ex(uint32_t size);

uint32_t STDCALL mmc_device_destroy(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_device_register(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_device_deregister(MMC_DEVICE *mmc);
 
MMC_DEVICE * STDCALL mmc_device_find(uint32_t mmcid);

MMC_DEVICE * STDCALL mmc_device_find_by_device(DEVICE *device);
MMC_DEVICE * STDCALL mmc_device_find_by_name(const char *name);
MMC_DEVICE * STDCALL mmc_device_find_by_description(const char *description);
uint32_t STDCALL mmc_device_enumerate(mmc_enumerate_cb callback, void *data);
 
uint32_t STDCALL mmc_device_notification(MMC_DEVICE *mmc, mmc_notification_cb callback, void *data, uint32_t notification, uint32_t flags);

uint32_t STDCALL sd_device_switch(MMC_DEVICE *mmc, int mode, int group, uint8_t value, void *buffer);
 
uint32_t STDCALL sd_device_switch_highspeed(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_set_bus_width(MMC_DEVICE *mmc, uint32_t width);
 
uint32_t STDCALL sd_device_send_interface_condition(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_operation_condition(MMC_DEVICE *mmc, BOOL probe);
 
uint32_t STDCALL sd_device_get_card_specific(MMC_DEVICE *mmc);

uint32_t STDCALL sd_device_decode_card_specific(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_get_card_identification(MMC_DEVICE *mmc);

uint32_t STDCALL sd_device_decode_card_identification(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_sd_status(MMC_DEVICE *mmc);
uint32_t STDCALL sd_device_decode_sd_status(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_sd_switch(MMC_DEVICE *mmc);
uint32_t STDCALL sd_device_decode_sd_switch(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_sd_configuration(MMC_DEVICE *mmc);

uint32_t STDCALL sd_device_decode_sd_configuration(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_relative_address(MMC_DEVICE *mmc);
 
uint32_t STDCALL sd_device_send_application_command(MMC_DEVICE *mmc, MMC_COMMAND *command);

uint32_t STDCALL sdio_device_reset(MMC_DEVICE *mmc);
 
uint32_t STDCALL sdio_device_enable_wide_bus(MMC_DEVICE *mmc);
uint32_t STDCALL sdio_device_disable_wide_bus(MMC_DEVICE *mmc);
 
uint32_t STDCALL sdio_device_enable_highspeed(MMC_DEVICE *mmc);
uint32_t STDCALL sdio_device_switch_highspeed(MMC_DEVICE *mmc, BOOL enable);
 
uint32_t STDCALL sdio_device_send_operation_condition(MMC_DEVICE *mmc, BOOL probe);
 
uint32_t STDCALL sdio_device_read_write_direct(MMC_DEVICE *mmc, BOOL write, uint32_t operation, uint32_t address, uint8_t input, uint8_t *output);
uint32_t STDCALL sdio_device_read_write_extended(MMC_DEVICE *mmc, BOOL write, uint32_t operation, uint32_t address, BOOL increment, void *buffer, uint32_t blockcount, uint32_t blocksize);

uint32_t STDCALL sdio_device_read_byte(MMC_DEVICE *mmc, uint32_t address, uint8_t *output);

uint32_t STDCALL sdio_device_write_byte(MMC_DEVICE *mmc, uint32_t address, uint8_t input);
 
uint32_t STDCALL sdio_device_read_cccr(MMC_DEVICE *mmc);
 
uint32_t STDCALL sdio_device_read_fbr(SDIO_FUNCTION *func);
 
uint32_t STDCALL sdio_device_read_cis(MMC_DEVICE *mmc, SDIO_FUNCTION *func);
 
uint32_t STDCALL sdio_device_read_common_cis(MMC_DEVICE *mmc);
uint32_t STDCALL sdio_device_read_function_cis(SDIO_FUNCTION *func);
 
uint32_t STDCALL sdio_device_process_interrupts(MMC_DEVICE *mmc);
uint32_t STDCALL sdio_device_register_interrupt(MMC_DEVICE *mmc, SDIO_FUNCTION *func, sdio_interrupt_handler handler);
uint32_t STDCALL sdio_device_deregister_interrupt(MMC_DEVICE *mmc, SDIO_FUNCTION *func);

uint32_t STDCALL sdio_device_bind_functions(MMC_DEVICE *mmc);

uint32_t STDCALL sdio_device_unbind_functions(MMC_DEVICE *mmc, SDIO_DRIVER *driver);

SDIO_FUNCTION * STDCALL sdio_function_allocate(MMC_DEVICE *mmc, uint32_t number);
uint32_t STDCALL sdio_function_release(SDIO_FUNCTION *func);
 
SDIO_FUNCTION * STDCALL sdio_function_find(MMC_DEVICE *mmc, uint32_t number);
SDIO_FUNCTION * STDCALL sdio_function_find_by_id(MMC_DEVICE *mmc, uint16_t vendorid, uint16_t deviceid);
uint32_t STDCALL sdio_function_enumerate(MMC_DEVICE *mmc, sdio_function_enumerate_cb callback, void *data);
 
uint32_t STDCALL sdio_function_bind(SDIO_FUNCTION *func, SDIO_DRIVER *driver);
uint32_t STDCALL sdio_function_unbind(SDIO_FUNCTION *func, SDIO_DRIVER *driver);
 
uint32_t STDCALL sdio_function_enable(SDIO_FUNCTION *func);
uint32_t STDCALL sdio_function_disable(SDIO_FUNCTION *func);
 
uint32_t STDCALL sdio_function_set_block_size(SDIO_FUNCTION *func, uint32_t blocksize);

uint32_t STDCALL sdio_function_read_write_extended(SDIO_FUNCTION *func, BOOL write, uint32_t address, BOOL increment, void *buffer, uint32_t size);

uint32_t STDCALL sdio_function_read(SDIO_FUNCTION *func, uint32_t address, void *buffer, uint32_t size);

uint32_t STDCALL sdio_function_write(SDIO_FUNCTION *func, uint32_t address, void *buffer, uint32_t size);

uint32_t STDCALL sdio_function_read_byte(SDIO_FUNCTION *func, uint32_t address, uint8_t *output);

uint32_t STDCALL sdio_function_write_byte(SDIO_FUNCTION *func, uint32_t address, uint8_t input);

uint32_t STDCALL sdio_function_write_read_byte(SDIO_FUNCTION *func, uint32_t address, uint8_t input, uint8_t *output);

uint32_t STDCALL sdio_function_read_word(SDIO_FUNCTION *func, uint32_t address, uint16_t *output);

uint32_t STDCALL sdio_function_write_word(SDIO_FUNCTION *func, uint32_t address, uint16_t input);

uint32_t STDCALL sdio_function_read_long(SDIO_FUNCTION *func, uint32_t address, uint32_t *output);

uint32_t STDCALL sdio_function_write_long(SDIO_FUNCTION *func, uint32_t address, uint32_t input);
 
uint32_t STDCALL sdio_function_register_interrupt(SDIO_FUNCTION *func, sdio_interrupt_handler handler);
uint32_t STDCALL sdio_function_deregister_interrupt(SDIO_FUNCTION *func);

uint32_t STDCALL sdio_host_dispatch_interrupt(SDHCI_HOST *sdhci, BOOL irq, BOOL fiq);


SDIO_DRIVER * STDCALL sdio_driver_create(void);

SDIO_DRIVER * STDCALL sdio_driver_create_ex(uint32_t size);

uint32_t STDCALL sdio_driver_destroy(SDIO_DRIVER *driver);

uint32_t STDCALL sdio_driver_register(SDIO_DRIVER *driver);

uint32_t STDCALL sdio_driver_deregister(SDIO_DRIVER *driver);

SDIO_DRIVER * STDCALL sdio_driver_find(uint32_t driverid);

SDIO_DRIVER * STDCALL sdio_driver_find_by_name(const char *name);
uint32_t STDCALL sdio_driver_enumerate(sdio_driver_enumerate_cb callback, void *data);


uint32_t STDCALL sdhci_host_reset(SDHCI_HOST *sdhci, uint8_t mask);

uint32_t STDCALL sdhci_host_hardware_reset(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_set_power(SDHCI_HOST *sdhci, uint16_t power);

uint32_t STDCALL sdhci_host_set_clock(SDHCI_HOST *sdhci, uint32_t clock);

uint32_t STDCALL sdhci_host_set_timing(SDHCI_HOST *sdhci, uint32_t timing);

uint32_t STDCALL sdhci_host_set_bus_width(SDHCI_HOST *sdhci, uint32_t buswidth);

uint32_t STDCALL sdhci_host_prepare_dma(SDHCI_HOST *sdhci, MMC_COMMAND *command);

uint32_t STDCALL sdhci_host_start_dma(SDHCI_HOST *sdhci, MMC_COMMAND *command);

uint32_t STDCALL sdhci_host_stop_dma(SDHCI_HOST *sdhci, MMC_COMMAND *command);

void STDCALL sdhci_host_complete_dma(DMA_REQUEST *request);

uint32_t STDCALL sdhci_host_setup_card_irq(SDHCI_HOST *sdhci, LONGBOOL enable);

uint32_t STDCALL sdhci_host_complete_card_irq(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_transfer_pio(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_transfer_dma(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_finish_command(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_finish_data(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_command_interrupt(SDHCI_HOST *sdhci, uint32_t interruptmask, uint32_t *returnmask);

uint32_t STDCALL sdhci_host_data_interrupt(SDHCI_HOST *sdhci, uint32_t interruptmask);

uint32_t STDCALL sdhci_host_start(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_stop(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_lock(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_unlock(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_signal(SDHCI_HOST *sdhci, SEMAPHORE_HANDLE semaphore);

uint8_t STDCALL sdhci_host_read_byte(SDHCI_HOST *sdhci, uint32_t reg);

uint16_t STDCALL sdhci_host_read_word(SDHCI_HOST *sdhci, uint32_t reg);

uint32_t STDCALL sdhci_host_read_long(SDHCI_HOST *sdhci, uint32_t reg);

void STDCALL sdhci_host_write_byte(SDHCI_HOST *sdhci, uint32_t reg, uint8_t value);

void STDCALL sdhci_host_write_word(SDHCI_HOST *sdhci, uint32_t reg, uint16_t value);

void STDCALL sdhci_host_write_long(SDHCI_HOST *sdhci, uint32_t reg, uint32_t value);

uint32_t STDCALL sdhci_host_set_clock_divider(SDHCI_HOST *sdhci, int index, uint32_t divider);

uint32_t STDCALL sdhci_host_set_control_register(SDHCI_HOST *sdhci);

size_t STDCALL sdhci_host_get_adma_address(SDHCI_HOST *sdhci);

void STDCALL sdhci_host_set_adma_address(SDHCI_HOST *sdhci, size_t address);

size_t STDCALL sdhci_host_get_sdma_address(SDHCI_HOST *sdhci, MMC_COMMAND *command);

void STDCALL sdhci_host_set_sdma_address(SDHCI_HOST *sdhci, size_t address);

void STDCALL sdhci_host_write_adma_descriptor(SDHCI_HOST *sdhci, void *descriptor, uint16_t command, uint16_t len, size_t address);

SDHCI_HOST * STDCALL sdhci_host_create(void);

SDHCI_HOST * STDCALL sdhci_host_create_ex(uint32_t size);

uint32_t STDCALL sdhci_host_destroy(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_register(SDHCI_HOST *sdhci);

uint32_t STDCALL sdhci_host_deregister(SDHCI_HOST *sdhci);
 
SDHCI_HOST * STDCALL sdhci_host_find(uint32_t sdhciid);
uint32_t STDCALL sdhci_host_enumerate(sdhci_enumerate_cb callback, void *data);
 
uint32_t STDCALL sdhci_host_notification(SDHCI_HOST *sdhci, sdhci_notification_cb callback, void *data, uint32_t notification, uint32_t flags);


uint32_t STDCALL mmc_get_count(void);
 
MMC_DEVICE * STDCALL mmc_device_check(MMC_DEVICE *mmc);
 
BOOL STDCALL mmc_is_sd(MMC_DEVICE *mmc);
BOOL STDCALL mmc_is_sdio(MMC_DEVICE *mmc);
 
SDHCI_HOST * STDCALL mmc_get_sdhci(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_get_cid_value(MMC_DEVICE *mmc, uint32_t version, uint32_t value);

uint32_t STDCALL mmc_get_csd_value(MMC_DEVICE *mmc, uint32_t value);

uint32_t STDCALL mmc_extract_bits(void *buffer, uint32_t start, uint32_t size);

uint32_t STDCALL mmc_extract_bits_ex(void *buffer, uint32_t length, uint32_t start, uint32_t size);
 
BOOL STDCALL mmc_is_multi_command(uint16_t command);
 
BOOL STDCALL mmc_is_non_removable(MMC_DEVICE *mmc);
BOOL STDCALL mmc_has_extended_csd(MMC_DEVICE *mmc);
BOOL STDCALL mmc_has_set_block_count(MMC_DEVICE *mmc);
BOOL STDCALL mmc_has_auto_block_count(MMC_DEVICE *mmc);
BOOL STDCALL mmc_has_auto_command_stop(MMC_DEVICE *mmc);

uint32_t STDCALL mmc_status_to_string(uint32_t status, char *string, uint32_t len);

uint32_t STDCALL mmc_version_to_string(uint32_t version, char *string, uint32_t len);

uint32_t STDCALL mmc_timing_to_string(uint32_t timing, char *string, uint32_t len);

uint32_t STDCALL mmc_bus_width_to_string(uint32_t buswidth, char *string, uint32_t len);

uint32_t STDCALL mmc_driver_type_to_string(uint32_t drivertype, char *string, uint32_t len);

uint32_t STDCALL mmc_signal_voltage_to_string(uint32_t signalvoltage, char *string, uint32_t len);
 
uint32_t STDCALL mmc_device_type_to_string(uint32_t mmctype, char *string, uint32_t len);
uint32_t STDCALL mmc_device_state_to_string(uint32_t mmcstate, char *string, uint32_t len);

uint32_t STDCALL mmc_device_state_to_notification(uint32_t state);


uint32_t STDCALL sd_get_max_clock(MMC_DEVICE *mmc);

uint32_t STDCALL sd_get_cid_value(MMC_DEVICE *mmc, uint32_t value);

uint32_t STDCALL sd_get_csd_value(MMC_DEVICE *mmc, uint32_t version, uint32_t value);

uint32_t STDCALL sd_get_scr_value(MMC_DEVICE *mmc, uint32_t value);

uint32_t STDCALL sd_get_ssr_value(MMC_DEVICE *mmc, uint32_t value);

uint32_t STDCALL sd_get_switch_value(MMC_DEVICE *mmc, uint32_t value);

uint32_t STDCALL sd_version_to_string(uint32_t version, char *string, uint32_t len);

uint32_t STDCALL sd_bus_width_to_string(uint32_t buswidth, char *string, uint32_t len);


uint32_t STDCALL sdio_driver_get_count(void);

SDIO_DRIVER * STDCALL sdio_driver_check(SDIO_DRIVER *driver);

uint32_t STDCALL sdio_device_get_max_clock(MMC_DEVICE *mmc);
 
MMC_DEVICE * STDCALL sdio_function_get_mmc(SDIO_FUNCTION *func);
SDHCI_HOST * STDCALL sdio_function_get_sdhci(SDIO_FUNCTION *func);

uint32_t STDCALL sdio_version_to_string(uint32_t version, char *string, uint32_t len);
 
uint32_t STDCALL sdio_function_state_to_string(uint32_t sdiostate, char *string, uint32_t len);
uint32_t STDCALL sdio_function_status_to_string(uint32_t sdiostatus, char *string, uint32_t len);

uint32_t STDCALL sdio_function_state_to_notification(uint32_t state);

uint32_t STDCALL sdio_function_status_to_notification(uint32_t status);


uint32_t STDCALL sdhci_get_count(void);

SDHCI_HOST * STDCALL sdhci_host_check(SDHCI_HOST *sdhci);
 
BOOL STDCALL sdhci_is_spi(SDHCI_HOST *sdhci);
BOOL STDCALL sdhci_has_dma(SDHCI_HOST *sdhci);
BOOL STDCALL sdhci_has_cmd23(SDHCI_HOST *sdhci);
BOOL STDCALL sdhci_auto_cmd12(SDHCI_HOST *sdhci);
BOOL STDCALL sdhci_auto_cmd23(SDHCI_HOST *sdhci);
 
uint16_t STDCALL sdhci_get_version(SDHCI_HOST *sdhci);
 
uint16_t STDCALL sdhci_get_command(uint16_t command);
uint16_t STDCALL sdhci_make_command(uint16_t command, uint16_t flags);
uint16_t STDCALL sdhci_make_block_size(uint16_t dma, uint16_t blocksize);

uint32_t STDCALL sdhci_version_to_string(uint32_t version, char *name, uint32_t len);

uint32_t STDCALL sdhci_power_to_string(uint32_t power, char *name, uint32_t len);
 
uint32_t STDCALL sdhci_device_type_to_string(uint32_t sdhcitype, char *name, uint32_t len);
uint32_t STDCALL sdhci_host_type_to_string(uint32_t sdhcitype, char *name, uint32_t len);
uint32_t STDCALL sdhci_device_state_to_string(uint32_t sdhcistate, char *name, uint32_t len);
uint32_t STDCALL sdhci_host_state_to_string(uint32_t sdhcistate, char *name, uint32_t len);

uint32_t STDCALL sdhci_host_state_to_notification(uint32_t state);
 
#ifdef __cplusplus
}
#endif
 
#endif // _ULTIBO_MMC_H