pl18x.h

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/*
 * This file is part of the Ultibo project, https://ultibo.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2026 Garry Wood <garry@softoz.com.au>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef _ULTIBO_PL18X_H
#define _ULTIBO_PL18X_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "ultibo/mmc.h"

#define PL180_MMCI_DESCRIPTION  "ARM PrimeCell PL180 MMCI Host" 
#define PL181_MMCI_DESCRIPTION  "ARM PrimeCell PL181 MMCI Host" 

#define PL18X_MMCI_POWER    0x000
#define PL18X_MMCI_POWER_OFF    0x00 
#define PL18X_MMCI_POWER_UP 0x02 
#define PL18X_MMCI_POWER_ON 0x03 
#define PL18X_MMCI_POWER_OD (1 << 6) 
#define PL18X_MMCI_POWER_ROD    (1 << 7) 

#define PL18X_MMCI_POWER_ST_DATA2DIREN  (1 << 2)
#define PL18X_MMCI_POWER_ST_CMDDIREN    (1 << 3)
#define PL18X_MMCI_POWER_ST_DATA0DIREN  (1 << 4)
#define PL18X_MMCI_POWER_ST_DATA31DIREN (1 << 5)
#define PL18X_MMCI_POWER_ST_FBCLKEN (1 << 7)
#define PL18X_MMCI_POWER_ST_DATA74DIREN (1 << 8)

#define PL18X_MMCI_CLOCK    0x004
#define PL18X_MMCI_CLOCK_ENABLE (1 << 8) 
#define PL18X_MMCI_CLOCK_PWRSAVE    (1 << 9) 
#define PL18X_MMCI_CLOCK_BYPASS (1 << 10) 
#define PL18X_MMCI_CLOCK_4BIT_BUS   (1 << 11) 

#define PL18X_MMCI_CLOCK_ST_8BIT_BUS    (1 << 12)
#define PL18X_MMCI_CLOCK_ST_U300_HWFCEN (1 << 13)
#define PL18X_MMCI_CLOCK_ST_UX500_NEG_EDGE  (1 << 13)
#define PL18X_MMCI_CLOCK_ST_UX500_HWFCEN    (1 << 14)
#define PL18X_MMCI_CLOCK_ST_UX500_CLK_INV   (1 << 15)
#define PL18X_MMCI_CLOCK_ARM_HWFCEN (1 << 12)

#define PL18X_MMCI_CLOCK_QCOM_WIDEBUS_8 (1 << 10) | (1 << 11)
#define PL18X_MMCI_CLOCK_QCOM_FLOWENA   (1 << 12)
#define PL18X_MMCI_CLOCK_QCOM_INVERTOUT (1 << 13)

#define PL18X_MMCI_CLOCK_QCOM_SELECT_IN_FBCLK   (1 << 15)
#define PL18X_MMCI_CLOCK_QCOM_SELECT_IN_DDR_MODE    (1 << 14) | (1 << 15)

#define PL18X_MMCI_ARGUMENT 0x008

#define PL18X_MMCI_COMMAND  0x00c
#define PL18X_MMCI_CPSM_RESPONSE    (1 << 6) 
#define PL18X_MMCI_CPSM_LONGRSP (1 << 7) 
#define PL18X_MMCI_CPSM_INTERRUPT   (1 << 8) 
#define PL18X_MMCI_CPSM_PENDING (1 << 9) 
#define PL18X_MMCI_CPSM_ENABLE  (1 << 10) 
#define PL18X_MMCI_CPSM_ST_SDIO_SUSP    (1 << 11)
#define PL18X_MMCI_CPSM_ST_ENCMD_COMPL  (1 << 12)
#define PL18X_MMCI_CPSM_ST_NIEN (1 << 13)
#define PL18X_MMCI_CPSM_ST_CE_ATACMD    (1 << 14)

#define PL18X_MMCI_CPSM_QCOM_DATCMD (1 << 12)
#define PL18X_MMCI_CPSM_QCOM_MCIABORT   (1 << 13)
#define PL18X_MMCI_CPSM_QCOM_CCSENABLE  (1 << 14)
#define PL18X_MMCI_CPSM_QCOM_CCSDISABLE (1 << 15)
#define PL18X_MMCI_CPSM_QCOM_AUTO_CMD19 (1 << 16)
#define PL18X_MMCI_CPSM_QCOM_AUTO_CMD21 (1 << 21)

#define PL18X_MMCI_RESPCMD  0x010

#define PL18X_MMCI_RESPONSE0    0x014
#define PL18X_MMCI_RESPONSE1    0x018
#define PL18X_MMCI_RESPONSE2    0x01c
#define PL18X_MMCI_RESPONSE3    0x020

#define PL18X_MMCI_DATATIMER    0x024

#define PL18X_MMCI_DATALENGTH   0x028

#define PL18X_MMCI_DATACTRL 0x02c
#define PL18X_MMCI_DPSM_ENABLE  (1 << 0) 
#define PL18X_MMCI_DPSM_DIRECTION   (1 << 1) 
#define PL18X_MMCI_DPSM_MODE    (1 << 2) 
#define PL18X_MMCI_DPSM_DMAENABLE   (1 << 3) 
#define PL18X_MMCI_DPSM_BLOCKSIZE   (1 << 4) 
#define PL18X_MMCI_ST_DPSM_RWSTART  (1 << 8)
#define PL18X_MMCI_ST_DPSM_RWSTOP   (1 << 9)
#define PL18X_MMCI_ST_DPSM_RWMOD    (1 << 10)
#define PL18X_MMCI_ST_DPSM_SDIOEN   (1 << 11)
#define PL18X_MMCI_ST_DPSM_DMAREQCTL    (1 << 12)
#define PL18X_MMCI_ST_DPSM_DBOOTMODEEN  (1 << 13)
#define PL18X_MMCI_ST_DPSM_BUSYMODE (1 << 14)
#define PL18X_MMCI_ST_DPSM_DDRMODE  (1 << 15)

#define PL18X_MMCI_DATACNT  0x030

#define PL18X_MMCI_STATUS   0x034
#define PL18X_MMCI_CMDCRCFAIL   (1 << 0)
#define PL18X_MMCI_DATACRCFAIL  (1 << 1)
#define PL18X_MMCI_CMDTIMEOUT   (1 << 2)
#define PL18X_MMCI_DATATIMEOUT  (1 << 3)
#define PL18X_MMCI_TXUNDERRUN   (1 << 4)
#define PL18X_MMCI_RXOVERRUN    (1 << 5)
#define PL18X_MMCI_CMDRESPEND   (1 << 6)
#define PL18X_MMCI_CMDSENT  (1 << 7)
#define PL18X_MMCI_DATAEND  (1 << 8)
#define PL18X_MMCI_STARTBITERR  (1 << 9)
#define PL18X_MMCI_DATABLOCKEND (1 << 10)
#define PL18X_MMCI_CMDACTIVE    (1 << 11)
#define PL18X_MMCI_TXACTIVE (1 << 12)
#define PL18X_MMCI_RXACTIVE (1 << 13)
#define PL18X_MMCI_TXFIFOHALFEMPTY  (1 << 14)
#define PL18X_MMCI_RXFIFOHALFFULL   (1 << 15)
#define PL18X_MMCI_TXFIFOFULL   (1 << 16)
#define PL18X_MMCI_RXFIFOFULL   (1 << 17)
#define PL18X_MMCI_TXFIFOEMPTY  (1 << 18)
#define PL18X_MMCI_RXFIFOEMPTY  (1 << 19)
#define PL18X_MMCI_TXDATAAVLBL  (1 << 20)
#define PL18X_MMCI_RXDATAAVLBL  (1 << 21)
#define PL18X_MMCI_ST_SDIOIT    (1 << 22)
#define PL18X_MMCI_ST_CEATAEND  (1 << 23)
#define PL18X_MMCI_ST_CARDBUSY  (1 << 24)

#define PL18X_MMCI_CLEAR    0x038
#define PL18X_MMCI_CMDCRCFAILCLR    (1 << 0)
#define PL18X_MMCI_DATACRCFAILCLR   (1 << 1)
#define PL18X_MMCI_CMDTIMEOUTCLR    (1 << 2)
#define PL18X_MMCI_DATATIMEOUTCLR   (1 << 3)
#define PL18X_MMCI_TXUNDERRUNCLR    (1 << 4)
#define PL18X_MMCI_RXOVERRUNCLR (1 << 5)
#define PL18X_MMCI_CMDRESPENDCLR    (1 << 6)
#define PL18X_MMCI_CMDSENTCLR   (1 << 7)
#define PL18X_MMCI_DATAENDCLR   (1 << 8)
#define PL18X_MMCI_STARTBITERRCLR   (1 << 9)
#define PL18X_MMCI_DATABLOCKENDCLR  (1 << 10)
#define PL18X_MMCI_ST_SDIOITC   (1 << 22)
#define PL18X_MMCI_ST_CEATAENDC (1 << 23)
#define PL18X_MMCI_ST_BUSYENDC  (1 << 24)

#define PL18X_MMCI_MASK0    0x03c
#define PL18X_MMCI_MASK1    0x040
#define PL18X_MMCI_CMDCRCFAILMASK   (1 << 0)
#define PL18X_MMCI_DATACRCFAILMASK  (1 << 1)
#define PL18X_MMCI_CMDTIMEOUTMASK   (1 << 2)
#define PL18X_MMCI_DATATIMEOUTMASK  (1 << 3)
#define PL18X_MMCI_TXUNDERRUNMASK   (1 << 4)
#define PL18X_MMCI_RXOVERRUNMASK    (1 << 5)
#define PL18X_MMCI_CMDRESPENDMASK   (1 << 6)
#define PL18X_MMCI_CMDSENTMASK  (1 << 7)
#define PL18X_MMCI_DATAENDMASK  (1 << 8)
#define PL18X_MMCI_STARTBITERRMASK  (1 << 9)
#define PL18X_MMCI_DATABLOCKENDMASK (1 << 10)
#define PL18X_MMCI_CMDACTIVEMASK    (1 << 11)
#define PL18X_MMCI_TXACTIVEMASK (1 << 12)
#define PL18X_MMCI_RXACTIVEMASK (1 << 13)
#define PL18X_MMCI_TXFIFOHALFEMPTYMASK  (1 << 14)
#define PL18X_MMCI_RXFIFOHALFFULLMASK   (1 << 15)
#define PL18X_MMCI_TXFIFOFULLMASK   (1 << 16)
#define PL18X_MMCI_RXFIFOFULLMASK   (1 << 17)
#define PL18X_MMCI_TXFIFOEMPTYMASK  (1 << 18)
#define PL18X_MMCI_RXFIFOEMPTYMASK  (1 << 19)
#define PL18X_MMCI_TXDATAAVLBLMASK  (1 << 20)
#define PL18X_MMCI_RXDATAAVLBLMASK  (1 << 21)
#define PL18X_MMCI_ST_SDIOITMASK    (1 << 22)
#define PL18X_MMCI_ST_CEATAENDMASK  (1 << 23)
#define PL18X_MMCI_ST_BUSYEND   (1 << 24)

#define PL18X_MMCI_SELECT   0x044

#define PL18X_MMCI_FIFOCNT  0x048

#define PL18X_MMCI_FIFO 0x080 

#define PL18X_MMCI_PERIPHID 0xFE0

#define PL18X_MMCI_PCELLID  0xFF0
 
#define PL18X_MMCI_IRQENABLE    (PL18X_MMCI_CMDCRCFAILMASK | PL18X_MMCI_DATACRCFAILMASK | PL18X_MMCI_CMDTIMEOUTMASK |  PL18X_MMCI_DATATIMEOUTMASK | PL18X_MMCI_TXUNDERRUNMASK | PL18X_MMCI_RXOVERRUNMASK | PL18X_MMCI_CMDRESPENDMASK | PL18X_MMCI_CMDSENTMASK | PL18X_MMCI_STARTBITERRMASK)
#define PL18X_MMCI_IRQ1MASK (PL18X_MMCI_RXFIFOHALFFULLMASK | PL18X_MMCI_RXDATAAVLBLMASK | PL18X_MMCI_TXFIFOHALFEMPTYMASK)

typedef struct _PL18X_VERSIONDATA PL18X_VERSIONDATA;
 
typedef struct _PL18X_VERSIONID PL18X_VERSIONID;
struct _PL18X_VERSIONID
{
    uint32_t peripheralid;
    uint32_t peripheralmask;
    PL18X_VERSIONDATA *versiondata;
};
 
 
struct _PL18X_VERSIONDATA
{
    char *name; 
    uint32_t clockregister; 
    uint32_t clockenable; 
    uint32_t clock8bitenable; 
    uint32_t clocknegativeedgeenable; 
    uint32_t datalengthbits; 
    uint32_t fifosize; 
    uint32_t fifohalfsize; 
    uint32_t datacommandenable; 
    uint32_t datacontrolmaskddr; 
    uint32_t datacontrolmasksdio; 
    LONGBOOL stsdio; 
    LONGBOOL stclockdivider; 
    LONGBOOL blocksizedatacontrol16; 
    LONGBOOL blocksizedatacontrol4; 
    uint32_t powerpowerup; 
    uint32_t clockmaximum; 
    LONGBOOL signaldirection; 
    LONGBOOL powerclockgate; 
    LONGBOOL busydetect; 
    LONGBOOL powernopower; 
    LONGBOOL explicitmclockcontrol; 
    LONGBOOL qualcommfifo; 
    LONGBOOL qualcommdma; 
    LONGBOOL reversedirq; 
};
 

typedef struct _PL18X_MMCIREGISTERS PL18X_MMCIREGISTERS;
struct _PL18X_MMCIREGISTERS
{
    uint32_t power; 
    uint32_t clock; 
    uint32_t argument; 
    uint32_t command; 
    uint32_t respcmd; 
    uint32_t response0; 
    uint32_t response1; 
    uint32_t response2; 
    uint32_t response3; 
    uint32_t datatimer; 
    uint32_t datalength; 
    uint32_t datactrl; 
    uint32_t datacnt; 
    uint32_t status; 
    uint32_t clear; 
    uint32_t mask0; 
    uint32_t mask1; 
    uint32_t select; 
    uint32_t fifocnt; 
    uint8_t reserved[0x30]; 
    uint32_t fifo; 
};
 

typedef struct _PL18X_SDHCIHOST PL18X_SDHCIHOST;

typedef uint32_t STDCALL (*pl18xsdhci_get_rxfifo_count_proc)(PL18X_SDHCIHOST *sdhci, uint32_t status, uint32_t remain);
 
struct _PL18X_SDHCIHOST
{
    // SDHCI Properties
    SDHCI_HOST sdhci;
    // PL18X Properties
    uint32_t irq0; 
    uint32_t irq1; 
    LONGBOOL enablefiq; 
    LONGBOOL singleirq; 
    PL18X_MMCIREGISTERS *registers; 
    PL18X_VERSIONDATA *version; 
    uint32_t clockregister; 
    uint32_t powerregister; 
    uint32_t datactrlregister; 
    uint32_t busystatus; 
    pl18xsdhci_get_rxfifo_count_proc getrxfifocount; 
};

void STDCALL pl18x_init(void);


SDHCI_HOST * STDCALL pl180sdhci_create(size_t address, char *name, uint32_t irq0, uint32_t irq1, uint32_t clockminimum, uint32_t clockmaximum, mmc_device_get_card_detect_proc carddetect, mmc_device_get_write_protect_proc writeprotect);

SDHCI_HOST * STDCALL pl181sdhci_create(size_t address, char *name, uint32_t irq0, uint32_t irq1, uint32_t clockminimum, uint32_t clockmaximum, mmc_device_get_card_detect_proc carddetect, mmc_device_get_write_protect_proc writeprotect);

uint32_t STDCALL pl18xsdhci_destroy(SDHCI_HOST *sdhci);
 
#ifdef __cplusplus
}
#endif
 
#endif // _ULTIBO_PL18X_H