Ultibo API
C/C++ API for Ultibo Core
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pl110.h File Reference
#include "ultibo/framebuffer.h"

Go to the source code of this file.

Data Structures

struct  _PL110_CLCD_REGISTERS
struct  _PL110_FRAMEBUFFER

Macros

#define PL110_FRAMEBUFFER_DESCRIPTION   "ARM PrimeCell PL110 Color LCD"
 Description of PL110 device.
#define PL110_MAX_PHYSICALWIDTH   1024
#define PL110_MAX_PHYSICALHEIGHT   1024
#define PL110_MODE_UNKNOWN   0
#define PL110_MODE_VGA   1
 Connected to a VGA display.
#define PL110_MODE_SVGA   2
 Connected to a SVGA display.
#define PL110_MODE_TFT   3
 Connected to a TFT display.
#define PL110_MODE_STN   4
 Connected to an STN display.
#define PL110_CLCD_TIMING0   0x00000000
 Horizontal Axis Panel Control Register.
#define PL110_CLCD_TIMING1   0x00000004
 Vertical Axis Panel Control Register.
#define PL110_CLCD_TIMING2   0x00000008
 Clock and Signal Polarity Control Register.
#define PL110_CLCD_TIMING3   0x0000000c
 Line End Control Register.
#define PL110_CLCD_UPBASE   0x00000010
 Upper Panel Frame Base Address Registers.
#define PL110_CLCD_LPBASE   0x00000014
 Lower Panel Frame Base Address Registers.
#define PL110_CLCD_CONTROL   0x00000018
 Control Register.
#define PL110_CLCD_IMSC   0x0000001c
 Interrupt Mask Set/Clear Register.
#define PL110_CLCD_RIS   0x00000020
 Raw Interrupt Status Register.
#define PL110_CLCD_MIS   0x00000024
 Masked Interrupt Status Register.
#define PL110_CLCD_ICR   0x00000028
 Interrupt Clear Register.
#define PL110_CLCD_UPCURR   0x0000002C
 Upper Panel Current Address Value Registers.
#define PL110_CLCD_LPCURR   0x00000030
 Lower Panel Current Address Value Registers.
#define PL110_CLCD_PALETTE   0x00000200
 Color Palette Register.
#define PL110_CLCD_TIMING0_HBP   (0xFF << 24)
 Horizontal back porch.
#define PL110_CLCD_TIMING0_HFP   (0xFF << 16)
 Horizontal front porch.
#define PL110_CLCD_TIMING0_HSW   (0xFF << 8)
 Horizontal synchronization pulse width.
#define PL110_CLCD_TIMING0_PPL   (0xFC << 2)
 Pixels-per-line (Actual pixels-per-line = 16 * (PPL + 1)).
#define PL110_CLCD_TIMING1_VBP   (0xFF << 24)
 Vertical back porch.
#define PL110_CLCD_TIMING1_VFP   (0xFF << 16)
 Vertical front porch.
#define PL110_CLCD_TIMING1_VSW   (0xFC << 10)
 Vertical synchronization pulse width.
#define PL110_CLCD_TIMING1_LPP   (0x3FF << 0)
 Lines per panel is the number of active lines per screen (Program to number of lines required minus 1).
#define PL110_CLCD_TIMING2_PCD_HI   (0x1F << 27)
 Upper five bits of Panel Clock Divisor.
#define PL110_CLCD_TIMING2_BCD   (1 << 26)
 Bypass pixel clock divider.
#define PL110_CLCD_TIMING2_CPL   (0x3FF << 16)
 Clocks per line.
#define PL110_CLCD_TIMING2_IOE   (1 << 14)
 Invert output enable.
#define PL110_CLCD_TIMING2_IPC   (1 << 13)
 Invert panel clock.
#define PL110_CLCD_TIMING2_IHS   (1 << 12)
 Invert horizontal synchron.
#define PL110_CLCD_TIMING2_IVS   (1 << 11)
 Invert vertical synchronization.
#define PL110_CLCD_TIMING2_ACB   (0x1F << 6)
 AC bias pin frequency.
#define PL110_CLCD_TIMING2_CLKSEL   (1 << 5)
 This bit drives the CLCDCLKSEL signal which is used as the select signal for the external LCD clock multiplexor.
#define PL110_CLCD_TIMING2_PCD_LO   (0x1F << 0)
 Lower five bits of Panel Clock Divisor.
#define PL110_CLCD_TIMING3_LEE   (1 << 16)
 LCD Line end enable: 0 = CLLE disabled (held LOW) / 1 = CLLE signal active.
#define PL110_CLCD_TIMING3_LED   (0x3F << 0)
 Line-end signal delay from the rising-edge of the last panel clock.
#define PL110_CLCD_CONTROL_LCDEN   (1 << 0)
#define PL110_CLCD_CONTROL_LCDBPP1   (0 << 1)
 LCD bits per pixel: 000 = 1 bpp.
#define PL110_CLCD_CONTROL_LCDBPP2   (1 << 1)
 001 = 2 bpp
#define PL110_CLCD_CONTROL_LCDBPP4   (2 << 1)
 010 = 4 bpp
#define PL110_CLCD_CONTROL_LCDBPP8   (3 << 1)
 011 = 8 bpp
#define PL110_CLCD_CONTROL_LCDBPP16   (4 << 1)
 100 = 16 bpp
#define PL110_CLCD_CONTROL_LCDBPP16_565   (6 << 1)
 110 = 16 bpp 565 (PL111 only)
#define PL110_CLCD_CONTROL_LCDBPP16_444   (7 << 1)
 111 = 16 bpp 444 (PL111 only)
#define PL110_CLCD_CONTROL_LCDBPP24   (5 << 1)
 101 = 24 bpp
#define PL110_CLCD_CONTROL_LCDBW   (1 << 4)
 STN LCD is monochrome (black and white) (0 = STN LCD is color / 1 = STN LCD is monochrome).
#define PL110_CLCD_CONTROL_LCDTFT   (1 << 5)
 LCD is TFT (0 = LCD is an STN display, use gray scaler / 1 = LCD is TFT, do not use gray scaler).
#define PL110_CLCD_CONTROL_LCDMONO8   (1 << 6)
 Monochrome LCD has an 8-bit interface (0 = mono LCD uses 4-bit interface / 1 = mono LCD uses 8-bit interface).
#define PL110_CLCD_CONTROL_LCDDUAL   (1 << 7)
 LCD interface is dual panel STN (0 = single panel LCD is in use / 1 = dual panel LCD is in use).
#define PL110_CLCD_CONTROL_BGR   (1 << 8)
 RGB or BGR format selection (0 = RGB normal output / 1 = BGR red and blue swapped.).
#define PL110_CLCD_CONTROL_BEBO   (1 << 9)
 Big-endian byte order (0 = little-endian byte order / 1 = big-endian byte order).
#define PL110_CLCD_CONTROL_BEPO   (1 << 10)
 Big-endian pixel ordering within a byte (0 = little-endian pixel ordering within a byte / 1= big-endian pixel ordering within a byte).
#define PL110_CLCD_CONTROL_LCDPWR   (1 << 11)
 LCD power enable.
#define PL110_CLCD_CONTROL_LCDVCOMP_VSYNC   (0 << 12)
 Generate interrupt at: 00 = start of vertical synchronization.
#define PL110_CLCD_CONTROL_LCDVCOMP_BPORCH   (1 << 12)
 01 = start of back porch
#define PL110_CLCD_CONTROL_LCDVCOMP_VIDEO   (2 << 12)
 10 = start of active video
#define PL110_CLCD_CONTROL_LCDVCOMP_FPORCH   (3 << 12)
 11 = start of front porch
#define PL110_CLCD_CONTROL_LDMAFIFOTIME   (1 << 15)
 Unknown.
#define PL110_CLCD_CONTROL_WATERMARK   (1 << 16)
 LCD DMA FIFO Watermark level.
#define PL110_CONTROL_VGA   PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH
#define PL110_CONTROL_SVGA   PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH
#define PL110_TIMING0_VGA   0x3F1F3F9C
#define PL110_TIMING0_SVGA   0x1313A4C4
#define PL110_TIMING1_VGA   0x090B61DF
#define PL110_TIMING1_SVGA   0x0505F657
#define PL110_TIMING2_VGA   0x067F1800
#define PL110_TIMING2_SVGA   0x071F1800

Typedefs

typedef struct _PL110_CLCD_REGISTERS PL110_CLCD_REGISTERS
typedef struct _PL110_FRAMEBUFFER PL110_FRAMEBUFFER

Functions

FRAMEBUFFER_DEVICE *STDCALL pl110_framebuffer_create_vga (size_t address, char *name, uint32_t rotation, uint32_t width, uint32_t height, uint32_t depth)
 Create, register and allocate a new PL110 Framebuffer device which can be accessed using the framebuffer API.
FRAMEBUFFER_DEVICE *STDCALL pl110_framebuffer_create_svga (size_t address, char *name, uint32_t rotation, uint32_t width, uint32_t height, uint32_t depth)
 Create, register and allocate a new PL110 Framebuffer device which can be accessed using the framebuffer API.
uint32_t STDCALL pl110_framebuffer_destroy (FRAMEBUFFER_DEVICE *framebuffer)
 Release, deregister and destroy a PL110 Framebuffer device created by this driver.

Macro Definition Documentation

◆ PL110_FRAMEBUFFER_DESCRIPTION

#define PL110_FRAMEBUFFER_DESCRIPTION   "ARM PrimeCell PL110 Color LCD"

Description of PL110 device.

PL110 specific constants

◆ PL110_MAX_PHYSICALWIDTH

#define PL110_MAX_PHYSICALWIDTH   1024

◆ PL110_MAX_PHYSICALHEIGHT

#define PL110_MAX_PHYSICALHEIGHT   1024

◆ PL110_MODE_UNKNOWN

#define PL110_MODE_UNKNOWN   0

PL110 mode constants

◆ PL110_MODE_VGA

#define PL110_MODE_VGA   1

Connected to a VGA display.

◆ PL110_MODE_SVGA

#define PL110_MODE_SVGA   2

Connected to a SVGA display.

◆ PL110_MODE_TFT

#define PL110_MODE_TFT   3

Connected to a TFT display.

◆ PL110_MODE_STN

#define PL110_MODE_STN   4

Connected to an STN display.

◆ PL110_CLCD_TIMING0

#define PL110_CLCD_TIMING0   0x00000000

Horizontal Axis Panel Control Register.

PL110 register offsets (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_TIMING1

#define PL110_CLCD_TIMING1   0x00000004

Vertical Axis Panel Control Register.

◆ PL110_CLCD_TIMING2

#define PL110_CLCD_TIMING2   0x00000008

Clock and Signal Polarity Control Register.

◆ PL110_CLCD_TIMING3

#define PL110_CLCD_TIMING3   0x0000000c

Line End Control Register.

◆ PL110_CLCD_UPBASE

#define PL110_CLCD_UPBASE   0x00000010

Upper Panel Frame Base Address Registers.

◆ PL110_CLCD_LPBASE

#define PL110_CLCD_LPBASE   0x00000014

Lower Panel Frame Base Address Registers.

◆ PL110_CLCD_CONTROL

#define PL110_CLCD_CONTROL   0x00000018

Control Register.

◆ PL110_CLCD_IMSC

#define PL110_CLCD_IMSC   0x0000001c

Interrupt Mask Set/Clear Register.

◆ PL110_CLCD_RIS

#define PL110_CLCD_RIS   0x00000020

Raw Interrupt Status Register.

◆ PL110_CLCD_MIS

#define PL110_CLCD_MIS   0x00000024

Masked Interrupt Status Register.

◆ PL110_CLCD_ICR

#define PL110_CLCD_ICR   0x00000028

Interrupt Clear Register.

◆ PL110_CLCD_UPCURR

#define PL110_CLCD_UPCURR   0x0000002C

Upper Panel Current Address Value Registers.

◆ PL110_CLCD_LPCURR

#define PL110_CLCD_LPCURR   0x00000030

Lower Panel Current Address Value Registers.

◆ PL110_CLCD_PALETTE

#define PL110_CLCD_PALETTE   0x00000200

Color Palette Register.

◆ PL110_CLCD_TIMING0_HBP

#define PL110_CLCD_TIMING0_HBP   (0xFF << 24)

Horizontal back porch.

PL110 Timing0 register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_TIMING0_HFP

#define PL110_CLCD_TIMING0_HFP   (0xFF << 16)

Horizontal front porch.

◆ PL110_CLCD_TIMING0_HSW

#define PL110_CLCD_TIMING0_HSW   (0xFF << 8)

Horizontal synchronization pulse width.

◆ PL110_CLCD_TIMING0_PPL

#define PL110_CLCD_TIMING0_PPL   (0xFC << 2)

Pixels-per-line (Actual pixels-per-line = 16 * (PPL + 1)).

◆ PL110_CLCD_TIMING1_VBP

#define PL110_CLCD_TIMING1_VBP   (0xFF << 24)

Vertical back porch.

PL110 Timing1 register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_TIMING1_VFP

#define PL110_CLCD_TIMING1_VFP   (0xFF << 16)

Vertical front porch.

◆ PL110_CLCD_TIMING1_VSW

#define PL110_CLCD_TIMING1_VSW   (0xFC << 10)

Vertical synchronization pulse width.

◆ PL110_CLCD_TIMING1_LPP

#define PL110_CLCD_TIMING1_LPP   (0x3FF << 0)

Lines per panel is the number of active lines per screen (Program to number of lines required minus 1).

◆ PL110_CLCD_TIMING2_PCD_HI

#define PL110_CLCD_TIMING2_PCD_HI   (0x1F << 27)

Upper five bits of Panel Clock Divisor.

PL110 Timing2 register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_TIMING2_BCD

#define PL110_CLCD_TIMING2_BCD   (1 << 26)

Bypass pixel clock divider.

◆ PL110_CLCD_TIMING2_CPL

#define PL110_CLCD_TIMING2_CPL   (0x3FF << 16)

Clocks per line.

◆ PL110_CLCD_TIMING2_IOE

#define PL110_CLCD_TIMING2_IOE   (1 << 14)

Invert output enable.

◆ PL110_CLCD_TIMING2_IPC

#define PL110_CLCD_TIMING2_IPC   (1 << 13)

Invert panel clock.

◆ PL110_CLCD_TIMING2_IHS

#define PL110_CLCD_TIMING2_IHS   (1 << 12)

Invert horizontal synchron.

◆ PL110_CLCD_TIMING2_IVS

#define PL110_CLCD_TIMING2_IVS   (1 << 11)

Invert vertical synchronization.

◆ PL110_CLCD_TIMING2_ACB

#define PL110_CLCD_TIMING2_ACB   (0x1F << 6)

AC bias pin frequency.

◆ PL110_CLCD_TIMING2_CLKSEL

#define PL110_CLCD_TIMING2_CLKSEL   (1 << 5)

This bit drives the CLCDCLKSEL signal which is used as the select signal for the external LCD clock multiplexor.

◆ PL110_CLCD_TIMING2_PCD_LO

#define PL110_CLCD_TIMING2_PCD_LO   (0x1F << 0)

Lower five bits of Panel Clock Divisor.

◆ PL110_CLCD_TIMING3_LEE

#define PL110_CLCD_TIMING3_LEE   (1 << 16)

LCD Line end enable: 0 = CLLE disabled (held LOW) / 1 = CLLE signal active.

PL110 Timing3 register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_TIMING3_LED

#define PL110_CLCD_TIMING3_LED   (0x3F << 0)

Line-end signal delay from the rising-edge of the last panel clock.

◆ PL110_CLCD_CONTROL_LCDEN

#define PL110_CLCD_CONTROL_LCDEN   (1 << 0)

PL110 Control register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)

◆ PL110_CLCD_CONTROL_LCDBPP1

#define PL110_CLCD_CONTROL_LCDBPP1   (0 << 1)

LCD bits per pixel: 000 = 1 bpp.

◆ PL110_CLCD_CONTROL_LCDBPP2

#define PL110_CLCD_CONTROL_LCDBPP2   (1 << 1)

001 = 2 bpp

◆ PL110_CLCD_CONTROL_LCDBPP4

#define PL110_CLCD_CONTROL_LCDBPP4   (2 << 1)

010 = 4 bpp

◆ PL110_CLCD_CONTROL_LCDBPP8

#define PL110_CLCD_CONTROL_LCDBPP8   (3 << 1)

011 = 8 bpp

◆ PL110_CLCD_CONTROL_LCDBPP16

#define PL110_CLCD_CONTROL_LCDBPP16   (4 << 1)

100 = 16 bpp

◆ PL110_CLCD_CONTROL_LCDBPP16_565

#define PL110_CLCD_CONTROL_LCDBPP16_565   (6 << 1)

110 = 16 bpp 565 (PL111 only)

◆ PL110_CLCD_CONTROL_LCDBPP16_444

#define PL110_CLCD_CONTROL_LCDBPP16_444   (7 << 1)

111 = 16 bpp 444 (PL111 only)

◆ PL110_CLCD_CONTROL_LCDBPP24

#define PL110_CLCD_CONTROL_LCDBPP24   (5 << 1)

101 = 24 bpp

◆ PL110_CLCD_CONTROL_LCDBW

#define PL110_CLCD_CONTROL_LCDBW   (1 << 4)

STN LCD is monochrome (black and white) (0 = STN LCD is color / 1 = STN LCD is monochrome).

◆ PL110_CLCD_CONTROL_LCDTFT

#define PL110_CLCD_CONTROL_LCDTFT   (1 << 5)

LCD is TFT (0 = LCD is an STN display, use gray scaler / 1 = LCD is TFT, do not use gray scaler).

◆ PL110_CLCD_CONTROL_LCDMONO8

#define PL110_CLCD_CONTROL_LCDMONO8   (1 << 6)

Monochrome LCD has an 8-bit interface (0 = mono LCD uses 4-bit interface / 1 = mono LCD uses 8-bit interface).

◆ PL110_CLCD_CONTROL_LCDDUAL

#define PL110_CLCD_CONTROL_LCDDUAL   (1 << 7)

LCD interface is dual panel STN (0 = single panel LCD is in use / 1 = dual panel LCD is in use).

◆ PL110_CLCD_CONTROL_BGR

#define PL110_CLCD_CONTROL_BGR   (1 << 8)

RGB or BGR format selection (0 = RGB normal output / 1 = BGR red and blue swapped.).

◆ PL110_CLCD_CONTROL_BEBO

#define PL110_CLCD_CONTROL_BEBO   (1 << 9)

Big-endian byte order (0 = little-endian byte order / 1 = big-endian byte order).

◆ PL110_CLCD_CONTROL_BEPO

#define PL110_CLCD_CONTROL_BEPO   (1 << 10)

Big-endian pixel ordering within a byte (0 = little-endian pixel ordering within a byte / 1= big-endian pixel ordering within a byte).

◆ PL110_CLCD_CONTROL_LCDPWR

#define PL110_CLCD_CONTROL_LCDPWR   (1 << 11)

LCD power enable.

◆ PL110_CLCD_CONTROL_LCDVCOMP_VSYNC

#define PL110_CLCD_CONTROL_LCDVCOMP_VSYNC   (0 << 12)

Generate interrupt at: 00 = start of vertical synchronization.

◆ PL110_CLCD_CONTROL_LCDVCOMP_BPORCH

#define PL110_CLCD_CONTROL_LCDVCOMP_BPORCH   (1 << 12)

01 = start of back porch

◆ PL110_CLCD_CONTROL_LCDVCOMP_VIDEO

#define PL110_CLCD_CONTROL_LCDVCOMP_VIDEO   (2 << 12)

10 = start of active video

◆ PL110_CLCD_CONTROL_LCDVCOMP_FPORCH

#define PL110_CLCD_CONTROL_LCDVCOMP_FPORCH   (3 << 12)

11 = start of front porch

◆ PL110_CLCD_CONTROL_LDMAFIFOTIME

#define PL110_CLCD_CONTROL_LDMAFIFOTIME   (1 << 15)

Unknown.

◆ PL110_CLCD_CONTROL_WATERMARK

#define PL110_CLCD_CONTROL_WATERMARK   (1 << 16)

LCD DMA FIFO Watermark level.

◆ PL110_CONTROL_VGA

#define PL110_CONTROL_VGA   PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH

PL110 control constants

◆ PL110_CONTROL_SVGA

#define PL110_CONTROL_SVGA   PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH

◆ PL110_TIMING0_VGA

#define PL110_TIMING0_VGA   0x3F1F3F9C

PL110 timing0 constants

◆ PL110_TIMING0_SVGA

#define PL110_TIMING0_SVGA   0x1313A4C4

◆ PL110_TIMING1_VGA

#define PL110_TIMING1_VGA   0x090B61DF

PL110 timing1 constants

◆ PL110_TIMING1_SVGA

#define PL110_TIMING1_SVGA   0x0505F657

◆ PL110_TIMING2_VGA

#define PL110_TIMING2_VGA   0x067F1800

PL110 timing2 constants

◆ PL110_TIMING2_SVGA

#define PL110_TIMING2_SVGA   0x071F1800

Typedef Documentation

◆ PL110_CLCD_REGISTERS

typedef struct _PL110_CLCD_REGISTERS PL110_CLCD_REGISTERS

PL110 specific types Layout of the PL110 registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I904421.html)

◆ PL110_FRAMEBUFFER

typedef struct _PL110_FRAMEBUFFER PL110_FRAMEBUFFER

Function Documentation

◆ pl110_framebuffer_create_vga()

FRAMEBUFFER_DEVICE *STDCALL pl110_framebuffer_create_vga ( size_t address,
char * name,
uint32_t rotation,
uint32_t width,
uint32_t height,
uint32_t depth )

Create, register and allocate a new PL110 Framebuffer device which can be accessed using the framebuffer API.

PL110 Functions

Parameters
AddressThe address of the PL110 registers
NameThe text description of this device which will show in the device list (Optional)
RotationThe rotation value for the framebuffer device (eg FRAMEBUFFER_ROTATION_180)
WidthThe width of the framebuffer in pixels
HeightThe height of the framebuffer in pixels
DepthThe color depth (bits per pixel) for the framebuffer (eg FRAMEBUFFER_DEPTH_16)
Returns
Pointer to the new Framebuffer device or nil if the framebuffer device could not be created

◆ pl110_framebuffer_create_svga()

FRAMEBUFFER_DEVICE *STDCALL pl110_framebuffer_create_svga ( size_t address,
char * name,
uint32_t rotation,
uint32_t width,
uint32_t height,
uint32_t depth )

Create, register and allocate a new PL110 Framebuffer device which can be accessed using the framebuffer API.

Parameters
AddressThe address of the PL110 registers
NameThe text description of this device which will show in the device list (Optional)
RotationThe rotation value for the framebuffer device (eg FRAMEBUFFER_ROTATION_180)
WidthThe width of the framebuffer in pixels
HeightThe height of the framebuffer in pixels
DepthThe color depth (bits per pixel) for the framebuffer (eg FRAMEBUFFER_DEPTH_16)
Returns
Pointer to the new Framebuffer device or nil if the framebuffer device could not be created

◆ pl110_framebuffer_destroy()

uint32_t STDCALL pl110_framebuffer_destroy ( FRAMEBUFFER_DEVICE * framebuffer)

Release, deregister and destroy a PL110 Framebuffer device created by this driver.

Parameters
FramebufferThe Framebuffer device to destroy
Returns
ERROR_SUCCESS if completed or another error code on failure