pl110.h

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/*
 * This file is part of the Ultibo project, https://ultibo.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2026 Garry Wood <garry@softoz.com.au>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef _ULTIBO_PL110_H
#define _ULTIBO_PL110_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "ultibo/framebuffer.h"

#define PL110_FRAMEBUFFER_DESCRIPTION   "ARM PrimeCell PL110 Color LCD" 
 
#define PL110_MAX_PHYSICALWIDTH 1024
#define PL110_MAX_PHYSICALHEIGHT    1024

#define PL110_MODE_UNKNOWN  0
#define PL110_MODE_VGA  1 
#define PL110_MODE_SVGA 2 
#define PL110_MODE_TFT  3 
#define PL110_MODE_STN  4 

#define PL110_CLCD_TIMING0  0x00000000 
#define PL110_CLCD_TIMING1  0x00000004 
#define PL110_CLCD_TIMING2  0x00000008 
#define PL110_CLCD_TIMING3  0x0000000c 
#define PL110_CLCD_UPBASE   0x00000010 
#define PL110_CLCD_LPBASE   0x00000014 
#define PL110_CLCD_CONTROL  0x00000018 
#define PL110_CLCD_IMSC 0x0000001c 
#define PL110_CLCD_RIS  0x00000020 
#define PL110_CLCD_MIS  0x00000024 
#define PL110_CLCD_ICR  0x00000028 
#define PL110_CLCD_UPCURR   0x0000002C 
#define PL110_CLCD_LPCURR   0x00000030 
#define PL110_CLCD_PALETTE  0x00000200 

#define PL110_CLCD_TIMING0_HBP  (0xFF << 24) 
#define PL110_CLCD_TIMING0_HFP  (0xFF << 16) 
#define PL110_CLCD_TIMING0_HSW  (0xFF << 8) 
#define PL110_CLCD_TIMING0_PPL  (0xFC << 2) 

#define PL110_CLCD_TIMING1_VBP  (0xFF << 24) 
#define PL110_CLCD_TIMING1_VFP  (0xFF << 16) 
#define PL110_CLCD_TIMING1_VSW  (0xFC << 10) 
#define PL110_CLCD_TIMING1_LPP  (0x3FF << 0) 

#define PL110_CLCD_TIMING2_PCD_HI   (0x1F << 27) 
#define PL110_CLCD_TIMING2_BCD  (1 << 26) 
#define PL110_CLCD_TIMING2_CPL  (0x3FF << 16) 
#define PL110_CLCD_TIMING2_IOE  (1 << 14) 
#define PL110_CLCD_TIMING2_IPC  (1 << 13) 
#define PL110_CLCD_TIMING2_IHS  (1 << 12) 
#define PL110_CLCD_TIMING2_IVS  (1 << 11) 
#define PL110_CLCD_TIMING2_ACB  (0x1F << 6) 
#define PL110_CLCD_TIMING2_CLKSEL   (1 << 5) 
#define PL110_CLCD_TIMING2_PCD_LO   (0x1F << 0) 

#define PL110_CLCD_TIMING3_LEE  (1 << 16) 
#define PL110_CLCD_TIMING3_LED  (0x3F << 0) 

#define PL110_CLCD_CONTROL_LCDEN    (1 << 0)
#define PL110_CLCD_CONTROL_LCDBPP1  (0 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP2  (1 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP4  (2 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP8  (3 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP16 (4 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP16_565 (6 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP16_444 (7 << 1) 
#define PL110_CLCD_CONTROL_LCDBPP24 (5 << 1) 
#define PL110_CLCD_CONTROL_LCDBW    (1 << 4) 
#define PL110_CLCD_CONTROL_LCDTFT   (1 << 5) 
#define PL110_CLCD_CONTROL_LCDMONO8 (1 << 6) 
#define PL110_CLCD_CONTROL_LCDDUAL  (1 << 7) 
#define PL110_CLCD_CONTROL_BGR  (1 << 8) 
#define PL110_CLCD_CONTROL_BEBO (1 << 9) 
#define PL110_CLCD_CONTROL_BEPO (1 << 10) 
#define PL110_CLCD_CONTROL_LCDPWR   (1 << 11) 
#define PL110_CLCD_CONTROL_LCDVCOMP_VSYNC   (0 << 12) 
#define PL110_CLCD_CONTROL_LCDVCOMP_BPORCH  (1 << 12) 
#define PL110_CLCD_CONTROL_LCDVCOMP_VIDEO   (2 << 12) 
#define PL110_CLCD_CONTROL_LCDVCOMP_FPORCH  (3 << 12) 
#define PL110_CLCD_CONTROL_LDMAFIFOTIME (1 << 15) 
#define PL110_CLCD_CONTROL_WATERMARK    (1 << 16) 

#define PL110_CONTROL_VGA   PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH
#define PL110_CONTROL_SVGA  PL110_CLCD_CONTROL_LCDTFT | PL110_CLCD_CONTROL_LCDVCOMP_BPORCH

#define PL110_TIMING0_VGA   0x3F1F3F9C
#define PL110_TIMING0_SVGA  0x1313A4C4

#define PL110_TIMING1_VGA   0x090B61DF
#define PL110_TIMING1_SVGA  0x0505F657

#define PL110_TIMING2_VGA   0x067F1800
#define PL110_TIMING2_SVGA  0x071F1800

typedef struct _PL110_CLCD_REGISTERS PL110_CLCD_REGISTERS;
struct _PL110_CLCD_REGISTERS
{
    uint32_t timing0; 
    uint32_t timing1; 
    uint32_t timing2; 
    uint32_t timing3; 
    uint32_t upbase; 
    uint32_t lpbase; 
    uint32_t control; 
    uint32_t imsc; 
    uint32_t ris; 
    uint32_t mis; 
    uint32_t icr; 
    uint32_t upcurr; 
    uint32_t lpcurr; 
 
};
 
 
typedef struct _PL110_FRAMEBUFFER PL110_FRAMEBUFFER;
struct _PL110_FRAMEBUFFER
{
    // Framebuffer Properties
    FRAMEBUFFER_DEVICE framebuffer;
    // PL110 Properties
    uint32_t mode; 
    uint32_t depth; 
    uint32_t width; 
    uint32_t height; 
    uint32_t rotation; 
    // Driver Properties
    uint32_t control; 
    uint32_t timing0; 
    uint32_t timing1; 
    uint32_t timing2; 
    uint32_t timing3; 
    PL110_CLCD_REGISTERS *registers; 
};


FRAMEBUFFER_DEVICE * STDCALL pl110_framebuffer_create_vga(size_t address, char *name, uint32_t rotation, uint32_t width, uint32_t height, uint32_t depth);

FRAMEBUFFER_DEVICE * STDCALL pl110_framebuffer_create_svga(size_t address, char *name, uint32_t rotation, uint32_t width, uint32_t height, uint32_t depth);

uint32_t STDCALL pl110_framebuffer_destroy(FRAMEBUFFER_DEVICE *framebuffer);
 
#ifdef __cplusplus
}
#endif
 
#endif // _ULTIBO_PL110_H