Unit PlatformARMv7L
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Description
Ultibo Platform Interface unit for ARMv7 LPAE
This unit extends the Platform ARMv7 unit to provide support for implementations using the Large Physical Address Extensions (LPAE) to access greater than 4GB of memory in 32-bit environments.
The LPAE defines a new page table descriptor format along with new memory region attributes and memory attribute indirection registers (MAIR0/1) as well as extending the TTBR0, TTBR1 and TTBCR registers with additional information.
The LPAE extensions allow addressing of up to 40 bits of physical address space (1TB) by mapping it into the 32-bit virtual address space.
For 64-bit environments the Platform ARMv8 unit provides the equivalent functionality as LPAE is not required and the processor can address up to 48 bits of address space directly. All functionality not directly related to LPAE is provided from the Platform ARMv7 unit.
Constants
ARMV7L page table level
ARMV7L_PAGE_TABLE_* ARMV7L_PAGE_TABLE_LEVELS = 3;
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ARMV7L page tables shift
ARMV7L_PAGE_TABLES_* ARMV7L_PAGE_TABLES_SHIFT = 12;
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ARMV7L CP15 C2 memory attribute indirection registers 0 and 1
ARMV7L_CP15_C2_MAIR*_ATTR*_* ARMV7L_CP15_C2_MAIR1_ATTR7_SHIFT = 24;
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ARMV7L_CP15_C2_MAIR1_ATTR7_MASK = ($FF shl ARMV7L_CP15_C2_MAIR1_ATTR7_SHIFT);
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ARMV7L_CP15_C2_MAIR1_ATTR6_SHIFT = 16;
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ARMV7L_CP15_C2_MAIR1_ATTR6_MASK = ($FF shl ARMV7L_CP15_C2_MAIR1_ATTR6_SHIFT);
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ARMV7L_CP15_C2_MAIR1_ATTR5_SHIFT = 8;
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ARMV7L_CP15_C2_MAIR1_ATTR5_MASK = ($FF shl ARMV7L_CP15_C2_MAIR1_ATTR5_SHIFT);
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ARMV7L_CP15_C2_MAIR1_ATTR4_SHIFT = 0;
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ARMV7L_CP15_C2_MAIR1_ATTR4_MASK = ($FF shl ARMV7L_CP15_C2_MAIR1_ATTR4_SHIFT);
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ARMV7L_CP15_C2_MAIR0_ATTR3_SHIFT = 24;
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ARMV7L_CP15_C2_MAIR0_ATTR3_MASK = ($FF shl ARMV7L_CP15_C2_MAIR0_ATTR3_SHIFT);
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ARMV7L_CP15_C2_MAIR0_ATTR2_SHIFT = 16;
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ARMV7L_CP15_C2_MAIR0_ATTR2_MASK = ($FF shl ARMV7L_CP15_C2_MAIR0_ATTR2_SHIFT);
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ARMV7L_CP15_C2_MAIR0_ATTR1_SHIFT = 8;
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ARMV7L_CP15_C2_MAIR0_ATTR1_MASK = ($FF shl ARMV7L_CP15_C2_MAIR0_ATTR1_SHIFT);
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ARMV7L_CP15_C2_MAIR0_ATTR0_SHIFT = 0;
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ARMV7L_CP15_C2_MAIR0_ATTR0_MASK = ($FF shl ARMV7L_CP15_C2_MAIR0_ATTR0_SHIFT);
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ARMV7L CP15 C2 memory attribute indirection register values
ARMV7L_CP15_C2_MAIR* | See B4.1.104 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition (These values are from Linux) | |
ARMV7L_CP15_C2_MAIR_STRONGLY_ORDERED = $00;
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Strongly-ordered memory |
ARMV7L_CP15_C2_MAIR_DEVICE = $04;
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Device memory |
ARMV7L_CP15_C2_MAIR_NORMAL_NONCACHED = $44;
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Normal memory, Inner Non-cacheable |
ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_THROUGH = $AA;
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Normal memory, Inner Write-Through Cacheable |
ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_BACK = $EE;
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Normal memory, Inner Write-Back Cacheable |
ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_ALLOCATE = $FF;
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Normal memory, Inner Write-Allocate Cacheable |
| NORMAL_WRITE_BACK, NORMAL_WRITE_THROUGH, NORMAL_NONCACHED, STRONGLY_ORDERED (0xEEAA4400) | |
ARMV7L_CP15_C2_MAIR0_MASK = ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_BACK shl ARMV7L_CP15_C2_MAIR0_ATTR3_SHIFT or ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_THROUGH shl ARMV7L_CP15_C2_MAIR0_ATTR2_SHIFT or ARMV7L_CP15_C2_MAIR_NORMAL_NONCACHED shl ARMV7L_CP15_C2_MAIR0_ATTR1_SHIFT or ARMV7L_CP15_C2_MAIR_STRONGLY_ORDERED shl ARMV7L_CP15_C2_MAIR0_ATTR0_SHIFT;
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| NORMAL_WRITE_ALLOCATE, UNUSED, UNUSED, DEVICE (0xFF000004) | |
ARMV7L_CP15_C2_MAIR1_MASK = ARMV7L_CP15_C2_MAIR_NORMAL_WRITE_ALLOCATE shl ARMV7L_CP15_C2_MAIR1_ATTR7_SHIFT or ARMV7L_CP15_C2_MAIR_DEVICE shl ARMV7L_CP15_C2_MAIR1_ATTR4_SHIFT;
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ARMV7L CP15 C2 translation table base control
ARMV7L_CP15_C2_TTBCR_* ARMV7L_CP15_C2_TTBCR_EAE = (1 shl 31);
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Extended Address Enable (0 Use the 32-bit translation system / 1 Use the 40-bit translation system) |
ARMV7L_CP15_C2_TTBCR_SH1_MASK = (3 shl 28);
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Shareability attribute for memory associated with translation table walks using TTBR1 |
ARMV7L_CP15_C2_TTBCR_SH1_NONSHAREABLE = (0 shl 28);
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Non-shareable |
ARMV7L_CP15_C2_TTBCR_SH1_OUTER_SHAREABLE = (2 shl 28);
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Outer Shareable |
ARMV7L_CP15_C2_TTBCR_SH1_INNER_SHAREABLE = (3 shl 28);
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Inner Shareable |
ARMV7L_CP15_C2_TTBCR_ORGN1_MASK = (3 shl 26);
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Outer cacheability attribute for memory associated with translation table walks using TTBR1 |
ARMV7L_CP15_C2_TTBCR_ORGN1_OUTER_NONCACHED = (0 shl 26);
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Normal memory, Outer Non-cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN1_OUTER_WRITE_ALLOCATE = (1 shl 26);
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Normal memory, Outer Write-Back Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN1_OUTER_WRITE_THROUGH = (2 shl 26);
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Normal memory, Outer Write-Through Cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN1_OUTER_WRITE_BACK = (3 shl 26);
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Normal memory, Outer Write-Back no Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN1_MASK = (3 shl 24);
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Inner cacheability attribute for memory associated with translation table walks using TTBR1 |
ARMV7L_CP15_C2_TTBCR_IRGN1_INNER_NONCACHED = (0 shl 24);
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Normal memory, Inner Non-cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN1_INNER_WRITE_ALLOCATE = (1 shl 24);
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Normal memory, Inner Write-Back Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN1_INNER_WRITE_THROUGH = (2 shl 24);
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Normal memory, Inner Write-Through Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN1_INNER_WRITE_BACK = (3 shl 24);
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Normal memory, Inner Write-Back no Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_EPD1 = (1 shl 23);
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Translation table walk disable for translations using TTBR1 (0 Perform translation table walks using TTBR1 / 1 A TLB miss on an address that is translated using TTBR1 generates a Translation fault) |
ARMV7L_CP15_C2_TTBCR_A1 = (1 shl 22);
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Selects whether TTBR0 or TTBR1 defines the ASID (0 TTBR0.ASID defines the ASID / 1 TTBR1.ASID defines the ASID) |
ARMV7L_CP15_C2_TTBCR_T1SZ_MASK = (7 shl 16);
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The size offset of the memory region addressed by TTBR1 |
ARMV7L_CP15_C2_TTBCR_SH0_MASK = (3 shl 12);
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Shareability attribute for memory associated with translation table walks using TTBR0 |
ARMV7L_CP15_C2_TTBCR_SH0_NONSHAREABLE = (0 shl 12);
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Non-shareable |
ARMV7L_CP15_C2_TTBCR_SH0_OUTER_SHAREABLE = (2 shl 12);
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Outer Shareable |
ARMV7L_CP15_C2_TTBCR_SH0_INNER_SHAREABLE = (3 shl 12);
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Inner Shareable |
ARMV7L_CP15_C2_TTBCR_ORGN0_MASK = (3 shl 10);
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Outer cacheability attribute for memory associated with translation table walks using TTBR0 |
ARMV7L_CP15_C2_TTBCR_ORGN0_OUTER_NONCACHED = (0 shl 10);
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Normal memory, Outer Non-cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN0_OUTER_WRITE_ALLOCATE = (1 shl 10);
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Normal memory, Outer Write-Back Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN0_OUTER_WRITE_THROUGH = (2 shl 10);
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Normal memory, Outer Write-Through Cacheable |
ARMV7L_CP15_C2_TTBCR_ORGN0_OUTER_WRITE_BACK = (3 shl 10);
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Normal memory, Outer Write-Back no Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN0_MASK = (3 shl 8);
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Inner cacheability attribute for memory associated with translation table walks using TTBR0 |
ARMV7L_CP15_C2_TTBCR_IRGN0_INNER_NONCACHED = (0 shl 8);
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Normal memory, Inner Non-cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN0_INNER_WRITE_ALLOCATE = (1 shl 8);
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Normal memory, Inner Write-Back Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN0_INNER_WRITE_THROUGH = (2 shl 8);
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Normal memory, Inner Write-Through Cacheable |
ARMV7L_CP15_C2_TTBCR_IRGN0_INNER_WRITE_BACK = (3 shl 8);
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Normal memory, Inner Write-Back no Write-Allocate Cacheable |
ARMV7L_CP15_C2_TTBCR_EPD0 = (1 shl 7);
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Translation table walk disable for translations using TTBR0 (See ARMV7L_CP15_C2_TTBCR_EPD1) |
ARMV7L_CP15_C2_TTBCR_T0SZ_MASK = (7 shl 0);
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The size offset of the memory region addressed by TTBR0 |
ARMV7L_CP15_C2_TTBCR_T0SZ_4GB = (0 shl 0);
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| TTBR1 Inner Write Allocate, Outer Write Allocate, Inner Shareable | |
ARMV7L_CP15_C2_TTBCR_MASK = ARMV7L_CP15_C2_TTBCR_IRGN0_INNER_WRITE_ALLOCATE or ARMV7L_CP15_C2_TTBCR_ORGN0_OUTER_WRITE_ALLOCATE or ARMV7L_CP15_C2_TTBCR_SH0_INNER_SHAREABLE or ARMV7L_CP15_C2_TTBCR_IRGN1_INNER_WRITE_ALLOCATE or ARMV7L_CP15_C2_TTBCR_ORGN1_OUTER_WRITE_ALLOCATE or ARMV7L_CP15_C2_TTBCR_SH1_INNER_SHAREABLE;
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ARMV7L CP15 C2 translation table base registers 0 and 1
ARMV7L_CP15_C2_TTBR_* ARMV7L_CP15_C2_TTBR_ASID_MASK = ($F shl 48);
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An ASID for the translation table base address (The TTBCR.A1 field selects either TTBR0.ASID or TTBR1.ASID) |
ARMV7L_CP15_C2_TTBR_BASE_MASK = $000000FFFFFFFFE0;
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Translation table base address, bits[39:5] (Only correct if TTBCR.TxSZ is 0) |
ARMV7L_CP15_C2_TTBR_BASE_MASK_HI = $000000FF;
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ARMV7L_CP15_C2_TTBR_BASE_MASK_LO = $FFFFFFE0;
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ARMV7L hardware page table descriptor
ARMV7L_*_BASE_MASK | See B3.6 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition | |
| Level 1 Page Table contains up to 512 64bit (8 byte) entries for a total size of 4KB | |
| Level 2 Page Table contains up to 512 64bit (8 byte) entries for a total size of 4KB | |
| Level 3 Page Table contains 512 64bit (8 byte) entries for a total size of 4KB | |
ARMV7L_LARGESECTION_BASE_MASK = $C0000000;
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1GB Large Sections |
ARMV7L_SECTION_BASE_MASK = $FFE00000;
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2MB Sections |
ARMV7L_PAGE_BASE_MASK = $FFFFF000;
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4KB Pages |
ARMV7L_DESCRIPTOR_BASE_MASK = $FFFFF000;
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ARMV7L hardware descriptor type
ARMV7L_DESCRIPTOR_TYPE_* | See B3.6.1 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition | |
ARMV7L_DESCRIPTOR_TYPE_INVALID = (0 shl 0);
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00 - Invalid at all levels |
ARMV7L_DESCRIPTOR_TYPE_BLOCK = (1 shl 0);
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01 - Block at level 1 and 2 |
ARMV7L_DESCRIPTOR_TYPE_TABLE = (3 shl 0);
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11 - Table at level 1 and 2 |
ARMV7L_DESCRIPTOR_TYPE_RESERVED = (1 shl 0);
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01 - Reserved at level 3 |
ARMV7L_DESCRIPTOR_TYPE_PAGE = (3 shl 0);
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11 - Page at level 3 |
ARMV7L_DESCRIPTOR_TYPE_MASK = (3 shl 0);
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ARMV7L hardware descriptor type output
ARMV7L_DESCRIPTOR_*_OUTPUT_* | See B3.6.1 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition | |
ARMV7L_DESCRIPTOR_L1_OUTPUT_MASK = $000000FFC0000000;
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Output address bits[39:30] |
ARMV7L_DESCRIPTOR_L2_OUTPUT_MASK = $000000FFFFE00000;
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Output address bits[39:21] |
ARMV7L_DESCRIPTOR_L3_OUTPUT_MASK = $000000FFFFFFF000;
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Output address bits[39:12] |
ARMV7L_DESCRIPTOR_NEXT_TABLE_MASK = $000000FFFFFFF000;
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Next-level table address bits[39:12] (The first-level descriptor returns the address of the second-level table, The second-level descriptor returns the address of the third-level table) |
ARMV7L long-descriptor table, block and page descriptor
ARMV7L_DESCRIPTOR_ATTRIBUTE_* | See B3.6.2 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition | |
ARMV7L_DESCRIPTOR_ATTRIBUTE_NSTABLE = (1 shl 63);
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For memory accesses from Secure state, specifies the security level for subsequent levels of lookup (For memory accesses from Non-secure state, this bit is ignored) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_APTABLE_MASK = (3 shl 61);
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Access permissions limit for subsequent levels of lookup |
ARMV7L_DESCRIPTOR_ATTRIBUTE_APTABLE_NONE = (0 shl 61);
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No effect on permissions in subsequent levels of lookup |
ARMV7L_DESCRIPTOR_ATTRIBUTE_APTABLE_NOACCESS_PL0 = (1 shl 61);
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Access at PL0 not permitted, regardless of permissions in subsequent levels of lookup |
ARMV7L_DESCRIPTOR_ATTRIBUTE_APTABLE_NOWRITE_ALL = (2 shl 61);
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Write access not permitted, at any privilege level, regardless of permissions in subsequent levels of lookup |
ARMV7L_DESCRIPTOR_ATTRIBUTE_APTABLE_NOWRITE_ALL_NOREAD_PL0 = (3 shl 61);
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Regardless of permissions in subsequent levels of lookup write access not permitted, at any privilege level, read access not permitted at PL0 |
ARMV7L_DESCRIPTOR_ATTRIBUTE_XNTABLE = (1 shl 60);
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XN limit for subsequent levels of lookup (when XNTable is set to 0 it has no effect) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_PXNTABLE = (1 shl 59);
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PXN limit for subsequent levels of lookup (when PXNTable is set to 0 it has no effect) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_XN = (1 shl 54);
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The Execute-never bit. Determines whether the region is executable |
ARMV7L_DESCRIPTOR_ATTRIBUTE_PXN = (1 shl 53);
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The Privileged execute-never bit. Determines whether the region is executable at PL1 |
ARMV7L_DESCRIPTOR_ATTRIBUTE_CONTIGUOUS = (1 shl 52);
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A hint bit indicating that 16 adjacent translation table entries point to contiguous memory regions |
ARMV7L_DESCRIPTOR_ATTRIBUTE_NG = (1 shl 11);
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The not global bit. Determines how the translation is marked in the TLB |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AF = (1 shl 10);
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The Access flag |
ARMV7L_DESCRIPTOR_ATTRIBUTE_SH_MASK = (3 shl 8);
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Shareability field |
ARMV7L_DESCRIPTOR_ATTRIBUTE_SH_NONSHAREABLE = (0 shl 8);
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Non-shareable |
ARMV7L_DESCRIPTOR_ATTRIBUTE_SH_OUTER_SHAREABLE = (2 shl 8);
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Outer Shareable |
ARMV7L_DESCRIPTOR_ATTRIBUTE_SH_INNER_SHAREABLE = (3 shl 8);
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Inner Shareable |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_MASK = (3 shl 6);
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Access Permissions bits (Note: There is no No Access permission in the AP[2:1] model) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_READWRITE_PL1 = (0 shl 6);
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Read/write, at PL1 |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_READWRITE_ALL = (1 shl 6);
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Read/write, at any privilege level |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_READONLY_PL1 = (2 shl 6);
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Read-only, at PL1 |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_READONLY_ALL = (3 shl 6);
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Read-only, at any privilege level |
ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_NONE_ALL = ARMV7L_DESCRIPTOR_ATTRIBUTE_AP_READONLY_PL1;
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No access, at any privilege level (No such permission exists, see note above) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_NS = (1 shl 5);
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Non-secure bit. For memory accesses from Secure state, specifies whether the output address is in Secure or Non-secure memory (For memory accesses from Non-secure state, this bit is ignored) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_MASK = (7 shl 2);
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Memory attributes index field, for the indicated Memory Attribute Indirection Register (MAIR) |
ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR0 = (0 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR1 = (1 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR2 = (2 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR3 = (3 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR4 = (4 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR5 = (5 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR6 = (6 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR7 = (7 shl 2);
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ARMV7L_DESCRIPTOR_ATTRIBUTE_MASK = $FFF0000000000FFC;
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Upper Attributes bits[63:52] Lower Attributes bits[11:9] |
ARMV7L descriptor cache value
ARMV7L_DESCRIPTOR_CACHE_* | See B4.1.104 of the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition (These values are from Linux) | |
ARMV7L_DESCRIPTOR_CACHE_STRONGLY_ORDERED = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR0;
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Strongly Ordered |
ARMV7L_DESCRIPTOR_CACHE_NORMAL_NONCACHED = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR1;
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Normal Noncacheable (Shared if SH bits set) |
ARMV7L_DESCRIPTOR_CACHE_NORMAL_WRITE_THROUGH = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR2;
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Normal Write Through (Shared if SH bits set) |
ARMV7L_DESCRIPTOR_CACHE_NORMAL_WRITE_BACK = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR3;
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Normal Write Back (Shared if SH bits set) |
ARMV7L_DESCRIPTOR_CACHE_DEVICE = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR4;
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Device |
ARMV7L_DESCRIPTOR_CACHE_UNUSED1 = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR5;
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Not currently used |
ARMV7L_DESCRIPTOR_CACHE_UNUSED2 = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR6;
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Not currently used |
ARMV7L_DESCRIPTOR_CACHE_NORMAL_WRITE_ALLOCATE = ARMV7L_DESCRIPTOR_ATTRIBUTE_ATTRINDX_ATTR7;
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Normal Write Allocate (Shared if SH bits set) |
Type definitions
None defined
Public variables
None defined
Function declarations
Initialization functions
procedure ARMv7LInit;
Description: To be documented
| Note | None documented |
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ARMv7L platform functions
procedure ARMv7LMMUInit;
Description: To be documented
| Note | None documented |
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procedure ARMv7LPageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU
| Note | None documented |
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procedure ARMv7LPageTableGetEntry(Address:PtrUInt; var Entry:TPageTableEntry);
Description: Get and Decode the entry in the Page Table that corresponds to the supplied virtual address
| Note | None documented |
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function ARMv7LPageTableSetEntry(const Entry:TPageTableEntry):LongWord;
Description: Encode and Set an entry in the Page Table that corresponds to the supplied virtual address
| Note | None documented |
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ARMv7L helper functions
procedure ARMv7LStartMMU;
Description: To be documented
| Note | None documented |
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function ARMv7LGetPageTableLevel1(Address:PtrUInt):UInt64;
Description: Get the descriptor for a Level 1 Page Table (1GB)
| Note | None documented |
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function ARMv7LSetPageTableLevel1(Address,TableAddress:PtrUInt; Flags:UInt64):Boolean;
Description: Set the descriptor for a Level 1 Page Table (1GB)
| Note | Caller must call ARMv7InvalidateTLB after changes if MMU is enabled |
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function ARMv7LGetPageTableLevel2(Address:PtrUInt):UInt64;
Description: Get the descriptor for a Level 2 Page Table (2MB)
| Note | None documented |
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function ARMv7LSetPageTableLevel2(Address,TableAddress:PtrUInt; Flags:UInt64):Boolean;
Description: Set the descriptor for a Level 2 Page Table (2MB)
| Note | Caller must call ARMv7InvalidateTLB after changes if MMU is enabled |
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function ARMv7LGetPageTablePage(Address:PtrUInt):UInt64;
Description: Get the descriptor for a Page Table Page (4KB)
| Note | None documented |
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function ARMv7LSetPageTablePage(Address:PtrUInt; PhysicalRange:LongWord; PhysicalAddress:PtrUInt; Flags:UInt64):Boolean;
Description: Set the descriptor for a Page Table Page (4KB)
| Note | Caller must call ARMv7InvalidateTLB after changes if MMU is enabled |
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function ARMv7LGetPageTableSection(Address:PtrUInt):UInt64;
Description: Get the descriptor for a Page Table Section (2MB)
| Note | None documented |
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function ARMv7LSetPageTableSection(Address:PtrUInt; PhysicalRange:LongWord; PhysicalAddress:PtrUInt; Flags:UInt64):Boolean;
Description: Set the descriptor for a Page Table Section (2MB)
| Note | Caller must call ARMv7InvalidateTLB after changes if MMU is enabled |
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function ARMv7LGetPageTableLargeSection(Address:PtrUInt):UInt64;
Description: Get the descriptor for a Page Table Large Section (1GB)
| Note | None documented |
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function ARMv7LSetPageTableLargeSection(Address:PtrUInt; PhysicalRange:LongWord; PhysicalAddress:PtrUInt; Flags:UInt64):Boolean;
Description: Set the descriptor for a Page Table Large Section (1GB)
| Note | Caller must call ARMv7InvalidateTLB after changes if MMU is enabled |
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