Unit PlatformARMv7

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`ARMV7_CP15_C0_CLID_LOUU_MASK = (7 shl 27);`	Level of Unification Uniprocessor for the cache hierarchy
`ARMV7_CP15_C0_CLID_LOC_MASK = (7 shl 24);`	Level of Coherency for the cache hierarchy
`ARMV7_CP15_C0_CLID_LOUIS_MASK = (7 shl 21);`	Level of Unification Inner Shareable for the cache hierarchy
`ARMV7_CP15_C0_CLID_CTYPE7_MASK = (7 shl 18);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE7_NONE = (0 shl 18);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE7_INSTRUCTION = (1 shl 18);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE7_DATA = (2 shl 18);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE7_SEPARATE = (3 shl 18);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE7_UNIFIED = (4 shl 18);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE6_MASK = (7 shl 15);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE6_NONE = (0 shl 15);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE6_INSTRUCTION = (1 shl 15);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE6_DATA = (2 shl 15);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE6_SEPARATE = (3 shl 15);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE6_UNIFIED = (4 shl 15);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE5_MASK = (7 shl 12);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE5_NONE = (0 shl 12);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE5_INSTRUCTION = (1 shl 12);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE5_DATA = (2 shl 12);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE5_SEPARATE = (3 shl 12);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE5_UNIFIED = (4 shl 12);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE4_MASK = (7 shl 9);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE4_NONE = (0 shl 9);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE4_INSTRUCTION = (1 shl 9);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE4_DATA = (2 shl 9);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE4_SEPARATE = (3 shl 9);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE4_UNIFIED = (4 shl 9);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE3_MASK = (7 shl 6);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE3_NONE = (0 shl 6);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE3_INSTRUCTION = (1 shl 6);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE3_DATA = (2 shl 6);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE3_SEPARATE = (3 shl 6);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE3_UNIFIED = (4 shl 6);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE2_MASK = (7 shl 3);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE2_NONE = (0 shl 3);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE2_INSTRUCTION = (1 shl 3);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE2_DATA = (2 shl 3);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE2_SEPARATE = (3 shl 3);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE2_UNIFIED = (4 shl 3);`	Unified cache

`ARMV7_CP15_C0_CLID_CTYPE1_MASK = (7 shl 0);`	Cache Type fields. Indicate the type of cache implemented at each level, from Level 1 up to a maximum of seven levels of cache hierarchy.
`ARMV7_CP15_C0_CLID_CTYPE1_NONE = (0 shl 0);`	No cache
`ARMV7_CP15_C0_CLID_CTYPE1_INSTRUCTION = (1 shl 0);`	Instruction cache only
`ARMV7_CP15_C0_CLID_CTYPE1_DATA = (2 shl 0);`	Data cache only
`ARMV7_CP15_C0_CLID_CTYPE1_SEPARATE = (3 shl 0);`	Separate instruction and data caches
`ARMV7_CP15_C0_CLID_CTYPE1_UNIFIED = (4 shl 0);`	Unified cache

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ARMv7 CP15 C0 cache size selection ARMV7_CP15_C0_CSSEL_*

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ARMv7 CP15 C1 control ARMV7_CP15_C1_*

`ARMV7_CP15_C1_TE_BIT = (1 shl 30);`	Thumb Exception enable. This bit enabled exceptions to be taken in Thumb state when set to 1 (Default 0).
`ARMV7_CP15_C1_AFE_BIT = (1 shl 29);`	Access Flag Enable bit. This bit enables use of the AP[0] bit in the translation table descriptors as an access flag when set to 1 (Default 0).
`ARMV7_CP15_C1_TRE_BIT = (1 shl 28);`	TEX remap enabled when set to 1 (TEX[2:1] become page table bits for OS) (Default 0).
`ARMV7_CP15_C1_NMFI_BIT = (1 shl 27);`	Non-maskable Fast Interrupts enabled when set to 1 (Default 0)
`ARMV7_CP15_C1_EE_BIT = (1 shl 25);`	CPSR E bit is set to 1 on an exception when set to 1 (Default 0)
`ARMV7_CP15_C1_VE_BIT = (1 shl 24);`	Interrupt vectors are defined by the VIC interface when set to 1 (Default 0)
`ARMV7_CP15_C1_U_BIT = (1 shl 22);`	Unaligned data access support enabled when set to 1 (Always 1 in ARMv7). The processor permits unaligned loads and stores and support for mixed endian data is enabled.
`ARMV7_CP15_C1_FI_BIT = (1 shl 21);`	Low interrupt latency configuration enabled when set to 1 (Default 0)
`ARMV7_CP15_C1_UWXN_BIT = (1 shl 20);`	Unprivileged write permission implies Execute Never (XN) when set to 1 (Default 0)(Cortext-A7 MPCore)
`ARMV7_CP15_C1_WXN_BIT= (1 shl 19);`	Write permission implies Execute Never (XN) when set to 1 (Default 0)(Cortext-A7 MPCore)
`ARMV7_CP15_C1_HA_BIT = (1 shl 17);`	Hardware Access Flag Enable bit. If the implementation provides hardware management of the access flag this bit enables the access flag management (Default 0).
`ARMV7_CP15_C1_RR_BIT = (1 shl 14);`	Predictable cache replacement strategy by round-robin replacement when set to 1 (Default 0).
`ARMV7_CP15_C1_V_BIT = (1 shl 13);`	High exception vectors selected when set to 1, address range = 0xFFFF0000-0xFFFF001C (Default 0).
`ARMV7_CP15_C1_I_BIT = (1 shl 12);`	L1 Instruction Cache enabled when set to 1 (Default 0)
`ARMV7_CP15_C1_Z_BIT = (1 shl 11);`	Branch prediction enabled when set to 1 (Default 0)(Always Enabled on Cortext-A7 MPCore)
`ARMV7_CP15_C1_SW_BIT = (1 shl 10);`	SWP/SWPB Enable bit. This bit enables the use of SWP and SWPB instructions when set to 1 (Default 0).
`ARMV7_CP15_C1_B_BIT = (1 shl 7);`	Big-endian word-invariant memory system when set to 1 (Always 0 in ARMv7)
`ARMV7_CP15_C1_C_BIT = (1 shl 2);`	L1 Data cache enabled when set to 1 (Default 0)
`ARMV7_CP15_C1_A_BIT = (1 shl 1);`	Strict alignment fault checking enabled when set to 1 (Default 0)
`ARMV7_CP15_C1_M_BIT = (1 shl 0);`	MMU enabled when set to 1 (Default 0)

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ARMv7 CP15 C1 auxiliary control ARMV7_CP15_C1_AUX_*

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ARMv7 CP15 C1 coprocessor access control ARMV7_CP15_C1_CP*

`ARMV7_CP15_C1_COPRO_ASEDIS = (1 shl 31);`	Disable Advanced SIMD Functionality when set to 1 (Default 0)
`ARMV7_CP15_C1_COPRO_D32DIS = (1 shl 30);`	Disable use of D16-D31 of the VFP register file when set to 1 (Default 0)

`ARMV7_CP15_C1_CP0_NONE = (0 shl 0);`	Access denied (Default)
`ARMV7_CP15_C1_CP0_SYS = (1 shl 0);`	Privileged mode access only
`ARMV7_CP15_C1_CP0_USER = (3 shl 0);`	Privileged and User mode access

`ARMV7_CP15_C1_CP1_NONE = (0 shl 2);`	Access denied (Default)
`ARMV7_CP15_C1_CP1_SYS = (1 shl 2);`	Privileged mode access only
`ARMV7_CP15_C1_CP1_USER = (3 shl 2);`	Privileged and User mode access

`ARMV7_CP15_C1_CP2_NONE = (0 shl 4);`	Access denied (Default)
`ARMV7_CP15_C1_CP2_SYS = (1 shl 4);`	Privileged mode access only
`ARMV7_CP15_C1_CP2_USER = (3 shl 4);`	Privileged and User mode access

`ARMV7_CP15_C1_CP3_NONE = (0 shl 6);`	Access denied (Default)
`ARMV7_CP15_C1_CP3_SYS = (1 shl 6);`	Privileged mode access only
`ARMV7_CP15_C1_CP3_USER = (3 shl 6);`	Privileged and User mode access

`ARMV7_CP15_C1_CP4_NONE = (0 shl 8);`	Access denied (Default)
`ARMV7_CP15_C1_CP4_SYS = (1 shl 8);`	Privileged mode access only
`ARMV7_CP15_C1_CP4_USER = (3 shl 8);`	Privileged and User mode access

`ARMV7_CP15_C1_CP5_NONE = (0 shl 10);`	Access denied (Default)
`ARMV7_CP15_C1_CP5_SYS = (1 shl 10);`	Privileged mode access only
`ARMV7_CP15_C1_CP5_USER = (3 shl 10);`	Privileged and User mode access

`ARMV7_CP15_C1_CP6_NONE = (0 shl 12);`	Access denied (Default)
`ARMV7_CP15_C1_CP6_SYS = (1 shl 12);`	Privileged mode access only
`ARMV7_CP15_C1_CP6_USER = (3 shl 12);`	Privileged and User mode access

`ARMV7_CP15_C1_CP7_NONE = (0 shl 14);`	Access denied (Default)
`ARMV7_CP15_C1_CP7_SYS = (1 shl 14);`	Privileged mode access only
`ARMV7_CP15_C1_CP7_USER = (3 shl 14);`	Privileged and User mode access

`ARMV7_CP15_C1_CP8_NONE = (0 shl 16);`	Access denied (Default)
`ARMV7_CP15_C1_CP8_SYS = (1 shl 16);`	Privileged mode access only
`ARMV7_CP15_C1_CP8_USER = (3 shl 16);`	Privileged and User mode access

`ARMV7_CP15_C1_CP9_NONE = (0 shl 18);`	Access denied (Default)
`ARMV7_CP15_C1_CP9_SYS = (1 shl 18);`	Privileged mode access only
`ARMV7_CP15_C1_CP9_USER = (3 shl 18);`	Privileged and User mode access

`ARMV7_CP15_C1_CP10_NONE = (0 shl 20);`	Access denied (Default)
`ARMV7_CP15_C1_CP10_SYS = (1 shl 20);`	Privileged mode access only
`ARMV7_CP15_C1_CP10_USER = (3 shl 20);`	Privileged and User mode access

`ARMV7_CP15_C1_CP11_NONE = (0 shl 22);`	Access denied (Default)
`ARMV7_CP15_C1_CP11_SYS = (1 shl 22);`	Privileged mode access only
`ARMV7_CP15_C1_CP11_USER = (3 shl 22);`	Privileged and User mode access

`ARMV7_CP15_C1_CP12_NONE = (0 shl 24);`	Access denied (Default)
`ARMV7_CP15_C1_CP12_SYS = (1 shl 24);`	Privileged mode access only
`ARMV7_CP15_C1_CP12_USER = (3 shl 24);`	Privileged and User mode access

`ARMV7_CP15_C1_CP13_NONE = (0 shl 26);`	Access denied (Default)
`ARMV7_CP15_C1_CP13_SYS = (1 shl 26);`	Privileged mode access only
`ARMV7_CP15_C1_CP13_USER = (3 shl 26);`	Privileged and User mode access
Coprocessors CP14 (Debug Control) and CP15 (System Control) are not affected by the Coprocessor Access Control Register

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ARMv7 CP15 C1 secure configuration ARMV7_CP15_C1_SCR_*

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ARMv7 CP15 C2 translation table base ARMV7_CP15_C2_TTBR_*

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ARMv7 CP15 C3 domain access control ARMV7_CP15_C3_DOMAIN*

`ARMV7_CP15_C3_DOMAIN0_NONE = (0 shl 0);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN0_CLIENT = (1 shl 0);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN0_MANAGER = (3 shl 0);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN1_NONE = (0 shl 2);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN1_CLIENT = (1 shl 2);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN1_MANAGER = (3 shl 2);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN2_NONE = (0 shl 4);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN2_CLIENT = (1 shl 4);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN2_MANAGER = (3 shl 4);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN3_NONE = (0 shl 6);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN3_CLIENT = (1 shl 6);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN3_MANAGER = (3 shl 6);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN4_NONE = (0 shl 8);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN4_CLIENT = (1 shl 8);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN4_MANAGER = (3 shl 8);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN5_NONE = (0 shl 10);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN5_CLIENT = (1 shl 10);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN5_MANAGER = (3 shl 10);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN6_NONE = (0 shl 12);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN6_CLIENT = (1 shl 12);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN6_MANAGER = (3 shl 12);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN7_NONE = (0 shl 14);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN7_CLIENT = (1 shl 14);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN7_MANAGER = (3 shl 14);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN8_NONE = (0 shl 16);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN8_CLIENT = (1 shl 16);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN8_MANAGER = (3 shl 16);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN9_NONE = (0 shl 18);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN9_CLIENT = (1 shl 18);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN9_MANAGER = (3 shl 18);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN10_NONE = (0 shl 20);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN10_CLIENT = (1 shl 20);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN10_MANAGER = (3 shl 20);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN11_NONE = (0 shl 22);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN11_CLIENT = (1 shl 22);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN11_MANAGER = (3 shl 22);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN12_NONE = (0 shl 24);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN12_CLIENT = (1 shl 24);`	Client, Accesses are checked against the access permission bits in the TLB entr
`ARMV7_CP15_C3_DOMAIN12_MANAGER = (3 shl 24);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN13_NONE = (0 shl 26);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN13_CLIENT = (1 shl 26);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN13_MANAGER = (3 shl 26);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN14_NONE = (0 shl 28);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN14_CLIENT = (1 shl 28);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN14_MANAGER = (3 shl 28);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

`ARMV7_CP15_C3_DOMAIN15_NONE = (0 shl 30);`	No access, Any access generates a domain fault (Default)
`ARMV7_CP15_C3_DOMAIN15_CLIENT = (1 shl 30);`	Client, Accesses are checked against the access permission bits in the TLB entry
`ARMV7_CP15_C3_DOMAIN15_MANAGER = (3 shl 30);`	Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated

[Expand]

ARMv7 CP15 C10 primary region remap ARMV7_CP15_C10_PRRR_*

`ARMV7_CP15_C10_PRRR_NOS7 = (1 shl 31);`	Outer Shareable property mapping for memory attributes 7, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS6 = (1 shl 30);`	Outer Shareable property mapping for memory attributes 6, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS5 = (1 shl 29);`	Outer Shareable property mapping for memory attributes 5, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS4 = (1 shl 28);`	Outer Shareable property mapping for memory attributes 4, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS3 = (1 shl 27);`	Outer Shareable property mapping for memory attributes 3, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS2 = (1 shl 26);`	Outer Shareable property mapping for memory attributes 2, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS1 = (1 shl 25);`	Outer Shareable property mapping for memory attributes 1, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NOS0 = (1 shl 24);`	Outer Shareable property mapping for memory attributes 0, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C10_PRRR_NS1 = (1 shl 19);`	Mapping of S = 1 attribute for Normal memory (0 Not Sharable/1 Shareable)
`ARMV7_CP15_C10_PRRR_NS0 = (1 shl 18);`	Mapping of S = 0 attribute for Normal memory (0 Not Sharable/1 Shareable)
`ARMV7_CP15_C10_PRRR_DS1 = (1 shl 17);`	Mapping of S = 1 attribute for Device memory (This field has no significance in the Cortex-A7)
`ARMV7_CP15_C10_PRRR_DS0 = (1 shl 16);`	Mapping of S = 0 attribute for Device memory (This field has no significance in the Cortex-A7)
`ARMV7_CP15_C10_PRRR_TR7_STRONGLY_ORDERED = (0 shl 14);`	Primary TEX mapping for memory attributes 7 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR7_DEVICE = (1 shl 14);`	Primary TEX mapping for memory attributes 7 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR7_NORMAL = (2 shl 14);`	Primary TEX mapping for memory attributes 7 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR6_STRONGLY_ORDERED = (0 shl 12);`	Primary TEX mapping for memory attributes 6 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR6_DEVICE = (1 shl 12);`	Primary TEX mapping for memory attributes 6 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR6_NORMAL = (2 shl 12);`	Primary TEX mapping for memory attributes 6 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR5_STRONGLY_ORDERED = (0 shl 10);`	Primary TEX mapping for memory attributes 5 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR5_DEVICE = (1 shl 10);`	Primary TEX mapping for memory attributes 5 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR5_NORMAL = (2 shl 10);`	Primary TEX mapping for memory attributes 5 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR4_STRONGLY_ORDERED = (0 shl 8);`	Primary TEX mapping for memory attributes 4 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR4_DEVICE = (1 shl 8);`	Primary TEX mapping for memory attributes 4 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR4_NORMAL = (2 shl 8);`	Primary TEX mapping for memory attributes 4 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR3_STRONGLY_ORDERED = (0 shl 6);`	Primary TEX mapping for memory attributes 3 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR3_DEVICE = (1 shl 6);`	Primary TEX mapping for memory attributes 3 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR3_NORMAL = (2 shl 6);`	Primary TEX mapping for memory attributes 3 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR2_STRONGLY_ORDERED = (0 shl 4);`	Primary TEX mapping for memory attributes 2 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR2_DEVICE = (1 shl 4);`	Primary TEX mapping for memory attributes 2 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR2_NORMAL = (2 shl 4);`	Primary TEX mapping for memory attributes 2 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR1_STRONGLY_ORDERED = (0 shl 2);`	Primary TEX mapping for memory attributes 1 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR1_DEVICE = (1 shl 2);`	Primary TEX mapping for memory attributes 1 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR1_NORMAL = (2 shl 2);`	Primary TEX mapping for memory attributes 1 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR0_STRONGLY_ORDERED = (0 shl 0);`	Primary TEX mapping for memory attributes 0 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR0_DEVICE = (1 shl 0);`	Primary TEX mapping for memory attributes 0 (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_PRRR_TR0_NORMAL = (2 shl 0);`	Primary TEX mapping for memory attributes 0 (The value of the TEX[0], C and B bits)

`ARMV7_CP15_C10_PRRR_MASK = ARMV7_CP15_C10_PRRR_NOS7 or ARMV7_CP15_C10_PRRR_NOS6 or ARMV7_CP15_C10_PRRR_NOS5 or ARMV7_CP15_C10_PRRR_NOS4`	TR0 to TR7 Inner Shareable

`or ARMV7_CP15_C10_PRRR_NOS3 or ARMV7_CP15_C10_PRRR_NOS2 or ARMV7_CP15_C10_PRRR_NOS1 or ARMV7_CP15_C10_PRRR_NOS0`

`or ARMV7_CP15_C10_PRRR_NS1 or ARMV7_CP15_C10_PRRR_DS1`	S bit controls Shareable for Normal and Device memory

`or ARMV7_CP15_C10_PRRR_TR0_STRONGLY_ORDERED`	TR0 is Strongly Ordered

`or ARMV7_CP15_C10_PRRR_TR1_NORMAL or ARMV7_CP15_C10_PRRR_TR2_NORMAL or ARMV7_CP15_C10_PRRR_TR3_NORMAL`	TR1/2/3 are Normal

`or ARMV7_CP15_C10_PRRR_TR4_DEVICE`	TR4 is Device

`or ARMV7_CP15_C10_PRRR_TR7_NORMAL;`	TR7 is Normal

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ARMv7 CP15 C10 normal memory remap ARMV7_CP15_C10_NMRR_*

`ARMV7_CP15_C10_NMRR_OR7_NONCACHED = (0 shl 30);`	Outer Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR7_WRITE_ALLOCATE = (1 shl 30);`	Outer Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR7_WRITE_THROUGH = (2 shl 30);`	Outer Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR7_WRITE_BACK = (3 shl 30);`	Outer Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits
`ARMV7_CP15_C10_NMRR_OR6_NONCACHED = (0 shl 28);`	Outer Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR6_WRITE_ALLOCATE = (1 shl 28);`	Outer Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR6_WRITE_THROUGH = (2 shl 28);`	Outer Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR6_WRITE_BACK = (3 shl 28);`	Outer Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR5_NONCACHED = (0 shl 26);`	Outer Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR5_WRITE_ALLOCATE = (1 shl 26);`	Outer Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR5_WRITE_THROUGH = (2 shl 26);`	Outer Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR5_WRITE_BACK = (3 shl 26);`	Outer Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR4_NONCACHED = (0 shl 24);`	Outer Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR4_WRITE_ALLOCATE = (1 shl 24);`	Outer Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR4_WRITE_THROUGH = (2 shl 24);`	Outer Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR4_WRITE_BACK = (3 shl 24);`	Outer Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR3_NONCACHED = (0 shl 22);`	Outer Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR3_WRITE_ALLOCATE = (1 shl 22);`	Outer Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR3_WRITE_THROUGH = (2 shl 22);`	Outer Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR3_WRITE_BACK = (3 shl 22);`	Outer Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR2_NONCACHED = (0 shl 20);`	Outer Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR2_WRITE_ALLOCATE = (1 shl 20);`	Outer Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR2_WRITE_THROUGH = (2 shl 20);`	Outer Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR2_WRITE_BACK = (3 shl 20);`	Outer Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR1_NONCACHED = (0 shl 18);`	Outer Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR1_WRITE_ALLOCATE = (1 shl 18);`	Outer Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR1_WRITE_THROUGH = (2 shl 18);`	Outer Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR1_WRITE_BACK = (3 shl 18);`	Outer Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR0_NONCACHED = (0 shl 16);`	Outer Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR0_WRITE_ALLOCATE = (1 shl 16);`	Outer Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR0_WRITE_THROUGH = (2 shl 16);`	Outer Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_OR0_WRITE_BACK = (3 shl 16);`	Outer Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR7_NONCACHED = (0 shl 14);`	Inner Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR7_WRITE_ALLOCATE = (1 shl 14);`	Inner Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR7_WRITE_THROUGH = (2 shl 14);`	Inner Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR7_WRITE_BACK = (3 shl 14);`	Inner Cacheable property mapping for memory attributes 7, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR6_NONCACHED = (0 shl 12);`	Inner Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR6_WRITE_ALLOCATE = (1 shl 12);`	Inner Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR6_WRITE_THROUGH = (2 shl 12);`	Inner Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR6_WRITE_BACK = (3 shl 12);`	Inner Cacheable property mapping for memory attributes 6, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR5_NONCACHED = (0 shl 10);`	Inner Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR5_WRITE_ALLOCATE = (1 shl 10);`	Inner Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR5_WRITE_THROUGH = (2 shl 10);`	Inner Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR5_WRITE_BACK = (3 shl 10);`	Inner Cacheable property mapping for memory attributes 5, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits
`ARMV7_CP15_C10_NMRR_IR4_NONCACHED = (0 shl 8);`	Inner Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR4_WRITE_ALLOCATE = (1 shl 8);`	Inner Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR4_WRITE_THROUGH = (2 shl 8);`	Inner Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR4_WRITE_BACK = (3 shl 8);`	Inner Cacheable property mapping for memory attributes 4, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR3_NONCACHED = (0 shl 6);`	Inner Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR3_WRITE_ALLOCATE= (1 shl 6);`	Inner Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR3_WRITE_THROUGH = (2 shl 6);`	Inner Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR3_WRITE_BACK = (3 shl 6);`	Inner Cacheable property mapping for memory attributes 3, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR2_NONCACHED = (0 shl 4);`	Inner Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR2_WRITE_ALLOCATE = (1 shl 4);`	Inner Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR2_WRITE_THROUGH = (2 shl 4);`	Inner Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR2_WRITE_BACK = (3 shl 4);`	Inner Cacheable property mapping for memory attributes 2, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR1_NONCACHED = (0 shl 2);`	Inner Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR1_WRITE_ALLOCATE = (1 shl 2);`	Inner Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR1_WRITE_THROUGH = (2 shl 2);`	Inner Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR1_WRITE_BACK = (3 shl 2);`	Inner Cacheable property mapping for memory attributes 1, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR0_NONCACHED = (0 shl 0);`	Inner Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR0_WRITE_ALLOCATE = (1 shl 0);`	Inner Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR0_WRITE_THROUGH = (2 shl 0);`	Inner Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)
`ARMV7_CP15_C10_NMRR_IR0_WRITE_BACK = (3 shl 0);`	Inner Cacheable property mapping for memory attributes 0, if the region is mapped as Normal memory by the PRRR (The value of the TEX[0], C and B bits)

`ARMV7_CP15_C10_NMRR_MASK = ARMV7_CP15_C10_NMRR_IR1_NONCACHED or ARMV7_CP15_C10_NMRR_OR1_NONCACHED`	IR1 and OR1 are Non Cached

`or ARMV7_CP15_C10_NMRR_IR2_WRITE_THROUGH or ARMV7_CP15_C10_NMRR_OR2_WRITE_THROUGH`	IR2 and OR2 are Write Through

`or ARMV7_CP15_C10_NMRR_IR3_WRITE_BACK or ARMV7_CP15_C10_NMRR_OR3_WRITE_BACK`	IR3 and OR3 are Write Back

`or ARMV7_CP15_C10_NMRR_IR7_WRITE_ALLOCATE or ARMV7_CP15_C10_NMRR_OR7_WRITE_ALLOCATE;`	IR7 and OR7 are Write Allocate

[Expand]

ARMv7 CP15 C14 generic timer control ARMV7_CP15_C14_CNT_CTL_*

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ARMv7 CP15 C14 generic timer ARMV7_CP15_C14_*

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ARMv7 floating-point exception ARMV7_FPEXC_*

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ARMv7 level one descriptor type ARMV7_L1D_TYPE_*

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ARMv7 level one descriptor flag ARMV7_L1D_FLAG_*

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ARMv7 level one descriptor mask ARMV7_L1D_*_MASK

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ARMv7 level one descriptor TEX value ARMV7_L1D_TEX*

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ARMv7 level one descriptor AP value ARMV7_L1D_AP*

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ARMv7 level one descriptor permission value ARMV7_L1D_ACCESS_*

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ARMv7 level one descriptor cache value ARMV7_L1D_CACHE_*

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ARMv7 level one descriptor cacheable memory value ARMV7_L1D_CACHE_CACHEABLE_*

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ARMv7 level one descriptor cache TEX remap value ARMV7_L1D_CACHE_REMAP_*

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ARMv7 level two descriptor type ARMV7_L2D_TYPE_*

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ARMv7 level two descriptor flag ARMV7_L2D_FLAG_*

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ARMv7 level two descriptor mask ARMV7_L2D_*_MASK

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ARMv7 level two descriptor large TEX value ARMV7_L2D_LARGE_TEX*

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ARMv7 level two descriptor small TEX value ARMV7_L2D_SMALL_TEX*

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ARMv7 level two descriptor AP value ARMV7_L2D_AP*

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ARMv7 level two descriptor permission value ARMV7_L2D_ACCESS_*

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ARMv7 level two descriptor large cache value ARMV7_L2D_LARGE_CACHE_*

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ARMv7 level two descriptor large cacheable memory value ARMV7_L2D_LARGE_CACHE_CACHEABLE_*

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ARMv7 level two descriptor large cache TEX remap value ARMV7_L2D_LARGE_CACHE_REMAP_*

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ARMv7 level two descriptor small cache value ARMV7_L2D_SMALL_CACHE_*

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ARMv7 level two descriptor small cacheable memory value ARMV7_L2D_SMALL_CACHE_CACHEABLE_*

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ARMv7 level two descriptor small cache TEX remap value ARMV7_L2D_SMALL_CACHE_REMAP_*

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ARMv7 specific constants ARMV7_*

Type definitions

ARMv7 page table initialization

`TARMv7PageTableInit = procedure;`

ARMv7 dispatch IRQ

`TARMv7DispatchIRQ = function(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;`

ARMv7 dispatch FIQ

`TARMv7DispatchFIQ = function(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;`

ARMv7 dispatch SWI

`TARMv7DispatchSWI = function(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle;`

Public variables

ARMv7 specific variables

`ARMv7Initialized:Boolean;`

Page table handlers

`ARMv7PageTableInitHandler:TARMv7PageTableInit;`

IRQ handlers

`ARMv7DispatchIRQHandler:TARMv7DispatchIRQ;`

FIQ handlers

`ARMv7DispatchFIQHandler:TARMv7DispatchFIQ;`

SWI handlers

`ARMv7DispatchSWIHandler:TARMv7DispatchSWI;`

Function declarations

Initialization functions

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procedure ARMv7Init;

Description: To be documented

ARMv7 platform functions

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procedure ARMv7CPUInit; assembler; nostackframe;

Description: To be documented

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procedure ARMv7FPUInit; assembler; nostackframe;

Description: To be documented

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procedure ARMv7MMUInit;

Description: To be documented

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procedure ARMv7CacheInit; assembler; nostackframe;

Description: To be documented

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procedure ARMv7TimerInit(Frequency:LongWord); assembler; nostackframe;

Description: To be documented

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procedure ARMv7PageTableInit;

Description: Initialize the Hardware Page Tables before enabling the MMU

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procedure ARMv7SystemCall(Number:LongWord; Param1,Param2,Param3:PtrUInt);

Description: To be documented

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function ARMv7CPUGetMode:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CPUGetState:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CPUGetCurrent:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CPUGetMainID:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CPUGetMultiprocessorID:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CPUGetModel:LongWord;

Description: To be documented

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function ARMv7CPUGetRevision:LongWord;

Description: To be documented

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function ARMv7CPUGetDescription:String;

Description: To be documented

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function ARMv7FPUGetState:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L1CacheGetType:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L1DataCacheGetSize:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L1DataCacheGetLineSize:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L1InstructionCacheGetSize:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L1InstructionCacheGetLineSize:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L2CacheGetType:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L2CacheGetSize:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7L2CacheGetLineSize:LongWord; assembler; nostackframe;

Description: To be documented

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procedure ARMv7Halt; assembler; nostackframe; public name '_haltproc';

Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state

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procedure ARMv7Pause; assembler; nostackframe;

Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state

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procedure ARMv7SendEvent; assembler; nostackframe;

Description: To be documented

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procedure ARMv7WaitForEvent; assembler; nostackframe;

Description: To be documented

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procedure ARMv7WaitForInterrupt; assembler; nostackframe;

Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state

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procedure ARMv7DataMemoryBarrier; assembler; nostackframe;

Description: Perform a data memory barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15

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procedure ARMv7DataSynchronizationBarrier; assembler; nostackframe;

Description: Perform a data synchronization barrier operation

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procedure ARMv7InstructionMemoryBarrier; assembler; nostackframe;

Description: Perform a instruction synchronization barrier operation

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procedure ARMv7InvalidateTLB; assembler; nostackframe;

Description: Perform an invalidate entire TLB operation using the c8 (TLB Operations) register of system control coprocessor CP15

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procedure ARMv7InvalidateDataTLB; assembler; nostackframe;

Description: Perform an invalidate data TLB (Unlocked/Data) operation using the c8 (TLB Operations) register of system control coprocessor CP15

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procedure ARMv7InvalidateInstructionTLB; assembler; nostackframe;

Description: Perform an invalidate instruction TLB (Unlocked/Instruction) operation using the c8 (TLB Operations) register of system control coprocessor CP15

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procedure ARMv7InvalidateCache; assembler; nostackframe;

Description: Perform an invalidate both caches operation using the c7 (Cache Operations) register of system control coprocessor CP15

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procedure ARMv7CleanDataCache; assembler; nostackframe;

Description: Perform a clean entire data cache operation

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procedure ARMv7InvalidateDataCache; assembler; nostackframe;

Description: Perform an invalidate entire data cache operation

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procedure ARMv7InvalidateL1DataCache; assembler; nostackframe;

Description: Perform an invalidate entire L1 data cache operation

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procedure ARMv7CleanAndInvalidateDataCache; assembler; nostackframe;

Description: Perform a clean and invalidate entire data cache operation

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procedure ARMv7InvalidateInstructionCache; assembler; nostackframe;

Description: Perform an invalidate entire instruction cache operation using the c7 (Cache Operations) register of system control coprocessor CP15

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procedure ARMv7CleanDataCacheRange(Address:PtrUInt; Size:LongWord);

Description: Perform a clean data cache by MVA to PoC operation

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procedure ARMv7InvalidateDataCacheRange(Address:PtrUInt; Size:LongWord);

Description: Perform an invalidate data cache by MVA to PoC operation

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procedure ARMv7CleanAndInvalidateDataCacheRange(Address:PtrUInt; Size:LongWord);

Description: Perform a clean and invalidate data cache by MVA to PoC operation

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procedure ARMv7InvalidateInstructionCacheRange(Address:PtrUInt; Size:LongWord);

Description: Perform an invalidate instruction caches by MVA to PoU operation

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procedure ARMv7CleanDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;

Description: Perform a clean data cache line by set/way operation

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procedure ARMv7InvalidateDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;

Description: Perform an invalidate data cache line by set/way operation

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procedure ARMv7CleanAndInvalidateDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;

Description: Perform a clean and invalidate data cache line by set/way operation

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procedure ARMv7FlushPrefetchBuffer; assembler; nostackframe;

Description: Perform an Instruction Synchronization Barrier operation

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procedure ARMv7FlushBranchTargetCache; assembler; nostackframe;

Description: Perform a Flush Entire Branch Target Cache operation

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procedure ARMv7ContextSwitch(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;

Description: Perform a context switch from one thread to another as a result of a thread yielding, sleeping or waiting

OldStack	The address to save the stack pointer to for the current thread (Passed in r0)
NewStack	The address to restore the stack pointer from for the new thread (Passed in r1)
NewThread	The handle of the new thread to switch to (Passed in r2)
Note	At the point of the actual context switch (str sp/ldr sp) the thread stacks will look like this: (See: ARMv7ThreadSetupStack for additional information) (Base "Highest Address" of Stack) . . . . cpsr <- The current program status register value to load on return from the context switch lr/pc <- The address to return to from the context switch lr <- The lr value prior to the context switch r12 <- r11 <- r10 <- r9 <- r8 <- r7 <- r6 <- The value of these registers prior to the context switch r5 <- r4 <- r3 <- r2 <- r1 <- r0 <- d15 <- d14 <- d13 <- d12 <- d11 <- d10 <- d9 <- d8 <- The value of these floating point registers prior to the context switch d7 <- d6 <- d5 <- d4 <- d3 <- d2 <- d1 <- d0 <- fpscr <- The floating point FPSCR register fpexc <- The floating point FPEXC register (Current StackPointer points to here) . . . . (Top "Lowest Address" of Stack) This form of context switch uses r12 to save the cpsr value (and RFE to restore it). Because this context switch is called from a routine which will have saved the value of r12 (which is caller save in the ARM ABI) then we do not need to save the original value of r12. The context switch will be performed from SYS mode to SYS mode, the cpsr value will include the control bits (Mode and IRQ/FIQ state) but not the flags values. Again the ARM ABI does not require that the flags be saved by the callee and so the caller would have accounted for any needed flags before calling. If the thread to be resumed was interrupted by an IRQ or FIQ then the cpsr will also contain the flags etc as they were at the point of interrupt. We do not need to account for the state bits in the cpsr since all operations are performed in ARM mode at present. The main requirement of this routine is to ensure that the context record on the stack matches exactly that which is created on an interrupt and also that created by ThreadSetupStack for a new thread. If this is correct then the next context switch for any given thread can be either by a call to reschedule or by an interrupt. Equally a new thread can be first run from a context switch that resulted from either a call to reschedule or an interrupt. Note that this routine could use: pop (lr) pop (r12) msr cpsr_c, r12 mov pc, lr To return but that would mess up the value of r12, lr and the cpsr flags etc if the thread being resumed was interrupted by an IRQ, FIQ or SWI. The use of RFE here allows for exactly the same behaviour no matter which way the context record is saved and restored.

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procedure ARMv7ContextSwitchIRQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;

Description: Perform a context switch from one thread to another as a result of an interrupt request (IRQ)

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procedure ARMv7ContextSwitchFIQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;

Description: Perform a context switch from one thread to another as a result of a fast interrupt request (FIQ)

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procedure ARMv7ContextSwitchSWI(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;

Description: Perform a context switch from one thread to another as a result of a software interrupt (SWI)

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function ARMv7InterlockedOr(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic OR operation using LDREX/STREX

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function ARMv7InterlockedXor(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic XOR operation using LDREX/STREX

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function ARMv7InterlockedAnd(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic AND operation using LDREX/STREX

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function ARMv7InterlockedDecrement(var Target:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic decrement operation using LDREX/STREX

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function ARMv7InterlockedIncrement(var Target:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic increment operation using LDREX/STREX

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function ARMv7InterlockedExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic exchange operation using LDREX/STREX

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function ARMv7InterlockedAddExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic add and exchange operation using LDREX/STREX

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function ARMv7InterlockedCompareExchange(var Target:LongInt; Source,Compare:LongInt):LongInt; assembler; nostackframe;

Description: Perform an atomic compare and exchange operation using LDREX/STREX

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procedure ARMv7PageTableGetEntry(Address:PtrUInt; var Entry:TPageTableEntry);

Description: Get and Decode the entry in the Page Table that corresponds to the supplied virtual address

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function ARMv7PageTableSetEntry(const Entry:TPageTableEntry):LongWord;

Description: Encode and Set an entry in the Page Table that corresponds to the supplied virtual address

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function ARMv7VectorTableGetEntry(Number:LongWord):PtrUInt;

Description: Return the address of the specified vector table entry number

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function ARMv7VectorTableSetEntry(Number:LongWord; Address:PtrUInt):LongWord;

Description: Set the supplied address as the value of the specified vector table entry number

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function ARMv7FirstBitSet(Value:LongWord):LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7CountLeadingZeros(Value:LongWord):LongWord; assembler; nostackframe;

Description: Equivalent of the GCC Builtin function __builtin_clz

ARMv7 thread functions

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procedure ARMv7PrimaryInit; assembler; nostackframe;

Description: To be documented

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function ARMv7SpinLock(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Lock an existing Spin entry

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function ARMv7SpinUnlock(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Unlock an existing Spin entry

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function ARMv7SpinLockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Lock an existing Spin entry, disable IRQ and save the previous IRQ state

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function ARMv7SpinUnlockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Unlock an existing Spin entry and restore the previous IRQ state

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function ARMv7SpinLockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Lock an existing Spin entry, disable FIQ and save the previous FIQ state

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function ARMv7SpinUnlockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Unlock an existing Spin entry and restore the previous FIQ state

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function ARMv7SpinLockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Lock an existing Spin entry, disable IRQ and FIQ and save the previous IRQ/FIQ state

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function ARMv7SpinUnlockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;

Description: Unlock an existing Spin entry and restore the previous IRQ/FIQ state

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function ARMv7SpinCheckIRQ(Spin:PSpinEntry):Boolean;

Description: To be documented

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function ARMv7SpinCheckFIQ(Spin:PSpinEntry):Boolean;

Description: To be documented

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function ARMv7SpinExchangeIRQ(Spin1,Spin2:PSpinEntry):LongWord;

Description: To be documented

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function ARMv7SpinExchangeFIQ(Spin1,Spin2:PSpinEntry):LongWord;

Description: To be documented

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function ARMv7MutexLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;

Description: Lock an existing Mutex entry

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function ARMv7MutexUnlock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;

Description: Unlock an existing Mutex entry

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function ARMv7MutexTryLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;

Description: Try to lock an existing Mutex entry

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function ARMv7ThreadGetCurrent:TThreadHandle; assembler; nostackframe;

Description: Get the current thread Id from the c13 (Thread and process ID) register of system control coprocessor CP15

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function ARMv7ThreadSetCurrent(Thread:TThreadHandle):LongWord; assembler; nostackframe;

Description: Set the current thread Id in the c13 (Thread and process ID) register of system control coprocessor CP15

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function ARMv7ThreadSetupStack(StackBase:Pointer; StartProc:TThreadStart; ReturnProc:TThreadEnd; Parameter:Pointer):Pointer;

Description: Set up the context record and arguments on the stack for a new thread

StackBase	Pointer to the base (highest address) of the allocated stack (as returned by ThreadAllocateStack
StartProc	The procedure the thread will start executing when resumed
ReturnProc	The procedure the thread will return to on exit
Return	Pointer to the starting address of the stack, which will be the Stack Pointer on the first context switch
Note	At the point of a context switch the thread stack will look like this: (Base "Highest Address" of Stack) . . . . cpsr <- The current program status register value to load on return from the context switch (On Interrupt: Includes the flags and control bits for the interrupted thread) (On Yield: Includes the control bits only for the yielded thread) (On Create: Includes the control bits only for the new thread) lr/pc <- The address to return to from the context switch (On Interrupt: The location the thread was at before interrupt) (On Yield: The location to return to in SchedulerReschedule) (On Create: The location of StartProc for the new thread) lr <- The lr value prior to the context switch (On Interrupt: The value of lr before the thread was interrupted) (On Yield: The location to return to in SchedulerReschedule) (On Create: The location of ReturnProc for the new thread) r12 <- r11 <- r10 <- r9 <- r8 <- r7 <- r6 <- The value of these registers prior to the context switch r5 <- (On Interrupt: The values before the thread was interrupted) r4 <- (On Yield: The values on return to SchedulerReschedule) r3 <- (On Create: The values on entry to StartProc as set by ThreadSetupStack) r2 <- r1 <- r0 <- d15 <- d14 <- d13 <- d12 <- d11 <- d10 <- d9 <- d8 <- The value of these floating point registers prior to the context switch d7 <- (On Interrupt: The values before the thread was interrupted) d6 <- (On Yield: The values on return to SchedulerReschedule) d5 <- (On Create: The values on entry to StartProc as set by ThreadSetupStack) d4 <- d3 <- d2 <- d1 <- d0 <- fpscr <- The floating point FPSCR register fpexc <- The floating point FPEXC register (Current StackPointer points to here) . . . . (Top "Lowest Address" of Stack) On exit from a standard context switch as performed by SchedulerReschedule the first value (Highest Address) of lr is used by the RFE (Return From Exception) instruction to load the pc which also loads the saved cpsr value. On exit from an IRQ or FIQ context switch as performed by SchedulerSwitch the first value (Highest Address) of lr is used by the interrupt handler to return from the interrupt. A standard context switch uses r12 to save the cpsr value (and RFE to restore it). Because the standard context switch is called from a routine which will have saved the value of r12 (which is caller save in the ARM ABI) then we do not need to save the original value of r12. An IRQ or FIQ context switch uses the SRS (Store Return State) and RFE (Return From Exception) instructions to save and restore the cpsr value from the spsr value of either IRQ or FIQ mode.

ARMv7 IRQ functions

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function ARMv7DispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;

Description: To be documented

ARMv7 FIQ functions

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function ARMv7DispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;

Description: To be documented

ARMv7 SWI functions

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function ARMv7DispatchSWI(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle; inline;

Description: To be documented

ARMv7 interrupt functions

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procedure ARMv7ResetHandler; assembler; nostackframe;

Description: To be documented

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procedure ARMv7UndefinedInstructionHandler; assembler; nostackframe;

Description: Handle an undefined instruction exception

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procedure ARMv7SoftwareInterruptHandler; assembler; nostackframe;

Description: Handle a software interrupt (SWI) from a system call (SVC)

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procedure ARMv7PrefetchAbortHandler; assembler; nostackframe;

Description: Handle a prefetch abort exception

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procedure ARMv7DataAbortHandler; assembler; nostackframe;

Description: Handle a data abort exception

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procedure ARMv7ReservedHandler; assembler; nostackframe;

Description: To be documented

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procedure ARMv7IRQHandler; assembler; nostackframe;

Description: Handle an interrupt request IRQ from an interrupt source

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procedure ARMv7FIQHandler; assembler; nostackframe;

Description: Handle a fast interrupt request FIQ from an interrupt source

Note	This routine is registered as the vector for FIQ requests in the vector table loaded during startup. At the end of each instruction the processor checks the FIQ line and if triggered it will lookup the vector in the vector table and jump to the routine listed. When the processor receives an FIQ it switches to FIQ mode, stores the address of the next instruction in the FIQ mode link register (lr_fiq) and saves the current program status register into the FIQ mode saved program status register (spsr_fiq). The FIQ handler first checks the spsr to determine if the task being interrupted is a normal thread or an exception or interrupt handler. The FIQ handler then saves the FIQ mode lr and spsr (which represent the location and state to return to) onto eihter the SYS mode or SVC mode stack using the srsdb (Store Return State Decrement Before) instruction depending on the value of spsr. The FIQ handler switches to SYS or SVC mode and saves all the neccessary registers for the return to the interrupted task before switching back to FIQ mode in order to process the interrupt request. Because we arrive here from an interrupt the task that was executing has no opportunity to save registers and will be unaware on return that it was interrupted. For this reason we must save all of the general purpose registers (r0 to r12) as well as the SYS mode link register (lr). We do not save the stack pointer (r13) because we use it to store the other registers and will return it to the correct value before we return from the FIQ handler. The program counter (r15) does not need to be saved as it now points to this code. To process the fast interrupt request the handler calls the DispatchFIQ function which will dispatch the interrupt to a registered handler for processing. The handler must clear the interrupt source before it returns or the fast interrupt will simply occur again immediately once reenabled. To return from the fast interrupt request the handler uses the rfeia (Return From Exception Increment After) instruction which will load the pc and cpsr from the stack of the current mode (SYS or SVC).

ARMv7 helper functions

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function ARMv7GetFPEXC:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7GetFPSCR:LongWord; assembler; nostackframe;

Description: To be documented

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procedure ARMv7StartMMU; assembler; nostackframe;

Description: To be documented

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function ARMv7GetTimerState(Timer:LongWord):LongWord; assembler; nostackframe;

Description: To be documented

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procedure ARMv7SetTimerState(Timer,State:LongWord); assembler; nostackframe;

Description: To be documented

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function ARMv7GetTimerCount(Timer:LongWord):Int64; assembler; nostackframe;

Description: To be documented

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function ARMv7GetTimerValue(Timer:LongWord):LongWord; assembler; nostackframe;

Description: To be documented

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procedure ARMV7SetTimerValue(Timer,Value:LongWord); assembler; nostackframe;

Description: To be documented

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function ARMv7GetTimerCompare(Timer:LongWord):Int64; assembler; nostackframe;

Description: To be documented

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procedure ARMV7SetTimerCompare(Timer,High,Low:LongWord); assembler; nostackframe;

Description: To be documented

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function ARMv7GetTimerFrequency:LongWord; assembler; nostackframe;

Description: To be documented

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function ARMv7GetPageTableCoarse(Address:PtrUInt):LongWord;

Description: Get the descriptor for a Coarse Page Table entry (1MB)

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function ARMv7SetPageTableCoarse(Address,CoarseAddress:PtrUInt; Flags:Word):Boolean;

Description: Set the descriptor for a Coarse Page Table entry (1MB)

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function ARMv7GetPageTableLarge(Address:PtrUInt):LongWord;

Description: Get the descriptor for a Large Page Table entry (64KB)

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function ARMv7SetPageTableLarge(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;

Description: Set the descriptor for a Large Page Table entry (64KB)

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function ARMv7GetPageTableSmall(Address:PtrUInt):LongWord;

Description: Get the descriptor for a Small Page Table entry (4KB)

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function ARMv7SetPageTableSmall(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;

Description: Set the descriptor for a Small Page Table entry (4KB)

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function ARMv7GetPageTableSection(Address:PtrUInt):LongWord;

Description: Get the descriptor for a Page Table Section (1MB) or Supersection (16MB)

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function ARMv7SetPageTableSection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;

Description: Set the descriptor for a Page Table Section (1MB)

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function ARMv7SetPageTableSupersection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;

Description: Set the descriptor for a Page Table Supersection (16MB)

Return to Unit Reference

`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_MASK = ($FF shl 24);`
`ARMV7_CP15_C0_MAINID_VARIANT_MASK = ($F shl 20);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_MASK = ($F shl 16);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_MASK = ($FFF shl 4);`
`ARMV7_CP15_C0_MAINID_REVISION_MASK = ($F shl 0);`

`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_ARM = ($41 shl 24);`
`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_DEC = ($44 shl 24);`
`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_FREESCALE = ($4D shl 24);`
`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_QUALCOMM = ($51 shl 24);`
`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_MARVELL = ($56 shl 24);`
`ARMV7_CP15_C0_MAINID_IMPLEMENTOR_INTEL = ($69 shl 24);`

`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV4 = ($1 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV4T = ($2 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV5 = ($3 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV5T = ($4 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV5TE = ($5 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV5TEJ = ($6 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_ARMV6 = ($7 shl 16);`
`ARMV7_CP15_C0_MAINID_ARCHITECTURE_CPUID = ($F shl 16);`

`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A5 = ($C05 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A7 = ($C07 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A8 = ($C08 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A9 = ($C09 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A15 = ($C0F shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A17 = ($C0E shl 4);`
The following are ARMv8 part numbers, included here to allow ARMv7 code on ARMv8 in 32bit mode
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A53 = ($D03 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A57 = ($D07 shl 4);`
`ARMV7_CP15_C0_MAINID_PARTNUMBER_CORTEX_A72 = ($D08 shl 4);`

`ARMV7_CP15_C0_MPID_MPE = (1 shl 31);`
`ARMV7_CP15_C0_MPID_U_UNIPROCESSOR = (1 shl 30);`
`ARMV7_CP15_C0_MPID_U_MULTIPROCESSOR = (0 shl 30);`
`ARMV7_CP15_C0_MPID_CLUSTERID_MASK = ($F shl 8);`
`ARMV7_CP15_C0_MPID_CPUID_MASK = (3 shl 0);`

`ARMV7_CP15_C0_CCSID_WT = (1 shl 31);`	Indicates whether the cache level supports Write-Through
`ARMV7_CP15_C0_CCSID_WB = (1 shl 30);`	Indicates whether the cache level supports Write-Back
`ARMV7_CP15_C0_CCSID_RA = (1 shl 29);`	Indicates whether the cache level supports Read-Allocation
`ARMV7_CP15_C0_CCSID_WA = (1 shl 28);`	Indicates whether the cache level supports Write-Allocation
`ARMV7_CP15_C0_CCSID_NUMSETS_MASK = ($7FFF shl 13);`	(Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.
`ARMV7_CP15_C0_CCSID_NUMWAYS_MASK = ($3FF shl 3);`	(Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2.
`ARMV7_CP15_C0_CCSID_LINESIZE_MASK = (7 shl 0);`	(Log2(Number of words in cache line)) -2. (eg For a line length of 8 words: Log2(8) = 3, LineSize entry = 1)

`ARMV7_CP15_C0_CCSID_NUMSETS_SHIFT = 13;`
`ARMV7_CP15_C0_CCSID_NUMWAYS_SHIFT = 3;`

`ARMV7_CP15_C0_CSSEL_LEVEL1 = (0 shl 1);`	Cache level of required cache. Permitted values are from 0b000, indicating Level 1 cache, to 0b110 indicating Level 7 cache.
`ARMV7_CP15_C0_CSSEL_LEVEL2 = (1 shl 1);`
`ARMV7_CP15_C0_CSSEL_LEVEL3 = (2 shl 1);`
`ARMV7_CP15_C0_CSSEL_LEVEL4 = (3 shl 1);`
`ARMV7_CP15_C0_CSSEL_LEVEL5 = (4 shl 1);`
`ARMV7_CP15_C0_CSSEL_LEVEL6 = (5 shl 1);`
`ARMV7_CP15_C0_CSSEL_LEVEL7 = (6 shl 1);`
`ARMV7_CP15_C0_CSSEL_DATA = (0 shl 0);`	Instruction not Data bit (0 = Data or unified cache)
`ARMV7_CP15_C0_CSSEL_INSTRUCTION = (1 shl 0);`	Instruction not Data bit (1 = Instruction cache)

`ARMV7_CP15_C1_AUX_DDI = (1 shl 28);`	Disable dual issue when set to 1 (Default 0)
`ARMV7_CP15_C1_AUX_DDVM = (1 shl 15);`	Disable Distributed Virtual Memory (DVM) transactions when set to 1 (Default 0)
`ARMV7_CP15_C1_AUX_L1PCTL_0 = (0 shl 13);`	L1 Data prefetch control, Prefetch disabled
`ARMV7_CP15_C1_AUX_L1PCTL_1 = (1 shl 13);`	L1 Data prefetch control, 1 outstanding pre-fetch permitted
`ARMV7_CP15_C1_AUX_L1PCTL_2 = (2 shl 13);`	L1 Data prefetch control, 2 outstanding pre-fetches permitted
`ARMV7_CP15_C1_AUX_L1PCTL_3 = (3 shl 13);`	L1 Data prefetch control, 3 outstanding pre-fetches permitted, this is the reset value (Default)
`ARMV7_CP15_C1_AUX_L1RADIS = (1 shl 12);`	L1 Data Cache read-allocate mode disable when set to 1 (Default 0)
`ARMV7_CP15_C1_AUX_L2RADIS = (1 shl 11);`	L2 Data Cache read-allocate mode disable when set to 1 (Default 0)
`ARMV7_CP15_C1_AUX_DODMBS = (1 shl 10);`	Disable optimized data memory barrier behavior when set to 1 (Default 0)
`ARMV7_CP15_C1_AUX_SMP = (1 shl 6);`	Enables coherent requests to the processor when set to 1 (Default 0). You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed.

`ARMV7_CP15_C1_AUX_FW = (1 shl 0);`	Cache and TLB maintenance broadcast enabled when set to 1 (Default 0) (Cortex-A9 Only)

Unit PlatformARMv7

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`ARMV7_CP15_C1_SCR_SIF = (1 shl 9);`	Secure Instruction Fetch bit
`ARMV7_CP15_C1_SCR_HCE = (1 shl 8);`	Hyp Call enable. This bit enables the use of HVC instruction from Non-secure PL1 modes.
`ARMV7_CP15_C1_SCR_SCD = (1 shl 7);`	Secure Monitor Call disable. This bit causes the SMC instruction to be UNDEFINED in Non-secure state.
`ARMV7_CP15_C1_SCR_NET = (1 shl 6);`	Not Early Termination. This bit disables early termination of data operations.
`ARMV7_CP15_C1_SCR_AW = (1 shl 5);`	A bit writable. This bit controls whether the A bit in the CPSR can be modified in Non-secure state.
`ARMV7_CP15_C1_SCR_FW = (1 shl 4);`	F bit writable. This bit controls whether the F bit in the CPSR can be modified in Non-secure state.
`ARMV7_CP15_C1_SCR_EA = (1 shl 3);`	External Abort handler. This bit controls which mode takes external aborts.
`ARMV7_CP15_C1_SCR_FIQ = (1 shl 2);`	FIQ handler. This bit controls which mode takes FIQ exceptions.
`ARMV7_CP15_C1_SCR_IRQ = (1 shl 1);`	IRQ handler. This bit controls which mode takes IRQ exceptions.
`ARMV7_CP15_C1_SCR_NS = (1 shl 0);`	Non Secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the processor.

`ARMV7_CP15_C2_TTBR_BASE_MASK = $FFFFC000;`
`ARMV7_CP15_C2_TTBR_NOS = (1 shl 5);`	Not Outer Shareable bit (0 Outer Shareable/1 Inner Shareable)
`ARMV7_CP15_C2_TTBR_RGN_OUTER_NONCACHED = (0 shl 3);`	Normal Outer Noncacheable (Default)
`ARMV7_CP15_C2_TTBR_RGN_OUTER_WRITE_ALLOCATE= (1 shl 3);`	Normal Outer Write-back, Write Allocate
`ARMV7_CP15_C2_TTBR_RGN_OUTER_WRITE_THROUGH = (2 shl 3);`	Normal Outer Write-through, No Allocate on Write
`ARMV7_CP15_C2_TTBR_RGN_OUTER_WRITE_BACK = (3 shl 3);`	Normal Outer Write-back, No Allocate on Write
`ARMV7_CP15_C2_TTBR_IMP = (1 shl 2);`	The effect of this bit is IMPLEMENTATION DEFINED
`ARMV7_CP15_C2_TTBR_S = (1 shl 1);`	Shareable bit (0 Non Shareable/1 Shareable)
`ARMV7_CP15_C2_TTBR_C_INNER_CACHED = (1 shl 0);`	Cacheable bit (0 Inner Non Cacheable/1 Inner Cacheable) (ARMv7-A base only)
`ARMV7_CP15_C2_TTBR_IRGN_INNER_NONCACHED = (0 shl 6) or (0 shl 0);`	Normal Inner Noncacheable (Default)
`ARMV7_CP15_C2_TTBR_IRGN_INNER_WRITE_ALLOCATE = (1 shl 6) or (0 shl 0);`	Normal Inner Write-Back Write-Allocate Cacheable
`ARMV7_CP15_C2_TTBR_IRGN_INNER_WRITE_THROUGH = (0 shl 6) or (1 shl 0);`	Normal Inner Write-Through Cacheable
`ARMV7_CP15_C2_TTBR_IRGN_INNER_WRITE_BACK = (1 shl 6) or (1 shl 0);`	Normal Inner Write-Back no Write-Allocate Cacheable

`ARMV7_CP15_C14_CNT_CTL_ISTATUS = (1 shl 2);`	The status of the timer (Read Only)(When set the timer condition is asserted)
`ARMV7_CP15_C14_CNT_CTL_IMASK = (1 shl 1);`	Timer output signal mask bit (When set the timer output signal is masked)
`ARMV7_CP15_C14_CNT_CTL_ENABLE = (1 shl 0);`	Enables the timer (When set the timer output signal is enabled)

`ARMV7_CP15_C14_CNTP = 0;`	Physical Timer (Secure or Non Secure depending on the NS bit of the SCR)
`ARMV7_CP15_C14_CNTV = 1;`	Virtual Timer
`ARMV7_CP15_C14_CNTH = 2;`	Hypervisor Timer (Only available from HYP mode)

`ARMV7_FPEXC_EN = (1 shl 30);`	Floating-point system is enabled and operates normally if set to 1 (Default 0)
`ARMV7_FPEXC_EX = (1 shl 31);`	If EX is set to 0 then only FPSCR and FPEXC need to be preseved on a context switch (Default 0)

See page B3-7 of the ARMv7 Architecture Reference Manual
See page B3-8 of the ARMv7 Architecture Reference Manual
Level One Page Table contains 4096 32bit (4 byte) entries for a total size of 16KB

`ARMV7_L1D_TYPE_COARSE = 1;`	The entry points to a 1MB second-level page table. See page 6-40.
`ARMV7_L1D_TYPE_SECTION = 2;`	The entry points to a either a 1MB Section of memory or a 16MB Supersection of memory
`ARMV7_L1D_TYPE_SUPERSECTION = 2;`	Bit[18] of the descriptor selects between a Section and a Supersection

See page B3-9 of the ARMv7 Architecture Reference Manual

`ARMV7_L1D_FLAG_COARSE_NS = (1 shl 3);`	NS (Non Secure) Attribute bit to enable the support of TrustZone
`ARMV7_L1D_FLAG_SECTION_NS = (1 shl 19);`	NS (Non Secure) Attribute bit to enable the support of TrustZone
`ARMV7_L1D_FLAG_SUPERSECTION = (1 shl 18);`	The descriptor is a 16MB Supersection instead of a 1MB Section (Section Only)
`ARMV7_L1D_FLAG_NOT_GLOBAL = (1 shl 17);`	The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1) (Section Only)
`ARMV7_L1D_FLAG_SHARED = (1 shl 16);`	The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions. Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits (Section Only).
`ARMV7_L1D_FLAG_AP2 = (1 shl 15);`	The access permissions extension (AP2) bit, provides an extra access permission bit (Section Only)
`ARMV7_L1D_FLAG_IMP = (1 shl 9);`	The meaning of this bit is IMPLEMENTATION DEFINED
`ARMV7_L1D_FLAG_XN = (1 shl 4);`	The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1) (Section Only)
`ARMV7_L1D_FLAG_C = (1 shl 3);`	Cacheable (C) bit (Section Only)
`ARMV7_L1D_FLAG_B = (1 shl 2);`	Bufferable (B) bit (Section Only)

See page B3-8 of the ARMv7 Architecture Reference Manual

`ARMV7_L1D_COARSE_BASE_MASK = $FFFFFC00;`
`ARMV7_L1D_SECTION_BASE_MASK = $FFF00000;`
`ARMV7_L1D_SUPERSECTION_BASE_MASK = $FF000000;`
`ARMV7_L1D_DOMAIN_MASK = ($F shl 5);`	Security Domain of the Descriptor
`ARMV7_L1D_TEX_MASK = (7 shl 12);`	Type extension field bits (Section Only)
`ARMV7_L1D_AP_MASK = (3 shl 10);`	Access permission bits (Section Only)

See page B3-32 of the ARMv7 Architecture Reference Manual (Section Only)

`ARMV7_L1D_TEX0 = (0 shl 12);`
`ARMV7_L1D_TEX1 = (1 shl 12);`
`ARMV7_L1D_TEX2 = (2 shl 12);`
`ARMV7_L1D_TEX4 = (4 shl 12);`	Only used for Cacheable memory values
`ARMV7_L1D_TEX5 = (5 shl 12);`	Only used for Cacheable memory values
`ARMV7_L1D_TEX6 = (6 shl 12);`	Only used for Cacheable memory values
`ARMV7_L1D_TEX7 = (7 shl 12);`	Only used for Cacheable memory values

See page B3-28 of the ARMv7 Architecture Reference Manual (Section Only)

`ARMV7_L1D_AP0 = (0 shl 10);`
`ARMV7_L1D_AP1 = (1 shl 10);`
`ARMV7_L1D_AP2 = (2 shl 10);`
`ARMV7_L1D_AP3 = (3 shl 10);`

See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L1D_CACHE_STRONGLY_ORDERED = ARMV7_L1D_TEX0;`	Strongly Ordered. (Always Shared)
`ARMV7_L1D_CACHE_SHARED_DEVICE = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_B;`	Device. (Always Shared)
`ARMV7_L1D_CACHE_NORMAL_WRITE_THROUGH = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_C;`	Normal. Write Through (Shared if S bit set)
`ARMV7_L1D_CACHE_NORMAL_WRITE_BACK = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_C or ARMV7_L1D_FLAG_B;`	Normal. Write Back (Shared if S bit set)
`ARMV7_L1D_CACHE_NORMAL_NONCACHED = ARMV7_L1D_TEX1;`	Normal. Noncacheable (Shared if S bit set)
`ARMV7_L1D_CACHE_NORMAL_WRITE_ALLOCATE = ARMV7_L1D_TEX1 or ARMV7_L1D_FLAG_C or ARMV7_L1D_FLAG_B;`	Normal. Write Allocate (Shared if S bit set)
`ARMV7_L1D_CACHE_NONSHARED_DEVICE = ARMV7_L1D_TEX2;`	Device. (Not Shared)

TEX Remap Enabled
See page B3-34 of the ARMv7 Architecture Reference Manual (These values are from Linux)

`ARMV7_L1D_CACHE_REMAP_STRONGLY_ORDERED = ARMV7_L1D_TEX0;`	TR0 - Strongly Ordered
`ARMV7_L1D_CACHE_REMAP_NORMAL_NONCACHED = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_B;`	TR1 - Normal Noncacheable (Inner Shared if S bit set)
`ARMV7_L1D_CACHE_REMAP_NORMAL_WRITE_THROUGH = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_C;`	TR2 - Normal Write Through (Inner Shared if S bit set)
`ARMV7_L1D_CACHE_REMAP_NORMAL_WRITE_BACK = ARMV7_L1D_TEX0 or ARMV7_L1D_FLAG_C or ARMV7_L1D_FLAG_B;`	TR3 - Normal Write Back (Inner Shared if S bit set)
`ARMV7_L1D_CACHE_REMAP_DEVICE = ARMV7_L1D_TEX1;`	TR4 - Device
`ARMV7_L1D_CACHE_REMAP_UNUSED = ARMV7_L1D_TEX1 or ARMV7_L1D_FLAG_B;`	TR5 - Not currently used
`ARMV7_L1D_CACHE_REMAP_RESERVED = ARMV7_L1D_TEX1 or ARMV7_L1D_FLAG_C;`	TR6 - Implementation Defined
`ARMV7_L1D_CACHE_REMAP_NORMAL_WRITE_ALLOCATE = ARMV7_L1D_TEX1 or ARMV7_L1D_FLAG_C or ARMV7_L1D_FLAG_B;`	TR7 - Normal Write Allocate (Inner Shared if S bit set)

See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_LARGE_CACHE_STRONGLY_ORDERED = ARMV7_L2D_LARGE_TEX0;`	Strongly Ordered. (Always Shared)
`ARMV7_L2D_LARGE_CACHE_SHARED_DEVICE = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_B;`	Device. (Always Shared)
`ARMV7_L2D_LARGE_CACHE_NORMAL_WRITE_THROUGH = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_C;`	Normal. Write Through (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_NORMAL_WRITE_BACK = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Normal. Write Back (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_NORMAL_NONCACHED = ARMV7_L2D_LARGE_TEX1;`	Normal. Noncacheable (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_NORMAL_WRITE_ALLOCATE = ARMV7_L2D_LARGE_TEX1 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Normal. Write Allocate (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_NONSHARED_DEVICE = ARMV7_L2D_LARGE_TEX2;`	Device. (Not Shared)

TEX Remap Enabled
See page B3-32 of the ARMv7 Architecture Reference Manual (These values are from Linux)

`ARMV7_L2D_LARGE_CACHE_REMAP_STRONGLY_ORDERED = ARMV7_L2D_LARGE_TEX0;`	TR0 - Strongly Ordered
`ARMV7_L2D_LARGE_CACHE_REMAP_NORMAL_NONCACHED = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_B;`	TR1 - Normal Noncacheable (Inner Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_REMAP_NORMAL_WRITE_THROUGH = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_C;`	TR2 - Normal Write Through (Inner Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_REMAP_NORMAL_WRITE_BACK = ARMV7_L2D_LARGE_TEX0 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	TR3 - Normal Write Back (Inner Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_REMAP_DEVICE = ARMV7_L2D_LARGE_TEX1;`	TR4 - Device
`ARMV7_L2D_LARGE_CACHE_REMAP_UNUSED = ARMV7_L2D_LARGE_TEX1 or ARMV7_L2D_FLAG_B;`	TR5 - Not currently used
`ARMV7_L2D_LARGE_CACHE_REMAP_RESERVED = ARMV7_L2D_LARGE_TEX1 or ARMV7_L2D_FLAG_C;`	TR6 - Implementation Defined
`ARMV7_L2D_LARGE_CACHE_REMAP_NORMAL_WRITE_ALLOCATE = ARMV7_L2D_LARGE_TEX1 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	TR7 - Normal Write Allocate (Inner Shared if S bit set)

See page B3-28 of the ARMv7 Architecture Reference Manual
This is not the full set of permissions as Ultibo always runs in priviledged mode
The XN bit can also be applied to control whether memory regions are executable or not

`ARMV7_L1D_ACCESS_NONE = ARMV7_L1D_AP0;`	No Access for both Privileged and Unprivileged code
`ARMV7_L1D_ACCESS_READONLY = ARMV7_L1D_FLAG_AP2 or ARMV7_L1D_AP3;`	Read-Only for both Privileged and Unprivileged code
`ARMV7_L1D_ACCESS_READWRITE = ARMV7_L1D_AP3;`	Read-Write for both Privileged and Unprivileged code

Cacheable Memory
See page B3-34 of the ARMv7 Architecture Reference Manual

`ARMV7_L1D_CACHE_CACHEABLE_OUTER_NONCACHED = ARMV7_L1D_TEX4;`	Outer Normal Noncacheable (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_OUTER_WRITE_ALLOCATE = ARMV7_L1D_TEX5;`	Outer Normal Write Allocate (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_OUTER_WRITE_THROUGH = ARMV7_L1D_TEX6;`	Outer Normal Write Through (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_OUTER_WRITE_BACK = ARMV7_L1D_TEX7;`	Outer Normal Write Back (Shared if S bit set)

`ARMV7_L1D_CACHE_CACHEABLE_INNER_NONCACHED = ARMV7_L1D_TEX4;`	Inner Normal Noncacheable (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_INNER_WRITE_ALLOCATE = ARMV7_L1D_TEX4 or ARMV7_L1D_FLAG_B;`	Inner Normal Write Allocate (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_INNER_WRITE_THROUGH = ARMV7_L1D_TEX4 or ARMV7_L1D_FLAG_C;`	Inner Normal Write Through (Shared if S bit set)
`ARMV7_L1D_CACHE_CACHEABLE_INNER_WRITE_BACK = ARMV7_L1D_TEX4 or ARMV7_L1D_FLAG_C or ARMV7_L1D_FLAG_B;`	Inner Normal Write Back (Shared if S bit set)

See page B3-10 of the ARMv7 Architecture Reference Manual
Level Two Page Table contains 256 32bit (4 byte) entries for a total size of 1KB

`ARMV7_L2D_TYPE_LARGE = 1;`	The entry points to a 64KB Large page in memory
`ARMV7_L2D_TYPE_SMALL = 2;`	The entry points to a 4KB Extended small page in memory. Bit[0] of the entry is the XN (Execute Never) bit for the entry.

See page B3-10 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_FLAG_LARGE_XN = (1 shl 15);`	The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1)
`ARMV7_L2D_FLAG_SMALL_XN = (1 shl 0);`	The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1)
`ARMV7_L2D_FLAG_NOT_GLOBAL = (1 shl 11);`	The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1)
`ARMV7_L2D_FLAG_SHARED = (1 shl 10);`	The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions. Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits.
`ARMV7_L2D_FLAG_AP2 = (1 shl 9);`	The access permissions extension (APX) bit, provides an extra access permission bit.
`ARMV7_L2D_FLAG_C = (1 shl 3);`	Cacheable (C) bit
`ARMV7_L2D_FLAG_B = (1 shl 2);`	Bufferable (B) bit

See page B3-10 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_LARGE_BASE_MASK = $FFFF0000;`
`ARMV7_L2D_SMALL_BASE_MASK = $FFFFF000;`
`ARMV7_L2D_LARGE_TEX_MASK = (7 shl 12);`	Type extension field bits
`ARMV7_L2D_SMALL_TEX_MASK = (7 shl 6);`	Type extension field bits
`ARMV7_L2D_AP_MASK = (3 shl 4);`	Access permission bits

See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_LARGE_TEX0 = (0 shl 12);`
`ARMV7_L2D_LARGE_TEX1 = (1 shl 12);`
`ARMV7_L2D_LARGE_TEX2 = (2 shl 12);`
`ARMV7_L2D_LARGE_TEX4 = (4 shl 12);`
`ARMV7_L2D_LARGE_TEX5 = (5 shl 12);`	Only used for Cacheable memory values
`ARMV7_L2D_LARGE_TEX6 = (6 shl 12);`	Only used for Cacheable memory values
`ARMV7_L2D_LARGE_TEX7 = (7 shl 12);`	Only used for Cacheable memory values

See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_SMALL_TEX0 = (0 shl 6);`
`ARMV7_L2D_SMALL_TEX1 = (1 shl 6);`
`ARMV7_L2D_SMALL_TEX2 = (2 shl 6);`
`ARMV7_L2D_SMALL_TEX4 = (4 shl 6);`
`ARMV7_L2D_SMALL_TEX5 = (5 shl 6);`	Only used for Cacheable memory values
`ARMV7_L2D_SMALL_TEX6 = (6 shl 6);`	Only used for Cacheable memory values
`ARMV7_L2D_SMALL_TEX7 = (7 shl 6);`	Only used for Cacheable memory values

See page B3-28 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_AP0 = (0 shl 4);`
`ARMV7_L2D_AP1 = (1 shl 4);`
`ARMV7_L2D_AP2 = (2 shl 4);`
`ARMV7_L2D_AP3 = (3 shl 4);`

Cacheable Memory
See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_LARGE_CACHE_CACHEABLE_OUTER_NONCACHED = ARMV7_L2D_LARGE_TEX4;`	Outer Normal Noncacheable (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_OUTER_WRITE_ALLOCATE = ARMV7_L2D_LARGE_TEX5;`	Outer Normal Write Allocate (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_OUTER_WRITE_THROUGH = ARMV7_L2D_LARGE_TEX6;`	Outer Normal Write Through (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_OUTER_WRITE_BACK = ARMV7_L2D_LARGE_TEX7;`	Outer Normal Write Back (Shared if S bit set)

`ARMV7_L2D_LARGE_CACHE_CACHEABLE_INNER_NONCACHED = ARMV7_L2D_LARGE_TEX4;`	Inner Normal Noncacheable (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_INNER_WRITE_ALLOCATE = ARMV7_L2D_LARGE_TEX4 or ARMV7_L2D_FLAG_B;`	Inner Normal Write Allocate (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_INNER_WRITE_THROUGH = ARMV7_L2D_LARGE_TEX4 or ARMV7_L2D_FLAG_C;`	Inner Normal Write Through (Shared if S bit set)
`ARMV7_L2D_LARGE_CACHE_CACHEABLE_INNER_WRITE_BACK = ARMV7_L2D_LARGE_TEX4 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Inner Normal Write Back (Shared if S bit set)

See page B3-32 of the ARMv7 Architecture Reference Manual
See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_SMALL_CACHE_STRONGLY_ORDERED = ARMV7_L2D_SMALL_TEX0;`	Strongly Ordered. (Always Shared)
`ARMV7_L2D_SMALL_CACHE_SHARED_DEVICE = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_B;`	Device. (Always Shared)
`ARMV7_L2D_SMALL_CACHE_SHARED_DEVICE = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_B;`	Device. (Always Shared)
`ARMV7_L2D_SMALL_CACHE_NORMAL_WRITE_THROUGH = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_C;`	Normal. Write Through (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_NORMAL_WRITE_BACK = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Normal. Write Back (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_NORMAL_WRITE_BACK = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Normal. Write Back (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_NORMAL_NONCACHED = ARMV7_L2D_SMALL_TEX1;`	Normal. Noncacheable (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_NORMAL_WRITE_ALLOCATE = ARMV7_L2D_SMALL_TEX1 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Normal. Write Allocate (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_NONSHARED_DEVICE = ARMV7_L2D_SMALL_TEX2;`	Device. (Not Shared)

Cacheable Memory
See page B3-32 of the ARMv7 Architecture Reference Manual

`ARMV7_L2D_SMALL_CACHE_CACHEABLE_OUTER_NONCACHED = ARMV7_L2D_SMALL_TEX4;`	Outer Normal Noncacheable (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_OUTER_WRITE_ALLOCATE = ARMV7_L2D_SMALL_TEX5;`	Outer Normal Write Allocate (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_OUTER_WRITE_THROUGH = ARMV7_L2D_SMALL_TEX6;`	Outer Normal Write Through (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_OUTER_WRITE_BACK = ARMV7_L2D_SMALL_TEX7;`	Outer Normal Write Back (Shared if S bit set)

`ARMV7_L2D_SMALL_CACHE_CACHEABLE_INNER_NONCACHED = ARMV7_L2D_SMALL_TEX4;`	Inner Normal Noncacheable (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_INNER_WRITE_ALLOCATE = ARMV7_L2D_SMALL_TEX4 or ARMV7_L2D_FLAG_B;`	Inner Normal Write Allocate (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_INNER_WRITE_THROUGH = ARMV7_L2D_SMALL_TEX4 or ARMV7_L2D_FLAG_C;`	Inner Normal Write Through (Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_CACHEABLE_INNER_WRITE_BACK = ARMV7_L2D_SMALL_TEX4 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	Inner Normal Write Back (Shared if S bit set)

TEX Remap Enabled
See page B3-32 of the ARMv7 Architecture Reference Manual (These values are from Linux)

`ARMV7_L2D_SMALL_CACHE_REMAP_STRONGLY_ORDERED = ARMV7_L2D_SMALL_TEX0;`	TR0 - Strongly Ordered
`ARMV7_L2D_SMALL_CACHE_REMAP_NORMAL_NONCACHED = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_B;`	TR1 - Normal Noncacheable (Inner Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_REMAP_NORMAL_WRITE_THROUGH = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_C;`	TR2 - Normal Write Through (Inner Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_REMAP_NORMAL_WRITE_BACK = ARMV7_L2D_SMALL_TEX0 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	TR3 - Normal Write Back (Inner Shared if S bit set)
`ARMV7_L2D_SMALL_CACHE_REMAP_DEVICE = ARMV7_L2D_SMALL_TEX1;`	TR4 - Device
`ARMV7_L2D_SMALL_CACHE_REMAP_UNUSED = ARMV7_L2D_SMALL_TEX1 or ARMV7_L2D_FLAG_B;`	TR5 - Not currently used
`ARMV7_L2D_SMALL_CACHE_REMAP_RESERVED = ARMV7_L2D_SMALL_TEX1 or ARMV7_L2D_FLAG_C;`	TR6 - Implementation Defined
`ARMV7_L2D_SMALL_CACHE_REMAP_NORMAL_WRITE_ALLOCATE = ARMV7_L2D_SMALL_TEX1 or ARMV7_L2D_FLAG_C or ARMV7_L2D_FLAG_B;`	TR7 - Normal Write Allocate (Inner Shared if S bit set)

SetWay	Set/Way/Level will be passed in r0
Note	See page B3-127 of the ARMv7 Architecture Reference Manual

Spin	Pointer to the Spin entry to lock (Passed in R0)
Return	ERROR_SUCCESS if completed or another error code on failure (Returned in R0)

Mutex	Pointer to the Mutex entry to lock (Passed in R0)
Return	ERROR_SUCCESS if completed or another error code on failure (Returned in R0)

Mutex	Pointer to the Mutex entry to try to lock (Passed in R0)
Return	ERROR_SUCCESS if completed, ERROR_LOCKED if already locked or another error code on failure (Returned in R0).