Unit PlatformARMv6

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Description


Ultibo Platform Interface unit for ARMv6

The ARMv6 (ARM11) does not support WFI, WFE, DMB, DSB or ISB instructions, these must be done using MCR operations on the system control processor registers.

The ARMv6 supports the LDREX/STREX instructions for syncronisation (Lock/Mutex/Semaphore etc) but only if the MMU is enabled.

Constants



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ARMv6 page tables shift ARMV6_PAGE_TABLES_*


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ARMv6 CP15 C0 main Id ARMV6_CP15_C0_MAINID_*


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ARMv6 CP15 C0 cache type ARMV6_CP15_C0_CTR_*


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ARMv6 CP15 C1 control ARMV6_CP15_C1_*


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ARMv6 CP15 C1 auxiliary control ARMV6_CP15_C1_AUX_*


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ARMv6 CP15 C1 coprocessor access control ARMV6_CP15_C1_CP*


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ARMv6 CP15 C2 translation table base ARMV6_CP15_C2_TTBR_*


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ARMv6 CP15 C3 domain access control ARMV6_CP15_C3_DOMAIN*


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ARMv6 floating-point exception ARMV6_FPEXC_*


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ARMv6 level one descriptor type ARMV6_L1D_TYPE_*


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ARMv6 level one descriptor flag ARMV6_L1D_FLAG_*


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ARMv6 level one descriptor mask ARMV6_L1D_*_MASK


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ARMv6 level one descriptor TEX value ARMV6_L1D_TEX*


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ARMv6 level one descriptor AP value ARMV6_L1D_AP*


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ARMv6 level one descriptor permission value ARMV6_L1D_ACCESS_*


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ARMv6 level one descriptor cache value ARMV6_L1D_CACHE_*


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ARMv6 level two descriptor type ARMV6_L2D_TYPE_*


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ARMv6 level two descriptor flag ARMV6_L2D_FLAG_*


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ARMv6 level two descriptor mask ARMV6_L2D_*_MASK


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ARMv6 level two descriptor large TEX value ARMV6_L2D_LARGE_TEX*


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ARMv6 level two descriptor small TEX value ARMV6_L2D_SMALL_TEX*


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ARMv6 level two descriptor AP value ARMV6_L2D_AP*


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ARMv6 level two descriptor permission value ARMV6_L2D_ACCESS_*


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ARMv6 level two descriptor large cache value ARMV6_L2D_LARGE_CACHE_*


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ARMv6 level two descriptor small cache value ARMV6_L2D_SMALL_CACHE_*


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ARMv6 specific constants ARMV6_*


Type definitions



ARMv6 page table initialization

TARMv6PageTableInit = procedure;

ARMv6 dispatch IRQ

TARMv6DispatchIRQ = function(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;

ARMv6 dispatch FIQ

TARMv6DispatchFIQ = function(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;

ARMv6 dispatch SWI

TARMv6DispatchSWI = function(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle;


Public variables



ARMv6 specific variables

ARMv6Initialized:Boolean;
ARMv6DummySTREX:LongWord; Variable to allow a dummy STREX operation to be performed after each context switch as required by ARM documentation

Page table handlers

ARMv6PageTableInitHandler:TARMv6PageTableInit;

IRQ handlers

ARMv6DispatchIRQHandler:TARMv6DispatchIRQ;

FIQ handlers

ARMv6DispatchFIQHandler:TARMv6DispatchFIQ;

SWI handlers

ARMv6DispatchSWIHandler:TARMv6DispatchSWI;


Function declarations



Initialization functions

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procedure ARMv6Init;
Description: To be documented


ARMv6 platform functions

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procedure ARMv6CPUInit; assembler; nostackframe;
Description: To be documented


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procedure ARMv6FPUInit; assembler; nostackframe;
Description: To be documented


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procedure ARMv6MMUInit;
Description: To be documented


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procedure ARMv6CacheInit; assembler; nostackframe;
Description: To be documented


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procedure ARMv6PageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU


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procedure ARMv6SystemCall(Number:LongWord; Param1,Param2,Param3:PtrUInt); assembler; nostackframe;
Description: To be documented


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function ARMv6CPUGetMode:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6CPUGetState:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6CPUGetMainID:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6CPUGetModel:LongWord;
Description: To be documented


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function ARMv6CPUGetRevision:LongWord;
Description: To be documented


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function ARMv6CPUGetDescription:String;
Description: To be documented


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function ARMv6FPUGetState:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6L1CacheGetType:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6L1DataCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6L1DataCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6L1InstructionCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6L1InstructionCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented


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procedure ARMv6Halt; assembler; nostackframe; public name '_haltproc';
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


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procedure ARMv6Pause; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


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procedure ARMv6WaitForEvent; assembler; nostackframe;
Description: Wait For Event not available in ARMv6, do a Wait For Interrupt instead


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procedure ARMv6WaitForInterrupt; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


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procedure ARMv6DataMemoryBarrier; assembler; nostackframe;
Description: Perform a data memory barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6DataSynchronizationBarrier; assembler; nostackframe;
Description: Perform a data synchronization barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6InstructionMemoryBarrier; assembler; nostackframe;
Description: Perform a Flush Prefetch Buffer operation


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procedure ARMv6InvalidateTLB; assembler; nostackframe;
Description: Perform an invalidate entire TLB (Unlocked/Unified) operation using the c8 (TLB Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateDataTLB; assembler; nostackframe;
Description: Perform an invalidate data TLB (Unlocked/Data) operation using the c8 (TLB Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateInstructionTLB; assembler; nostackframe;
Description: Perform an invalidate instruction TLB (Unlocked/Instruction) operation using the c8 (TLB Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateCache; assembler; nostackframe;
Description: Perform an invalidate both caches operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanDataCache; assembler; nostackframe;
Description: Perform a clean entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateDataCache; assembler; nostackframe;
Description: Perform an invalidate entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanAndInvalidateDataCache; assembler; nostackframe;
Description: Perform a clean and invalidate entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateInstructionCache; assembler; nostackframe;
Description: Perform an invalidate entire instruction cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanDataCacheRangeInternal(Address:PtrUInt; Size:LongWord); assembler; nostackframe;
Description: Perform a clean data cache range operation


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procedure ARMv6CleanDataCacheRange(Address:PtrUInt; Size:LongWord);
Description: Perform a clean data cache range, limiting the size for each operation to 4MB because some processors fail to correctly operate with larger ranges


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procedure ARMv6InvalidateDataCacheRangeInternal(Address:PtrUInt; Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate data cache range operation


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procedure ARMv6InvalidateDataCacheRange(Address:PtrUInt; Size:LongWord);
Description: Perform an invalidate data cache range, limiting the size for each operation to 4MB because some processors fail to correctly operate with larger ranges


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procedure ARMv6CleanAndInvalidateDataCacheRangeInternal(Address:PtrUInt; Size:LongWord); assembler; nostackframe;
Description: Perform a clean and invalidate data cache range operation


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procedure ARMv6CleanAndInvalidateDataCacheRange(Address:PtrUInt; Size:LongWord);
Description: Perform a clean and invalidate data cache range, limiting the size for each operation to 4MB because some processors fail to correctly operate with larger ranges


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procedure ARMv6InvalidateInstructionCacheRangeInternal(Address:PtrUInt; Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate instruction cache range operation


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procedure ARMv6InvalidateInstructionCacheRange(Address:PtrUInt; Size:LongWord);
Description: Perform an invalidate instruction cache range operation, limiting the size for each operation to 4MB because some processors fail to correctly operate with larger ranges


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procedure ARMv6FlushPrefetchBuffer; assembler; nostackframe;
Description: Perform a Flush Prefetch Buffer operation


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procedure ARMv6FlushBranchTargetCache; assembler; nostackframe;
Description: Perform a Flush Entire Branch Target Cache


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procedure ARMv6ContextSwitch(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a thread yielding, sleeping or waiting


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procedure ARMv6ContextSwitchIRQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of an interrupt request (IRQ)


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procedure ARMv6ContextSwitchFIQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a fast interrupt request (FIQ)


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procedure ARMv6ContextSwitchSWI(OldStack,NewStack:Pointer; NewThread:TThreadHandle);
Description: Perform a context switch from one thread to another as a result of a software interrupt (SWI)


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function ARMv6InterlockedOr(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic OR operation using LDREX/STREX


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function ARMv6InterlockedXor(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic XOR operation using LDREX/STREX


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function ARMv6InterlockedAnd(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic AND operation using LDREX/STREX


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function ARMv6InterlockedDecrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic decrement operation using LDREX/STREX


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function ARMv6InterlockedIncrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic increment operation using LDREX/STREX


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function ARMv6InterlockedExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic exchange operation using LDREX/STREX


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function ARMv6InterlockedAddExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic add and exchange operation using LDREX/STREX


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function ARMv6InterlockedCompareExchange(var Target:LongInt; Source,Compare:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic compare and exchange operation using LDREX/STREX


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procedure ARMv6PageTableGetEntry(Address:PtrUInt; var Entry:TPageTableEntry);
Description: Get and Decode the entry in the Page Table that corresponds to the supplied virtual address


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function ARMv6PageTableSetEntry(const Entry:TPageTableEntry):LongWord;
Description: Encode and Set an entry in the Page Table that corresponds to the supplied virtual address


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function ARMv6VectorTableGetEntry(Number:LongWord):PtrUInt;
Description: Return the address of the specified vector table entry number


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function ARMv6VectorTableSetEntry(Number:LongWord; Address:PtrUInt):LongWord;
Description: Set the supplied address as the value of the specified vector table entry number


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function ARMv6FirstBitSet(Value:LongWord):LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6CountLeadingZeros(Value:LongWord):LongWord; assembler; nostackframe;
Description: Equivalent of the GCC Builtin function __builtin_clz


ARMv6 thread functions

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procedure ARMv6PrimaryInit; assembler; nostackframe;
Description: To be documented


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function ARMv6SpinLock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry


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function ARMv6SpinUnlock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry


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function ARMv6SpinLockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and save the previous IRQ state


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function ARMv6SpinUnlockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ state


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function ARMv6SpinLockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable FIQ and save the previous FIQ state


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function ARMv6SpinUnlockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous FIQ state


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function ARMv6SpinLockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and FIQ and save the previous IRQ/FIQ state


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function ARMv6SpinUnlockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ/FIQ state


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function ARMv6SpinCheckIRQ(Spin:PSpinEntry):Boolean;
Description: To be documented


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function ARMv6SpinCheckFIQ(Spin:PSpinEntry):Boolean;
Description: To be documented


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function ARMv6SpinExchangeIRQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented


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function ARMv6SpinExchangeFIQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented


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function ARMv6MutexLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Mutex entry


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function ARMv6MutexUnlock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Mutex entry


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function ARMv6MutexTryLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Try to lock an existing Mutex entry


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function ARMv6ThreadGetCurrent:TThreadHandle; assembler; nostackframe;
Description: Get the current thread Id from the c13 (Thread and process ID) register of system control coprocessor CP15


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function ARMv6ThreadSetCurrent(Thread:TThreadHandle):LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6ThreadSetupStack(StackBase:Pointer; StartProc:TThreadStart; ReturnProc:TThreadEnd; Parameter:Pointer):Pointer;
Description: Set up the context record and arguments on the stack for a new thread


ARMv6 IRQ functions

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function ARMv6DispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented


ARMv6 FIQ functions

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function ARMv6DispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented


ARMv6 SWI functions

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function ARMv6DispatchSWI(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle; inline;
Description: To be documented


ARMv6 interrupt functions

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procedure ARMv6ResetHandler; assembler; nostackframe;
Description: To be documented


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procedure ARMv6UndefinedInstructionHandler; assembler; nostackframe;
Description: Handle an undefined instruction exception


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procedure ARMv6SoftwareInterruptHandler; assembler; nostackframe;
Description: Handle a software interrupt (SWI) from a system call (SVC)


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procedure ARMv6PrefetchAbortHandler; assembler; nostackframe;
Description: Handle a prefetch abort exception


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procedure ARMv6DataAbortHandler; assembler; nostackframe;
Description: Handle a data abort exception


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procedure ARMv6ReservedHandler; assembler; nostackframe;
Description: To be documented


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procedure ARMv6IRQHandler; assembler; nostackframe;
Description: Handle an interrupt request IRQ from an interrupt source


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procedure ARMv6FIQHandler; assembler; nostackframe;
Description: Handle a fast interrupt request FIQ from an interrupt source


ARMv6 helper functions

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function ARMv6GetFPEXC:LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6GetFPSCR:LongWord; assembler; nostackframe;
Description: To be documented


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procedure ARMv6StartMMU; assembler; nostackframe;
Description: To be documented


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function ARMv6GetPageTableCoarse(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Coarse Page Table entry (1MB)


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function ARMv6SetPageTableCoarse(Address,CoarseAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Coarse Page Table entry (1MB)


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function ARMv6GetPageTableLarge(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Large Page Table entry (64KB)


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function ARMv6SetPageTableLarge(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Large Page Table entry (64KB)


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function ARMv6GetPageTableSmall(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Small Page Table entry (4KB)


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function ARMv6SetPageTableSmall(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Small Page Table entry (4KB)


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function ARMv6GetPageTableSection(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Page Table Section (1MB) or Supersection (16MB)


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function ARMv6SetPageTableSection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Section (1MB)


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function ARMv6SetPageTableSupersection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Supersection (16MB)


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