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Description
ARM PrimeCell PL180/181 Multimedia Card Interface Driver unit
The PL180/181 Multimedia Card is an ARM peripheral that is compatible with MMC multimedia cards and SD secure digital cards in memory mapped I/O format compatible with the ARM advanced peripheral bus (APB).
The design of the Pl180/181 allows for multiple cards per controller however this driver currently only supports attaching one card.
Constants
[Expand]
PL18X specific constants PL180_MMCI_*
PL180_MMCI_DESCRIPTION = 'ARM PrimeCell PL180 MMCI Host';
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Description of PL180 device
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PL181_MMCI_DESCRIPTION = 'ARM PrimeCell PL181 MMCI Host';
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Description of PL181 device
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[Expand]
PL18X power control register PL18X_MMCI_POWER_*
PL18X_MMCI_POWER = $000;
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PL18X_MMCI_POWER_OFF = $00;
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Power-off
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| Bits 1:0 - $01 Reserved
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PL18X_MMCI_POWER_UP = $02;
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Power-up
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PL18X_MMCI_POWER_ON = $03;
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Power-on
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| Bits 5:2 - Output Voltage
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PL18X_MMCI_POWER_OD = (1 shl 6);
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MCICMD output control
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PL18X_MMCI_POWER_ROD = (1 shl 7);
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Rod control
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| The ST Micro version does not have ROD and reuses the voltage registers for direction settings
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PL18X_MMCI_POWER_ST_DATA2DIREN = (1 shl 2);
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PL18X_MMCI_POWER_ST_CMDDIREN = (1 shl 3);
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PL18X_MMCI_POWER_ST_DATA0DIREN = (1 shl 4);
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PL18X_MMCI_POWER_ST_DATA31DIREN = (1 shl 5);
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PL18X_MMCI_POWER_ST_FBCLKEN = (1 shl 7);
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PL18X_MMCI_POWER_ST_DATA74DIREN = (1 shl 8);
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[Expand]
PL18X clock control register PL18X_MMCI_CLOCK*
PL18X_MMCI_CLOCK = $004;
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PL18X_MMCI_CLOCK_ENABLE = (1 shl 8);
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Enable MCI bus clock: 0 = Clock disabled / 1 = Clock enabled
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PL18X_MMCI_CLOCK_PWRSAVE = (1 shl 9);
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Disable MCI clock output when bus is idle: 0 = Always enabled / 1 = Clock enabled when bus is active
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PL18X_MMCI_CLOCK_BYPASS = (1 shl 10);
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Enable bypass of clock divide logic: 0 = Disable bypass / 1 = Enable bypass
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PL18X_MMCI_CLOCK_4BIT_BUS = (1 shl 11);
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Enable wide bus mode: 0 = Standard bus mode (only MCIDAT0 used) / 1 = Wide bus mode (MCIDAT3:0 used)
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| 8bit wide buses, hardware flow contronl, negative edges and clock inversion supported in ST Micro U300 and Ux500 versions
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PL18X_MMCI_CLOCK_ST_8BIT_BUS = (1 shl 12);
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PL18X_MMCI_CLOCK_ST_U300_HWFCEN = (1 shl 13);
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PL18X_MMCI_CLOCK_ST_UX500_NEG_EDGE = (1 shl 13);
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PL18X_MMCI_CLOCK_ST_UX500_HWFCEN = (1 shl 14);
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PL18X_MMCI_CLOCK_ST_UX500_CLK_INV = (1 shl 15);
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| Modified PL180 on Versatile Express platform
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PL18X_MMCI_CLOCK_ARM_HWFCEN = (1 shl 12);
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| Modified on Qualcomm Integrations
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PL18X_MMCI_CLOCK_QCOM_WIDEBUS_8 = (1 shl 10) or (1 shl 11);
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PL18X_MMCI_CLOCK_QCOM_FLOWENA = (1 shl 12);
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PL18X_MMCI_CLOCK_QCOM_INVERTOUT = (1 shl 13);
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| Select in latch data and command in
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PL18X_MMCI_CLOCK_QCOM_SELECT_IN_FBCLK = (1 shl 15);
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PL18X_MMCI_CLOCK_QCOM_SELECT_IN_DDR_MODE = (1 shl 14) or (1 shl 15);
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[Expand]
PL18X argument register PL18X_MMCI_ARGUMENT*
PL18X_MMCI_ARGUMENT = $008;
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| Bits 31:0 Command Argument
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[Expand]
PL18X command register PL18X_MMCI_COMMAND*
PL18X_MMCI_COMMAND = $00c;
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| Bits 5:0 Command Index
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PL18X_MMCI_CPSM_RESPONSE = (1 shl 6);
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If set, CPSM waits for a response
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PL18X_MMCI_CPSM_LONGRSP = (1 shl 7);
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If set, CPSM receives a 136-bit long response
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PL18X_MMCI_CPSM_INTERRUPT = (1 shl 8);
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If set, CPSM disables command timer and waits for interrupt request
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PL18X_MMCI_CPSM_PENDING = (1 shl 9);
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If set, CPSM waits for CmdPend before it starts sending a command
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PL18X_MMCI_CPSM_ENABLE = (1 shl 10);
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If set, CPSM is enabled
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| Argument flag extenstions in the ST Micro versions
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PL18X_MMCI_CPSM_ST_SDIO_SUSP = (1 shl 11);
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PL18X_MMCI_CPSM_ST_ENCMD_COMPL = (1 shl 12);
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PL18X_MMCI_CPSM_ST_NIEN = (1 shl 13);
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PL18X_MMCI_CPSM_ST_CE_ATACMD = (1 shl 14);
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| Modified on Qualcomm Integrations
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PL18X_MMCI_CPSM_QCOM_DATCMD = (1 shl 12);
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PL18X_MMCI_CPSM_QCOM_MCIABORT = (1 shl 13);
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PL18X_MMCI_CPSM_QCOM_CCSENABLE = (1 shl 14);
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PL18X_MMCI_CPSM_QCOM_CCSDISABLE = (1 shl 15);
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PL18X_MMCI_CPSM_QCOM_AUTO_CMD19 = (1 shl 16);
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PL18X_MMCI_CPSM_QCOM_AUTO_CMD21 = (1 shl 21);
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[Expand]
PL18X command response register PL18X_MMCI_RESPCMD*
PL18X_MMCI_RESPCMD = $010;
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| Bits 5:0 Response command index
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| Bits 31:6 Reserved
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[Expand]
PL18X response registers PL18X_MMCI_RESPONSE*
PL18X_MMCI_RESPONSE0 = $014;
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PL18X_MMCI_RESPONSE1 = $018;
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PL18X_MMCI_RESPONSE2 = $01c;
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PL18X_MMCI_RESPONSE3 = $020;
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| Bits 31:0 Card Status
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[Expand]
PL18X data timer register PL18X_MMCI_DATATIMER*
PL18X_MMCI_DATATIMER = $024;
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| Bits 31:0 Data Timeout Period
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[Expand]
PL18X data length register PL18X_MMCI_DATALENGTH*
PL18X_MMCI_DATALENGTH = $028;
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| Bits 15:0 Data Length Value
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| Bits 31:16 Reserved
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[Expand]
PL18X data control register PL18X_MMCI_DATACTRL*
PL18X_MMCI_DATACTRL = $02c;
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PL18X_MMCI_DPSM_ENABLE = (1 shl 0);
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Data transfer enabled
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PL18X_MMCI_DPSM_DIRECTION = (1 shl 1);
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Data transfer direction: 0 = From controller to card / 1 = From card to controller
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PL18X_MMCI_DPSM_MODE = (1 shl 2);
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Data transfer mode: 0 = Block data transfer / 1 = Stream data transfer
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PL18X_MMCI_DPSM_BLOCKSIZE = (1 shl 4);
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Data block length
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| Control register extensions in the ST Micro U300 and Ux500 versions
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PL18X_MMCI_ST_DPSM_RWSTART = (1 shl 8);
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PL18X_MMCI_ST_DPSM_RWSTOP = (1 shl 9);
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PL18X_MMCI_ST_DPSM_RWMOD = (1 shl 10);
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PL18X_MMCI_ST_DPSM_SDIOEN = (1 shl 11);
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| Control register extensions in the ST Micro Ux500 versions
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PL18X_MMCI_ST_DPSM_DMAREQCTL = (1 shl 12);
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PL18X_MMCI_ST_DPSM_DBOOTMODEEN = (1 shl 13);
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PL18X_MMCI_ST_DPSM_BUSYMODE = (1 shl 14);
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PL18X_MMCI_ST_DPSM_DDRMODE = (1 shl 15);
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[Expand]
PL18X data counter register PL18X_MMCI_DATACNT*
PL18X_MMCI_DATACNT = $030;
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| Bits 15:0 Remaining Data
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| Bits 31:16 Reserved
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[Expand]
PL18X status register PL18X_MMCI_STATUS*
PL18X_MMCI_STATUS = $034;
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PL18X_MMCI_CMDCRCFAIL = (1 shl 0);
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PL18X_MMCI_DATACRCFAIL = (1 shl 1);
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PL18X_MMCI_CMDTIMEOUT = (1 shl 2);
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PL18X_MMCI_DATATIMEOUT = (1 shl 3);
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PL18X_MMCI_TXUNDERRUN = (1 shl 4);
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PL18X_MMCI_RXOVERRUN = (1 shl 5);
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PL18X_MMCI_CMDRESPEND = (1 shl 6);
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PL18X_MMCI_CMDSENT = (1 shl 7);
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PL18X_MMCI_DATAEND = (1 shl 8);
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PL18X_MMCI_STARTBITERR = (1 shl 9);
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PL18X_MMCI_DATABLOCKEND = (1 shl 10);
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PL18X_MMCI_CMDACTIVE = (1 shl 11);
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PL18X_MMCI_TXACTIVE = (1 shl 12);
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PL18X_MMCI_RXACTIVE = (1 shl 13);
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PL18X_MMCI_TXFIFOHALFEMPTY = (1 shl 14);
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PL18X_MMCI_RXFIFOHALFFULL = (1 shl 15);
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PL18X_MMCI_TXFIFOFULL = (1 shl 16);
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PL18X_MMCI_RXFIFOFULL = (1 shl 17);
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PL18X_MMCI_TXFIFOEMPTY = (1 shl 18);
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PL18X_MMCI_RXFIFOEMPTY = (1 shl 19);
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PL18X_MMCI_TXDATAAVLBL = (1 shl 20);
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PL18X_MMCI_RXDATAAVLBL = (1 shl 21);
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| Extended status bits for the ST Micro variants
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PL18X_MMCI_ST_SDIOIT = (1 shl 22);
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PL18X_MMCI_ST_CEATAEND = (1 shl 23);
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PL18X_MMCI_ST_CARDBUSY = (1 shl 24);
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[Expand]
PL18X clear register PL18X_MMCI_CLEAR*
PL18X_MMCI_CLEAR = $038;
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PL18X_MMCI_CMDCRCFAILCLR = (1 shl 0);
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PL18X_MMCI_DATACRCFAILCLR = (1 shl 1);
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PL18X_MMCI_CMDTIMEOUTCLR = (1 shl 2);
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PL18X_MMCI_DATATIMEOUTCLR = (1 shl 3);
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PL18X_MMCI_TXUNDERRUNCLR = (1 shl 4);
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PL18X_MMCI_RXOVERRUNCLR = (1 shl 5);
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PL18X_MMCI_CMDRESPENDCLR = (1 shl 6);
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PL18X_MMCI_CMDSENTCLR = (1 shl 7);
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PL18X_MMCI_DATAENDCLR = (1 shl 8);
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PL18X_MMCI_STARTBITERRCLR = (1 shl 9);
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PL18X_MMCI_DATABLOCKENDCLR = (1 shl 10);
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| Extended status bits for the ST Micro variants
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PL18X_MMCI_ST_SDIOITC = (1 shl 22);
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PL18X_MMCI_ST_CEATAENDC = (1 shl 23);
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PL18X_MMCI_ST_BUSYENDC = (1 shl 24);
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[Expand]
PL18X interrupt mask registers PL18X_MMCI_MASK*
PL18X_MMCI_MASK0 = $03c;
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PL18X_MMCI_MASK1 = $040;
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PL18X_MMCI_CMDCRCFAILMASK = (1 shl 0);
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PL18X_MMCI_DATACRCFAILMASK = (1 shl 1);
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PL18X_MMCI_CMDTIMEOUTMASK = (1 shl 2);
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PL18X_MMCI_DATATIMEOUTMASK = (1 shl 3);
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PL18X_MMCI_TXUNDERRUNMASK = (1 shl 4);
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PL18X_MMCI_RXOVERRUNMASK = (1 shl 5);
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PL18X_MMCI_CMDRESPENDMASK = (1 shl 6);
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PL18X_MMCI_CMDSENTMASK = (1 shl 7);
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PL18X_MMCI_DATAENDMASK = (1 shl 8);
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PL18X_MMCI_STARTBITERRMASK = (1 shl 9);
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PL18X_MMCI_DATABLOCKENDMASK = (1 shl 10);
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PL18X_MMCI_CMDACTIVEMASK = (1 shl 11);
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PL18X_MMCI_TXACTIVEMASK = (1 shl 12);
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PL18X_MMCI_RXACTIVEMASK = (1 shl 13);
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PL18X_MMCI_TXFIFOHALFEMPTYMASK = (1 shl 14);
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PL18X_MMCI_RXFIFOHALFFULLMASK = (1 shl 15);
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PL18X_MMCI_TXFIFOFULLMASK = (1 shl 16);
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PL18X_MMCI_RXFIFOFULLMASK = (1 shl 17);
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PL18X_MMCI_TXFIFOEMPTYMASK = (1 shl 18);
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PL18X_MMCI_RXFIFOEMPTYMASK = (1 shl 19);
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PL18X_MMCI_TXDATAAVLBLMASK = (1 shl 20);
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PL18X_MMCI_RXDATAAVLBLMASK = (1 shl 21);
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| Extended status bits for the ST Micro variants
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PL18X_MMCI_ST_SDIOITMASK = (1 shl 22);
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PL18X_MMCI_ST_CEATAENDMASK = (1 shl 23);
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PL18X_MMCI_ST_BUSYEND = (1 shl 24);
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[Expand]
PL18X SD card select register PL18X_MMCI_SELECT*
PL18X_MMCI_SELECT = $044;
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[Expand]
PL18X FIFO counter register PL18X_MMCI_FIFOCNT*
PL18X_MMCI_FIFOCNT = $048;
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[Expand]
PL18X data FIFO register PL18X_MMCI_FIFO*
PL18X_MMCI_FIFO = $080;
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To $0bc
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[Expand]
PL18X peripheral identification register PL18X_MMCI_PERIPHID*
PL18X_MMCI_PERIPHID = $FE0;
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[Expand]
PL18X PrimeCell identification register PL18X_MMCI_PCELLID*
PL18X_MMCI_PCELLID = $FF0;
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PL18X_MMCI_IRQENABLE = (PL18X_MMCI_CMDCRCFAILMASK or PL18X_MMCI_DATACRCFAILMASK or PL18X_MMCI_CMDTIMEOUTMASK or PL18X_MMCI_DATATIMEOUTMASK or PL18X_MMCI_TXUNDERRUNMASK or PL18X_MMCI_RXOVERRUNMASK or PL18X_MMCI_CMDRESPENDMASK or PL18X_MMCI_CMDSENTMASK or PL18X_MMCI_STARTBITERRMASK);
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| These interrupts are directed to IRQ1 when two IRQ lines are available
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PL18X_MMCI_IRQ1MASK = (PL18X_MMCI_RXFIFOHALFFULLMASK or PL18X_MMCI_RXDATAAVLBLMASK or PL18X_MMCI_TXFIFOHALFEMPTYMASK);
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Type definitions
PL18X version Id
[Expand]
PPL18XVersionID = ^TPL18XVersionID;
TPL18XVersionID = record
PeripheralID:LongWord;
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PeripheralMask:LongWord;
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VersionData:PPL18XVersionData;
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PL18X version data
[Expand]
PPL18XVersionData = ^TPL18XVersionData;
TPL18XVersionData = record
Name:String;
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Name of the device
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ClockRegister:LongWord;
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Default value for MCICLOCK register
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ClockEnable:LongWord;
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Enable value for MMCICLOCK register
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Clock8BitEnable:LongWord;
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Enable value for 8 bit bus
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ClockNegativeEdgeEnable:LongWord;
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Enable value for inverted data/cmd output
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DataLengthBits:LongWord;
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Number of bits in the MMCIDATALENGTH register
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FIFOSize:LongWord;
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Number of bytes that can be written when MMCI_TXFIFOEMPTY is asserted (likewise for RX)
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FIFOHalfSize:LongWord;
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Number of bytes that can be written when MCI_TXFIFOHALFEMPTY is asserted (likewise for RX)
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DataCommandEnable:LongWord;
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Enable value for data commands
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DataControlMaskDDR:LongWord;
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DDR mode mask in MMCIDATACTRL register
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DataControlMaskSDIO:LongWord;
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SDIO enable mask in MMCIDATACTRL register
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STSDIO:LongBool;
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Enable ST specific SDIO logic
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STClockDivider:LongBool;
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True if using a ST-specific clock divider algorithm
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BlockSizeDataControl16:LongBool;
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True if Block size is at b16..b30 position in MMCIDATACTRL register
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BlockSizeDataControl4:LongBool;
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True if Block size is at b4..b16 position in MMCIDATACTRL register
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PowerPowerUp:LongWord;
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Power up value for MMCIPOWER register
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ClockMaximum:LongWord;
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Maximum clk frequency supported by the controller
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SignalDirection:LongBool;
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Input/out direction of bus signals can be indicated
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PowerClockGate:LongBool;
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MMCIPOWER register must be used to gate the clock
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BusyDetect:LongBool;
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True if busy detection on dat0 is supported
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PowerNoPower:LongBool;
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Bits in MMCIPOWER don't control external power supply
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ExplicitMClockControl:LongBool;
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Enable explicit mclk control in driver
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QualcommFIFO:LongBool;
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Enable Qualcomm specific FIFO PIO read logic
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QualcommDMA:LongBool;
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Enable Qualcomm specific DMA glue for DMA transfers
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ReversedIRQ:LongBool;
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Handle data irq before cmd irq
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PL18X MMCI registers
[Expand]
PPL18XMMCIRegisters = ^TPL18XMMCIRegisters;
TPL18XMMCIRegisters = record
| Note: Layout of the PL18X registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0172a/i1006458.html)
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Power:LongWord;
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Power control register
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Clock:LongWord;
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Clock control register
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Argument:LongWord;
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Argument register
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Command:LongWord;
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Command register
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RespCmd:LongWord;
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Response command register
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Response0:LongWord;
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Response register
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Response1:LongWord;
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Response register
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Response2:LongWord;
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Response register
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Response3:LongWord;
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Response register
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DataTimer:LongWord;
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Data timer
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DataLength:LongWord;
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Data length register
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DataCtrl:LongWord;
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Data control register
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DataCnt:LongWord;
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Data counter
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Status:LongWord;
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Status register
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Clear:LongWord;
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Clear register
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Mask0:LongWord;
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Interrupt 0 mask register
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Mask1:LongWord;
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Interrupt 1 mask register
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Select:LongWord;
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Secure digital memory card select register
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FifoCnt:LongWord;
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FIFO counter
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Reserved:array[$4C..$7C] of Byte;
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Reserved
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FIFO:LongWord;
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Data FIFO register (0x80 to 0xBC)
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PL18X SDHCI get RXFIFO count
TPL18XSDHCIGetRXFIFOCount = function(SDHCI:PPL18XSDHCIHost; Status,Remain:LongWord):LongWord;
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PL18X SDHCI host
[Expand]
PPL18XSDHCIHost = ^TPL18XSDHCIHost;
TPL18XSDHCIHost = record
| SDHCI Properties
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SDHCI:TSDHCIHost;
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| PL18X Properties
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IRQ0:LongWord;
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First host IRQ line
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IRQ1:LongWord;
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Second host IRQ line
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EnableFIQ:LongBool;
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Use FIQ instead of IRQ
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SingleIRQ:LongBool;
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The host only has a single IRQ line instead of the standard 2 lines
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Registers:PPL18XMMCIRegisters;
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Host registers
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Version:PPL18XVersionData;
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Host version data
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ClockRegister:LongWord;
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Current clock register value
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PowerRegister:LongWord;
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Current power register value
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DataCtrlRegister:LongWord;
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Current data control register value
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BusyStatus:LongWord;
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Current Busy Status for ST Micro variants
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GetRXFIFOCount:TPL18XSDHCIGetRXFIFOCount;
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Model specific GetRXFIFOCount function
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Public variables
PL18X specific variables
PL18X_MMCI_FIQ_ENABLED:LongBool;
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The SDHCI uses Fast Interrupt Requests (FIQ) instead of IRQ
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PL18X_MMCI_MIN_FREQ:LongWord = 400000;
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Minimum clock frequency for SDHCI (Default minimum of 400KHz)
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PL18X_MMCI_MAX_FREQ:LongWord = 400000;
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Maximum clock frequency for SDHCI (Default maximum of 400KHz)
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Function declarations
Initialization functions
[Expand]
procedure PL18XInit;
Description: Initialize the PL18X unit and version table
| Note
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Called only during system startup
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PL18X functions
[Expand]
function PL180SDHCICreate(Address:PtrUInt; const Name:String; IRQ0,IRQ1,ClockMinimum,ClockMaximum:LongWord; CardDetect:TMMCDeviceGetCardDetect = nil; WriteProtect:TMMCDeviceGetWriteProtect = nil):PSDHCIHost;
Description: Create and register a new PL180 SDHCI device which can be accessed using the SDHCI API
| Address
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The address of the PL180 registers
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| Name
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The text description of this device which will show in the device list (Optional)
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| IRQ0
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The interrupt 0 number for the PL180
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| IRQ1
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The interrupt 1 number for the PL180
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| ClockMinimum
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The minimum frequency for the Pl180 clock
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| ClockMaximum
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The maximum frequency for the Pl180 clock
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| Return
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Pointer to the new SDHCI device or nil if the SDHCI device could not be created
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[Expand]
function PL181SDHCICreate(Address:PtrUInt; const Name:String; IRQ0,IRQ1,ClockMinimum,ClockMaximum:LongWord; CardDetect:TMMCDeviceGetCardDetect = nil; WriteProtect:TMMCDeviceGetWriteProtect = nil):PSDHCIHost;
Description: Create and register a new PL181 SDHCI device which can be accessed using the SDHCI API
| Address
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The address of the PL181 registers
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| Name
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The text description of this device which will show in the device list (Optional)
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| IRQ0
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The interrupt 0 number for the PL181
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| IRQ1
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The interrupt 1 number for the PL181
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| ClockMinimum
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The minimum frequency for the Pl181 clock
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| ClockMaximum
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The maximum frequency for the Pl181 clock
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| Return
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Pointer to the new SDHCI device or nil if the SDHCI device could not be created
|
[Expand]
function PL18XSDHCIDestroy(SDHCI:PSDHCIHost):LongWord;
Description: Stop, deregister and destroy a PL18X SDHCI device created by this driver
| SDHCI
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The SDHCI device to destroy
|
| Return
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ERROR_SUCCESS if completed or another error code on failure
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PL18X MMC functions
[Expand]
function PL18XMMCDeviceGetCardDetect(MMC:PMMCDevice):LongWord;
Description: Implementation of MMCDeviceGetCardDetect API for PL18X SDHCI
| Note
|
Not intended to be called directly by applications, use MMCDeviceGetCardDetect instead.
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[Expand]
function PL18XMMCDeviceGetWriteProtect(MMC:PMMCDevice):LongWord;
Description: Implementation of MMCDeviceGetWriteProtect API for PL18X SDHCI
| Note
|
Not intended to be called directly by applications, use MMCDeviceGetWriteProtect instead.
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[Expand]
function PL18XMMCDeviceSendCommand(MMC:PMMCDevice; Command:PMMCCommand):LongWord;
Description: Implementation of MMCDeviceSendCommand API for PL18X SDHCI
| Note
|
Not intended to be called directly by applications, use MMCDeviceSendCommand instead.
|
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function PL18XMMCDeviceSetIOS(MMC:PMMCDevice):LongWord;
Description: Implementation of MMCDeviceSetIOS API for PL18X SDHCI
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Not intended to be called directly by applications, use MMCDeviceSetIOS instead.
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PL18X SDHCI functions
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function PL18XSDHCIHostStart(SDHCI:PSDHCIHost):LongWord;
Description: Implementation of SDHCIHostStart API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostStart instead.
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function PL18XSDHCIHostStop(SDHCI:PSDHCIHost):LongWord;
Description: Implementation of SDHCIHostStop API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostStop instead.
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function PL18XSDHCIHostReadByte(SDHCI:PSDHCIHost; Reg:LongWord):Byte;
Description: Implementation of SDHCIHostReadByte API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostReadByte instead.
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function PL18XSDHCIHostReadWord(SDHCI:PSDHCIHost; Reg:LongWord):Word;
Description: Implementation of SDHCIHostReadWord API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostReadWord instead.
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function PL18XSDHCIHostReadLong(SDHCI:PSDHCIHost; Reg:LongWord):LongWord;
Description: Implementation of SDHCIHostReadLong API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostReadLong instead.
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procedure PL18XSDHCIHostWriteByte(SDHCI:PSDHCIHost; Reg:LongWord; Value:Byte);
Description: Implementation of SDHCIHostWriteByte API for PL18X SDHCI
| Note
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Not intended to be called directly by applications, use SDHCIHostWriteByte instead.
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procedure PL18XSDHCIHostWriteWord(SDHCI:PSDHCIHost; Reg:LongWord; Value:Word);
Description: Implementation of SDHCIHostWriteWord API for PL18X SDHCI
| Note
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Not intended to be called directly by applications, use SDHCIHostWriteWord instead.
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procedure PL18XSDHCIHostWriteLong(SDHCI:PSDHCIHost; Reg:LongWord; Value:LongWord);
Description: Implementation of SDHCIHostWriteLong API for PL18X SDHCI
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Not intended to be called directly by applications, use SDHCIHostWriteLong instead.
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function PL18XSDHCIHostSetPower(SDHCI:PSDHCIHost; Power:Word):LongWord;
Description: Implementation of SDHCISetPower API for PL18X SDHCI
| Note
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Not intended to be called directly by applications, use SDHCISetPower instead.
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procedure PL18XSDHCIInterruptHandler(SDHCI:PPL18XSDHCIHost);
Description: Interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
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procedure PL18XSDHCIDataInterrupt(SDHCI:PPL18XSDHCIHost; Status:LongWord);
Description: Data interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
Caller must hold the host lock
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procedure PL18XSDHCICommandInterrupt(SDHCI:PPL18XSDHCIHost; Status:LongWord);
Description: Command interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
Caller must hold the host lock
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procedure PL18XSDHCIStopData(SDHCI:PPL18XSDHCIHost);
Description: Data stop handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
Caller must hold the host lock
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procedure PL18XSDHCIPIOInterruptHandler(SDHCI:PPL18XSDHCIHost);
Description: PIO Interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
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function PL18XSHDCIReadPIO(SDHCI:PPL18XSDHCIHost ;Buffer:Pointer; Remain:LongWord):LongWord;
Description: PIO read interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
Caller must hold the host lock
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function PL18XSDHCIWritePIO(SDHCI:PPL18XSDHCIHost; Buffer:Pointer; Remain,Status:LongWord):LongWord;
Description: PIO read interrupt handler for the PL18X SDHCI
| Note
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Not intended to be called directly by applications
Caller must hold the host lock
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PL18X helper functions
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function PL18XGetPeripheralID(SDHCI:PPL18XSDHCIHost):LongWord;
Description: Return the Peripheral Id for a PL18X SDHCI device
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function PL18XGetVersionData(SDHCI:PPL18XSDHCIHost):PPL18XVersionData;
Description: Return the version data for a PL18X SDHCI device based on the Peripheral Id
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function PL18XGetRXFIFOCount(SDHCI:PPL18XSDHCIHost; Status,Remain:LongWord):LongWord;
Description: Determine the receive FIFO count available
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function PL18XQualcommGetRXFIFOCount(SDHCI:PPL18XSDHCIHost; Status,Remain:LongWord):LongWord;
Description: Determine the receive FIFO count available
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procedure PL18XRegisterDelay(SDHCI:PPL18XSDHCIHost);
Description: Delay for the required amount of time after a register write
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procedure PL18XSetClockRegister(SDHCI:PPL18XSDHCIHost; MMC:PMMCDevice; Desired:LongWord);
Description: Setup the current clock rate in the clock register
| Note
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Caller must hold the host lock
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procedure PL18XSetPowerRegister(SDHCI:PPL18XSDHCIHost; Value:LongWord);
Description: Setup the current power state in the power register
| Note
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Caller must hold the host lock
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procedure PL18XSetInterruptMask1(SDHCI:PPL18XSDHCIHost; Mask:LongWord);
Description: Setup the interrupt mask to use either Mask0 or Mask1 depending on configuration
| Note
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Caller must hold the host lock
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procedure PL18XWriteClockRegister(SDHCI:PPL18XSDHCIHost; Clock:LongWord);
Description: Write to the clock register
| Note
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Caller must hold the host lock
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procedure PL18XWritePowerRegister(SDHCI:PPL18XSDHCIHost; Power:LongWord);
Description: Write to the power register
| Note
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Caller must hold the host lock
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procedure PL18XWriteDataCtrlRegister(SDHCI:PPL18XSDHCIHost; DataCtrl:LongWord);
Description: Write to the data control register
| Note
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Caller must hold the host lock
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