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Description
USB Host Controller Driver for the Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller unit
This is a USB Host Controller Driver (HCD) that interfaces with the Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller, henceforth abbreviated as "DWC". This is the USB Host Controller used on the BCM2835 SoC used on the Raspberry Pi.
Please note that there is no publicly available official documentation for this particular piece of hardware, and it uses its own custom host controller interface rather than a standard one such as EHCI. Therefore, this driver was written on a best-effort basis using several sources to glean the necessary hardware details, including the extremely complicated and difficult to understand vendor provided Linux driver.
This file implements the Host Controller Driver Interface defined in TUSBHost. Most importantly, it implements a function to power on and start the host controller (HostStart) and a function to send and receive messages over the USB (HostSubmit).
The DWC is controlled by reading and writing to/from memory-mapped registers. The most important registers are the host channel registers. On this particular hardware, a "host channel", or simply "channel", is a set of registers to which software can read and write to cause transactions to take place on the USB. A fixed number of host channels exist, on the Raspberry Pi there are 8. From the software's perspective, transactions using different host channels can be executed at the same time.
Some of the host channel registers, as well as other registers, deal with interrupts. This driver makes heavy use of these and performs all USB transfers in an interrupt-driven manner. However, due to design flaws in this hardware and in USB 2.0 itself, "interrupt" and "isochronous" transfers still need to make use of software polling when checking for new data, even though each individual transfer is itself interrupt-driven. This means that, for example, if your USB mouse specifies a polling rate of 100 times per second, then it will, unfortunately, be polled 100 times per second in software. For more detail about how interrupts can be controlled on this particular hardware, see the comment above DWCSetupInterrupts. Another important concept is the idea of "packets", "transactions", and "transfers". A USB transfer, such as a single control message or bulk request, may need to be split into multiple packets if it exceeds the endpoint's maximum packet size. Unfortunately, this has to be dealt with explicitly in this code, as this hardware doesn't do it for us. But at least, from the viewpoint of this software, a "transaction" is essentially the same as a "packet".
The "On-The-Go" in the name of this hardware means that it supports the USB On-The-Go protocol, which allows it to act either as a host or a device. However, we only are concerned with it acting as a host, which simplifies our driver.
To simplify the USB core software, a useful design technique (as recommended by the USB 2.0 standard and used in other implementations such as Linux's) is to have the HCD present the root hub as a standard USB hub, even if the root hub is integrated with the host controller and does not appear as a standard hub at the hardware level. This is the case with the DWC, and we implement this design. Therefore, some code in this file deals with faking requests sent to the root hub.
Constants
[Expand]
DWCOTG specific constants DWC_*
DWCOTG_USBHOST_DESCRIPTION = 'DWCOTG USB Host';
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Description of DWCOTG host
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DWC_MAX_CHANNELS = 16;
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Maximum number of DWC host channels
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DWC_SCHEDULER_MAILSLOT_SIZE = SIZE_1K;
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Mailslot size for USB request scheduler
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DWC_SCHEDULER_THREAD_STACK_SIZE = SIZE_32K;
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Stack size of USB request scheduler thread
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DWC_SCHEDULER_THREAD_PRIORITY = THREAD_PRIORITY_HIGHEST;
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Priority of USB request scheduler thread (should be fairly high so that USB transfers can be started as soon as possible)
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DWC_SCHEDULER_THREAD_NAME = 'DWC Transfer Scheduler';
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Name of USB request scheduler thread
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DWC_COMPLETION_THREAD_STACK_SIZE = SIZE_32K;
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Stack size of USB request completion thread
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DWC_COMPLETION_THREAD_PRIORITY = THREAD_PRIORITY_HIGHEST;
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Priority of USB request completion thread (should be fairly high so that USB transfers can be completed as soon as possible)
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DWC_COMPLETION_THREAD_NAME = 'DWC Transfer Completion';
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Name of USB request completion thread
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DWC_RESUBMIT_THREAD_STACK_SIZE = SIZE_32K;
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Stack size of USB request resubmit threads
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DWC_RESUBMIT_THREAD_PRIORITY = THREAD_PRIORITY_CRITICAL;
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Priority of USB request resubmit threads (should be very high since these threads are used for the necessary software polling of interrupt endpoints, which are supposed to have guaranteed bandwidth).
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DWC_RESUBMIT_THREAD_NAME = 'DWC Transfer Resubmit';
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Name of USB request resubmit threads
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[Expand]
DWC USB packet ID DWC_USB_PID_*
| Recognized by the DWC hardware
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DWC_USB_PID_DATA0 = 0;
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DWC_USB_PID_DATA1 = 2;
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DWC_USB_PID_DATA2 = 1;
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DWC_USB_PID_SETUP = 3;
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DWC_USB_PID_MDATA = 3;
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[Expand]
DWC FIFO value DWC_RECEIVE_*
DWC_RECEIVE_WORDS = 1024;
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Size of Rx FIFO in 4-byte words
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DWC_TRANSMIT_WORDS = 1024;
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Size of Non-periodic Tx FIFO in 4-byte words
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DWC_PERIODIC_TRANSMIT_WORDS = 1024;
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Size of Periodic Tx FIFO in 4-byte words
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[Expand]
DWC status code DWC_STATUS_*
DWC_STATUS_SUCCESS = 0;
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DWC_STATUS_STALLED = 1;
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DWC_STATUS_FAILED = 2;
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DWC_STATUS_TRANSFER_RESUBMIT = 3;
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DWC_STATUS_TRANSFER_RESTART = 4;
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DWC_STATUS_TRANSACTION_RESTART = 5;
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DWC_STATUS_HOST_PORT_CHANGE = 6;
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DWC_STATUS_ROOT_HUB_REQUEST = 7;
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DWC_STATUS_INVALID = 8;
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DWC_STATUS_CANCELLED = 9;
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[Expand]
DWC complete split DWC_COMPLETE_SPLIT_*
DWC_SPLIT_ERROR_RETRIES = 3;
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DWC_COMPLETE_SPLIT_RETRIES = 10;
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[Expand]
DWC register value DWC_OTG_CTRL_*
| TDWCRegisters: 0x0000 : OTG Control Register
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DWC_OTG_CTRL_HST_SET_HNP_EN = (1 shl 10);
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[Expand]
DWC AHB configuration DWC_AHB_*
| TDWCRegisters: 0x0008 : AHB Configuration Register
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DWC_AHB_INTERRUPT_ENABLE = (1 shl 0);
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Enable interrupts from the USB controller. Disabled by default
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| Bits [4:1] of the AHB Configuration register were redefined by Broadcom for the BCM2835
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BCM_DWC_AHB_AXI_BURST_MASK = (3 shl 1);
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Max AXI burst length
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BCM_DWC_AHB_AXI_WAIT = (1 shl 4);
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Wait for all outstanding AXI writes to complete before signalling (internally) that DMA is done
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DWC_AHB_DMA_ENABLE = (1 shl 5);
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Writing 1 to this bit in the AHB Configuration Register allows the USB controller to perform DMA (Disabled by default)
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DWC_AHB_MASTER_IDLE = (1 shl 31);
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Unknown
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[Expand]
DWC core USB configuration DWC_USB_CFG_*
| TDWCRegisters: 0x000c : Core USB Configuration Register
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DWC_USB_CFG_TOUTCAL_MASK = (7 shl 0);
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DWC_USB_CFG_TOUTCAL_LIMIT = (7 shl 0);
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DWC_USB_CFG_PHYIF16 = (1 shl 3);
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DWC_USB_CFG_ULPI_UTMI_SEL = (1 shl 4);
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DWC_USB_CFG_FS_INTF = (1 shl 5);
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DWC_USB_CFG_PHY_SEL = (1 shl 6);
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DWC_USB_CFG_DDR_SEL = (1 shl 7);
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DWC_USB_CFG_SRP_CAPABLE = (1 shl 8);
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DWC_USB_CFG_HNP_CAPABLE = (1 shl 9);
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DWC_USB_CFG_USB_TRDTIM_MASK = ($F shl 10);
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DWC_USB_CFG_RESERVED14 = (1 shl 14);
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DWC_USB_CFG_PHY_LOW_PWR_CLK_SEL = (1 shl 15);
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DWC_USB_CFG_OTG_UTMI_FS_SEL = (1 shl 16);
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DWC_USB_CFG_ULPI_FSLS = (1 shl 17);
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DWC_USB_CFG_ULPI_AUTO_RES = (1 shl 18);
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DWC_USB_CFG_ULPI_CLK_SUS_M = (1 shl 19);
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DWC_USB_CFG_ULPI_EXT_VBUS_DRV = (1 shl 20);
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DWC_USB_CFG_ULPI_INT_VBUS_INDICATOR = (1 shl 21);
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DWC_USB_CFG_TERM_SEL_DL_PULSE = (1 shl 22);
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DWC_USB_CFG_INDICATOR_COMPLEMENT = (1 shl 23);
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DWC_USB_CFG_INDICATOR_PASS_THROUGH = (1 shl 24);
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DWC_USB_CFG_ULPI_INT_PROT_DIS = (1 shl 25);
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DWC_USB_CFG_IC_USB_CAP = (1 shl 26);
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DWC_USB_CFG_IC_TRAFFIC_PULL_REMOVE = (1 shl 27);
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DWC_USB_CFG_TX_END_DELAY = (1 shl 28);
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DWC_USB_CFG_FORCE_HOST_MODE = (1 shl 29);
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DWC_USB_CFG_FORCE_DEV_MODE = (1 shl 30);
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DWC_USB_CFG_RESERVED31 = (1 shl 31);
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[Expand]
DWC core reset DWC_SOFT_RESET*
| TDWCRegisters: 0x0010 : Core Reset Register
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DWC_SOFT_RESET = (1 shl 0);
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Write 1 to this location in the Core Reset Register to start a soft reset. This bit will then be cleared by the hardware when the reset is complete.
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[Expand]
DWC core interrupt DWC_CORE_INTERRUPTS_*
| TDWCRegisters: 0x0014 : Core Interrupt Register
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DWC_CORE_INTERRUPTS_SOF_INTR = (1 shl 3);
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Bit 3 This register contains the state of pending top-level DWC interrupts. 1 means interrupt pending while 0 means no interrupt pending. Note: That at least for port_intr and host_channel_intr, software must clear the interrupt somewhere else rather than by writing to this register.
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DWC_CORE_INTERRUPTS_PORT_INTR = (1 shl 24);
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Bit 24 Host port status changed. Software must examine the Host Port Control and Status Register to determine the current status of the host port and clear any flags in it that indicate a status change.
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DWC_CORE_INTERRUPTS_HOST_CHANNEL_INTR = (1 shl 25);
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Bit 25 Channel interrupt occurred. Software must examine the Host All Channels Interrupt Register to determine which channel(s) have pending interrupts, then handle and clear the interrupts for these channels.
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DWC_CORE_INTERRUPTS_DISCONNECT = (1 shl 29);
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Bit 29 Disconnect interrupt indicated that a device has been disconnected from the root port.
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[Expand]
DWC vendor Id DWC_VENDOR_ID_*
| TDWCRegisters: 0x0040 : Vendor Id Register
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DWC_VENDOR_ID_OTG2 = $4f542000;
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DWC_VENDOR_ID_OTG3 = $4f543000;
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DWC_VENDOR_ID_MASK = $fffff000;
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[Expand]
DWC hardware configuration 2 DWC_HWCFG2_*
| TDWCRegisters: 0x0048 : Hardware Configuration 2
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DWC_HWCFG2_OP_MODE_MASK = (7 shl 0);
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DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG = (0 shl 0);
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DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG = (1 shl 0);
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DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG = (2 shl 0);
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DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE = (3 shl 0);
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DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE = (4 shl 0);
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DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST = (5 shl 0);
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DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST = (6 shl 0);
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DWC_HWCFG2_ARCHITECTURE_MASK = (3 shl 3);
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DWC_HWCFG2_ARCHITECTURE_SLAVE_ONLY = (0 shl 3);
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DWC_HWCFG2_ARCHITECTURE_EXT_DMA = (1 shl 3);
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DWC_HWCFG2_ARCHITECTURE_INT_DMA = (2 shl 3);
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DWC_HWCFG2_POINT2POINT = (1 shl 5);
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DWC_HWCFG2_HS_PHY_TYPE_MASK = (3 shl 6);
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DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED = (0 shl 6);
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DWC_HWCFG2_HS_PHY_TYPE_UTMI = (1 shl 6);
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DWC_HWCFG2_HS_PHY_TYPE_ULPI = (2 shl 6);
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DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI = (3 shl 6);
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DWC_HWCFG2_FS_PHY_TYPE_MASK = (3 shl 8);
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DWC_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED = (0 shl 8);
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DWC_HWCFG2_FS_PHY_TYPE_DEDICATED = (1 shl 8);
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DWC_HWCFG2_FS_PHY_TYPE_SHARED_UTMI = (2 shl 8);
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DWC_HWCFG2_FS_PHY_TYPE_SHARED_ULPI = (3 shl 8);
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DWC_HWCFG2_NUM_DEV_ENDPOINTS = ($F shl 10);
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DWC_HWCFG2_NUM_HOST_CHANNELS = ($F shl 14);
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DWC_HWCFG2_PERIODIC_ENDPOINT_SUPPORTED = (1 shl 18);
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DWC_HWCFG2_DYNAMIC_FIFO = (1 shl 19);
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DWC_HWCFG2_MULTI_PROC_INT = (1 shl 20);
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DWC_HWCFG2_RESERVED21 = (1 shl 21);
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DWC_HWCFG2_NON_PERIODIC_TX_QUEUE_DEPTH = (3 shl 22);
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DWC_HWCFG2_HOST_PERIODIC_TX_QUEUE_DEPTH = (3 shl 24);
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DWC_HWCFG2_DEV_TOKEN_QUEUE_DEPTH = ($1F shl 26);
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DWC_HWCFG2_OTG_ENABLE_IC_USB = (1 shl 31);
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[Expand]
DWC host configuration DWC_HCFG_*
| TDWCRegisters: 0x0400 : Host Configuration Register
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DWC_HCFG_FS_LS_PHY_CLK_SEL_MASK = (3 shl 0);
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FS/LS Phy Clock Select
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DWC_HCFG_FS_LS_PHY_CLK_SEL_SHIFT = 0;
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DWC_HCFG_FS_LS_PHY_CLK_SEL_30_60_MHZ = 0;
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DWC_HCFG_FS_LS_PHY_CLK_SEL_48_MHZ = 1;
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DWC_HCFG_FS_LS_PHY_CLK_SEL_6_MHZ = 2;
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DWC_HCFG_FS_LS_SUPPORT_ONLY = (1 shl 2);
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FS/LS Only Support
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DWC_HCFG_ENABLE_32KHZ = (1 shl 7);
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Enable 32-KHz Suspend Mode
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DWC_HCFG_RESUME_VALID_MASK = ($FF shl 8);
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Resume Validation Period
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DWC_HCFG_RESUME_VALID_SHIFT = 8;
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DWC_HCFG_DESC_DMA = (1 shl 23);
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Enable Scatter/gather DMA in Host mode
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DWC_HCFG_FRAME_LIST_ENTRIES_MASK = (3 shl 24);
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Frame List Entries
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DWC_HCFG_FRAME_LIST_ENTRIES_SHIFT = 24;
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DWC_HCFG_FRAME_LIST_ENTRIES_8 = (0 shl 24);
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DWC_HCFG_FRAME_LIST_ENTRIES_8_SIZE = 8;
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DWC_HCFG_FRAME_LIST_ENTRIES_16 = (1 shl 24);
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DWC_HCFG_FRAME_LIST_ENTRIES_16_SIZE = 16;
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DWC_HCFG_FRAME_LIST_ENTRIES_32 = (3 shl 24);
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DWC_HCFG_FRAME_LIST_ENTRIES_32_SIZE = 32;
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DWC_HCFG_FRAME_LIST_ENTRIES_64 = (3 shl 24);
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DWC_HCFG_FRAME_LIST_ENTRIES_64_SIZE = 64;
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DWC_HCFG_PERSCHED_ENA = (1 shl 26);
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Enable Periodic Scheduling
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DWC_HCFG_MODE_CH_TIM_EN = (1 shl 31);
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[Expand]
DWC host frame interval DWC_HFIR_*
| TDWCRegisters: 0x0404 : Host Frame Interval Register
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DWC_HFIR_FRAME_INTERVAL_MASK = ($FFFF shl 0);
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DWC_HFIR_FRAME_INT_RELOAD_CTL = (1 shl 16);
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DWC_HFIR_RESERVED1 = ($FFFE shl 17);
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[Expand]
DWC host frame register DWC_HFNUM_*
| TDWCRegisters: 0x0408 : Host Frame Register
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DWC_HFNUM_FRAME_NUMBER_MASK = $FFFF;
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[Expand]
DWC host port control and status DWC_HOST_PORT_CTRLSTATUS_*
| TDWCRegisters: 0x0440 : Host Port Control and Status Register
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| This register provides the information needed to respond to status queries about the "host port", which is the port that is logically attached to the root hub.
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| When changing this register, software must read its value, then clear the enabled, connected_changed, enabled_changed, and overcurrent_changed members to avoid changing them, as those particular bits are cleared by writing 1.
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DWC_HOST_PORT_CTRLSTATUS_CONNECTED = (1 shl 0);
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Bit 0 1: a device is connected to this port. 0: no device is connected to this port. Changed by hardware only.
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DWC_HOST_PORT_CTRLSTATUS_CONNECTED_CHANGED = (1 shl 1);
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Bit 1 Set by hardware when connected bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
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DWC_HOST_PORT_CTRLSTATUS_ENABLED = (1 shl 2);
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Bit 2 1: port is enabled. 0: port is disabled. Note: the host port is enabled by default after it is reset. Note: Writing 1 here appears to disable the port.
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DWC_HOST_PORT_CTRLSTATUS_ENABLED_CHANGED = (1 shl 3);
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Bit 3 Set by hardware when enabled bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
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DWC_HOST_PORT_CTRLSTATUS_OVERCURRENT = (1 shl 4);
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Bit 4 1: overcurrent condition active on this port 0: no overcurrent condition active on this port. Changed by hardware only.
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DWC_HOST_PORT_CTRLSTATUS_OVERCURRENT_CHANGED = (1 shl 5);
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Bit 5 Set by hardware when the overcurrent bit changes. The software can write 1 to acknowledge and clear. The setting of this bit by hardware generates the interrupt that can be enabled by setting port_intr in the core_interrupt_mask register.
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DWC_HOST_PORT_CTRLSTATUS_RESUME = (1 shl 6);
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Bit 6 Set by software to set resume signalling
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DWC_HOST_PORT_CTRLSTATUS_SUSPENDED = (1 shl 7);
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Bit 7 Set by software to suspend the port
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DWC_HOST_PORT_CTRLSTATUS_RESET = (1 shl 8);
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Bit 8 Software can set this to start a reset on this port. Software must clear this after waiting 60 milliseconds for the reset is complete.
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DWC_HOST_PORT_CTRLSTATUS_RESERVED = (1 shl 9);
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Bit 9
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DWC_HOST_PORT_CTRLSTATUS_LINE_STATUS = (3 shl 10);
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Bits 10-11 Current logic of data lines (10: logic of D+; 11: logic of D-). Changed by hardware only.
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DWC_HOST_PORT_CTRLSTATUS_POWERED = (1 shl 12);
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Bit 12 1: port is powered. 0: port is not powered. Software can change this bit to power on (1) or power off (0) the port.
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DWC_HOST_PORT_CTRLSTATUS_TEST_CONTROL = ($0F shl 13);
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Bits 13-16
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DWC_HOST_PORT_CTRLSTATUS_SPEED = (3 shl 17);
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Bits 17-18 Speed of attached device (if any). This should only be considered meaningful if the connected bit is set. 00: high speed; 01: full speed; 10: low speed Changed by hardware only.
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DWC_HOST_PORT_CTRLSTATUS_RESERVED2 = ($1FFF shl 19);
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Bits 19-32
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[Expand]
DWC channel characteristics DWC_HOST_CHANNEL_CHARACTERISTICS_*
| TDWCHostChannel: 0x0000 : Channel Characteristics Register
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| Contains various fields that must be set to prepare this channel for a transfer to or from a particular endpoint on a particular USB device
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| This register only needs to be programmed one time when doing a transfer, regardless of how many packets it consists of, unless the channel is re-programmed for a different transfer or the transfer is moved to a different channel.
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DWC_HOST_CHANNEL_CHARACTERISTICS_MAX_PACKET_SIZE = ($7FF shl 0);
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Bits 0-10 Maximum packet size the endpoint is capable of sending or receiving. Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_NUMBER = ($0F shl 11);
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Bits 11-14 Endpoint number (low 4 bits of bEndpointAddress). Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_DIRECTION = (1 shl 15);
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Bit 15 Endpoint direction (high bit of bEndpointAddress). Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_RESERVED = (1 shl 16);
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Bit 16
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DWC_HOST_CHANNEL_CHARACTERISTICS_LOWSPEED = (1 shl 17);
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Bit 17 1 when the device being communicated with is attached at low speed; 0 otherwise. Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_TYPE = (3 shl 18);
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Bits 18-19 Endpoint type (low 2 bits of bmAttributes). Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_PACKETS_PER_FRAME = (3 shl 20);
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Bits 20-21 Maximum number of transactions that can be executed per microframe as part of this transfer. Normally 1, but should be set to 1 + (bits 11 and 12 of wMaxPacketSize) for high-speed interrupt and isochronous endpoints. Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_DEVICE_ADDRESS = ($7F shl 22);
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Bits 22-28 USB device address of the device on which the endpoint is located. Must be programmed by software before starting the transfer.
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DWC_HOST_CHANNEL_CHARACTERISTICS_ODD_FRAME = (1 shl 29);
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Bit 29 Just before enabling the channel (for all transactions), software needs to set this to the opposite of the low bit of the host_frame_number register. Otherwise the hardware will issue frame overrun errors on some transactions.
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DWC_HOST_CHANNEL_CHARACTERISTICS_CHANNEL_DISABLE = (1 shl 30);
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Bit 30 Software can set this to 1 to halt the channel. Not needed during normal operation as the channel halts automatically when a transaction completes or an error occurs.
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DWC_HOST_CHANNEL_CHARACTERISTICS_CHANNEL_ENABLE = (1 shl 31);
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Bit 31 Software can set this to 1 to enable the channel, thereby actually starting the transaction on the USB. This must only be done after the characteristics, split_control, and transfer registers, and possibly other registers (depending on the transfer) have been programmed.
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[Expand]
DWC channel split control DWC_HOST_CHANNEL_SPLIT_CONTROL_*
| TDWCHostChannel: 0x0004 : Channel Split Control Register
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| This register is used to set up Split Transactions for communicating with low or full-speed devices attached to a high-speed hub. When doing so, set split_enable to 1 and the other fields as documented. Otherwise, software must clear this register before starting the transfer.
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| Like the Channel Characteristics register, this register only needs to be programmed one time if the channel is enabled multiple times to send all the packets of a single transfer.
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DWC_HOST_CHANNEL_SPLIT_CONTROL_PORT_ADDRESS = ($7F shl 0);
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Bits 0-6 0-based index of the port on the high-speed hub on which the low or full-speed device is attached.
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DWC_HOST_CHANNEL_SPLIT_CONTROL_HUB_ADDRESS = ($7F shl 7);
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Bits 7-13 USB device address of the high-speed hub that acts as the Transaction Translator for this low or full-speed device. This is not necessarily the hub the device is physically connected to, since that could be a full-speed or low-speed hub. Instead, software must walk up the USB device tree (towards the root hub) until a high-speed hub is found and use its device address here.
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DWC_HOST_CHANNEL_SPLIT_CONTROL_TRANSACTION_POSITION = (3 shl 14);
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Bits 14-15
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DWC_HOST_CHANNEL_SPLIT_CONTROL_COMPLETE_SPLIT = (1 shl 16);
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Bit 16 0: Do a Start Split transaction 1: Do a Complete Split transaction. When split transactions are enabled, this must be programmed by software before enabling the channel. Note that you must begin with a Start Split transaction and alternate this bit for each transaction until the transfer is complete.
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DWC_HOST_CHANNEL_SPLIT_CONTROL_RESERVED = ($3FFF shl 17);
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Bits 17-30
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DWC_HOST_CHANNEL_SPLIT_CONTROL_SPLIT_ENABLE = (1 shl 31);
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Bit 31 Set to 1 to enable Split Transactions
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[Expand]
DWC channel interrupt DWC_HOST_CHANNEL_INTERRUPTS_*
| TDWCHostChannel: 0x0008 : Channel Interrupts Register
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| Bitmask of status conditions that have occurred on this channel.
|
| These bits can be used with or without "real" interrupts. To have the CPU get a real interrupt when one of these bits gets set, set the appropriate bit in the interrupt_mask, and also ensure that interrupts from the channel are enabled in the host_channels_interrupt_mask register, channel interrupts overall are enabled in the core_interrupt_mask register, and interrupts from the DWC hardware overall are enabled in the ahb_configuration register and by any system-specific interrupt controller.
|
DWC_HOST_CHANNEL_INTERRUPTS_TRANSFER_COMPLETED = (1 shl 0);
|
Bit 0 The requested USB transfer has successfully completed
Exceptions and caveats:
- When doing split transactions, this bit will be set after a Complete Split transaction has finished, even though the overall transfer may not actually be complete.
- The transfer will only be complete up to the extent that data was programmed into the channel. For example, control transfers have 3 phases, each of which must be programmed into the channel separately. This flag will be set after each of these phases has successfully completed.
- An OUT transfer is otherwise considered complete when exactly the requested number of bytes of data have been successfully transferred, while an IN transfer is otherwise considered complete when exactly the requested number of bytes of data have been successfully transferred or a shorter-than-expected packet was received.
|
DWC_HOST_CHANNEL_INTERRUPTS_CHANNEL_HALTED = (1 shl 1);
|
Bit 1 The channel has halted. After this bit has been set, the channel sits idle and nothing else will happen until software takes action. Channels may halt for several reasons. From our experience these cover all possible situations in which software needs to take action, so this is the only channel interrupt that actually needs to be enabled. At least in DMA mode, the controller to some extent will act autonomously to complete transfers and only issue this interrupt when software needs to take action.
Situations in which a channel will halt include but probably are not limited to:
- The transfer has completed, thereby setting the transfer_completed flag as documented above.
- A Start Split or Complete Split transaction has finished.
- The hub sent a NYET packet when trying to execute a Complete Split transaction, thereby signalling that the Split transaction is not yet complete.
- The device sent a NAK packet, thereby signalling it had no data to send at the time, when trying to execute an IN interrupt transfer.
- One of several errors has occurred, such as an AHB error, data toggle error, tranasction error, stall condition, or frame overrun error.
|
DWC_HOST_CHANNEL_INTERRUPTS_AHB_ERROR = (1 shl 2);
|
Bit 2 An error occurred on the ARM Advanced High-Performance Bus (AHB)
|
DWC_HOST_CHANNEL_INTERRUPTS_STALL_RESPONSE_RECEIVED = (1 shl 3);
|
Bit 3 The device issued a STALL handshake packet (endpoint is halted or control pipe request is not supported).
|
DWC_HOST_CHANNEL_INTERRUPTS_NAK_RESPONSE_RECEIVED = (1 shl 4);
|
Bit 4 The device issued a NAK handshake packet (receiving device cannot accept data or transmitting device cannot send data). The channel will halt with this bit set when performing an IN transfer from an interrupt endpoint that has no data to send. As this requires software intervention to restart the channel, this means that polling of interrupt endpoints (e.g. on hubs and HID devices) must be done in software, even if the actual transactions themselves are interrupt-driven.
|
DWC_HOST_CHANNEL_INTERRUPTS_ACK_RESPONSE_RECEIVED = (1 shl 5);
|
Bit 5 The device issued an ACK handshake packet (receiving device acknowledged error-free packet).
|
DWC_HOST_CHANNEL_INTERRUPTS_NYET_RESPONSE_RECEIVED = (1 shl 6);
|
Bit 6 The device issued a NYET handshake packet.
|
DWC_HOST_CHANNEL_INTERRUPTS_TRANSACTION_ERROR = (1 shl 7);
|
Bit 7 From our experience this seems to usually indicate that software programmed the channel incorrectly.
|
DWC_HOST_CHANNEL_INTERRUPTS_BABBLE_ERROR = (1 shl 8);
|
Bit 8 Unexpected bus activity occurred.
|
DWC_HOST_CHANNEL_INTERRUPTS_FRAME_OVERRUN = (1 shl 9);
|
Bit 9
|
DWC_HOST_CHANNEL_INTERRUPTS_DATA_TOGGLE_ERROR = (1 shl 10);
|
Bit 10 When issuing a series of DATA transactions to an endpoint, the correct DATA0 or DATA1 packet ID was not specified in the packet_id member of the transfer register.
|
DWC_HOST_CHANNEL_INTERRUPTS_BUFFER_NOT_AVAILABLE = (1 shl 11);
|
Bit 11
|
DWC_HOST_CHANNEL_INTERRUPTS_EXCESS_TRANSACTION_ERROR = (1 shl 12);
|
Bit 12
|
DWC_HOST_CHANNEL_INTERRUPTS_FRAME_LIST_ROLLOVER = (1 shl 13);
|
Bit 13
|
DWC_HOST_CHANNEL_INTERRUPTS_RESERVED = ($3FFFF shl 14);
|
Bits 14-31
|
[Expand]
DWC channel interrupt mask DWC_HOST_CHANNEL_INTERRUPT_MASK_*
| TDWCHostChannel: 0x000c : Channel Interrupts Mask Register
|
| This has the same format as the Channel Interrupts Register, but software uses this to enable (1) or disable (0) the corresponding interrupt. Defaults to all 0's after a reset.
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_TRANSFER_COMPLETED = DWC_HOST_CHANNEL_INTERRUPTS_TRANSFER_COMPLETED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_CHANNEL_HALTED = DWC_HOST_CHANNEL_INTERRUPTS_CHANNEL_HALTED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_AHB_ERROR = DWC_HOST_CHANNEL_INTERRUPTS_AHB_ERROR;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_STALL_RESPONSE_RECEIVED = DWC_HOST_CHANNEL_INTERRUPTS_STALL_RESPONSE_RECEIVED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_NAK_RESPONSE_RECEIVED = DWC_HOST_CHANNEL_INTERRUPTS_NAK_RESPONSE_RECEIVED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_ACK_RESPONSE_RECEIVED = DWC_HOST_CHANNEL_INTERRUPTS_ACK_RESPONSE_RECEIVED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_NYET_RESPONSE_RECEIVED = DWC_HOST_CHANNEL_INTERRUPTS_NYET_RESPONSE_RECEIVED;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_TRANSACTION_ERROR = DWC_HOST_CHANNEL_INTERRUPTS_TRANSACTION_ERROR;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_BABBLE_ERROR = DWC_HOST_CHANNEL_INTERRUPTS_BABBLE_ERROR;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_FRAME_OVERRUN = DWC_HOST_CHANNEL_INTERRUPTS_FRAME_OVERRUN;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_DATA_TOGGLE_ERROR = DWC_HOST_CHANNEL_INTERRUPTS_DATA_TOGGLE_ERROR;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_BUFFER_NOT_AVAILABLE = DWC_HOST_CHANNEL_INTERRUPTS_BUFFER_NOT_AVAILABLE;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_EXCESS_TRANSACTION_ERROR = DWC_HOST_CHANNEL_INTERRUPTS_EXCESS_TRANSACTION_ERROR;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_FRAME_LIST_ROLLOVER = DWC_HOST_CHANNEL_INTERRUPTS_FRAME_LIST_ROLLOVER;
|
|
DWC_HOST_CHANNEL_INTERRUPT_MASK_RESERVED = DWC_HOST_CHANNEL_INTERRUPTS_RESERVED;
|
|
[Expand]
DWC channel transfer DWC_HOST_CHANNEL_TRANSFER_*
| TDWCHostChannel: 0x0010 : Channel Transfer Register
|
| Used to store additional information about the transfer. This must be programmed before beginning the transfer.
|
DWC_HOST_CHANNEL_TRANSFER_SIZE = ($7FFFF shl 0);
|
Bits 0-18 Size of the data to send or receive, in bytes. Software must program this before beginning the transfer. This can be greater than the maximum packet length. For IN transfers, the hardware decrements this field for each packet received by the number of bytes received. For split transactions, the decrement happens after the Complete Split rather than the Start Split. Software can subtract this field from the original transfer size in order to determine the number of bytes received at any given point, including when the transfer has encountered an error or has completed with either the full size or a short size. For OUT transfers, the hardware does not update this field as expected. It will not be decremented when data is transmitted, at least not in every case; hence, software cannot rely on its value to indicate how many bytes of data have been transmitted so far. Instead, software must inspect the packet_count field and assume that all data was transmitted if packet_count is 0, or that the amount of data transmitted is equal to the endpoint's maximum packet size times (the original packet count minus packet_count) if packet_count is nonzero.
|
DWC_HOST_CHANNEL_TRANSFER_PACKET_COUNT = ($3FF shl 19);
|
Bits 19-28 Number of packets left to transmit or maximum number of packets left to receive. Software must program this before beginning the transfer. The packet count is calculated as the size divided by the maximum packet size, rounded up to the nearest whole packet. As a special case, if the transfer size is 0 bytes, the packet count must be set to 1. The hardware will decrement this register when a packet is successfully sent or received. In the case of split transactions, this happens after the Complete Split rather than after the Start Split. If the final received packet of an IN transfer is short, it is still counted.
|
DWC_HOST_CHANNEL_TRANSFER_PACKET_ID = ($03 shl 29);
|
Bits 29-30 High 2 bits of the Packet ID used in the USB protocol. When performing the SETUP phase of a control transfer, specify 0x3 here to generate the needed SETUP token. When performing the DATA phase of a control transfer, initially specify 0x2 here to begin the DATA packets with the needed DATA1 Packet ID. When performing the STATUS phase of a control transfer, specify 0x2 here to generate the need DATA1 Packet ID. When starting a bulk, isochronous, or interrupt transfer, specify 0x0 here to generate the needed DATA0 Packet ID. In the case of a transfer consisting of multiple DATA packets, the hardware will update this field with the Packet ID to use for the next packet. This field therefore only needs to be re-programmed if the transfer is moved to a different channel or the channel is re-used before the transfer is complete. When doing so, software must save this field so that it can be re-programmed correctly.
|
DWC_HOST_CHANNEL_TRANSFER_DO_PING = (1 shl 31);
|
Bit 31 Do PING protocol when 1 (See Section 8.5.1 of Universal Serial Bus Specification 2.0)
|
Type definitions
DWC host channel
[Expand]
PDWCHostChannel = ^TDWCHostChannel;
TDWCHostChannel = record
| Note: TDWCRegisters: 0x0500 : Array of host channels. Each host channel can be used to execute an independent USB transfer or transaction simultaneously. A USB transfer may consist of multiple transactions, or packets. To avoid having to re-program the channel, it may be useful to use one channel for all transactions of a transfer before allowing other transfers to be scheduled on it.
|
Characteristics:LongWord;
|
(0x0000 : Channel Characteristics) Contains various fields that must be set to prepare this channel for a transfer to or from a particular endpoint on a particular USB device. This register only needs to be programmed one time when doing a transfer, regardless of how many packets it consists of, unless the channel is re-programmed for a different transfer or the transfer is moved to a different channel.
|
SplitControl:LongWord;
|
(0x0004 : Channel Split Control) This register is used to set up Split Transactions for communicating with low or full-speed devices attached to a high-speed hub. When doing so, set split_enable to 1 and the other fields as documented. Otherwise, software must clear this register before starting the transfer. Like the Channel Characteristics register, this register only needs to be programmed one time if the channel is enabled multiple times to send all the packets of a single transfer.
|
Interrupts:LongWord;
|
(0x0008 : Channel Interrupts) Bitmask of status conditions that have occurred on this channel. These bits can be used with or without "real" interrupts. To have the CPU get a real interrupt when one of these bits gets set, set the appropriate bit in the interrupt_mask, and also ensure that interrupts from the channel are enabled in the host_channels_interrupt_mask register, channel interrupts overall are enabled in the core_interrupt_mask register, and interrupts from the DWC hardware overall are enabled in the ahb_configuration register and by any system-specific interrupt controller.
|
InterruptMask:LongWord;
|
(0x000c : Channel Interrupts Mask) This has the same format as the Channel Interrupts Register, but software uses this to enable (1) or disable (0) the corresponding interrupt. Defaults to all 0's after a reset.
|
Transfer:LongWord;
|
(0x0010 : Channel Transfer) Used to store additional information about the transfer. This must be programmed before beginning the transfer.
|
DMAAddress:LongWord;
|
(0x0014 : Channel DMA Address) Word-aligned address at which the hardware will read or write data using Direct Memory Access. This must be programmed before beginning the transfer, unless the size of the data to send or receive is 0. The hardware will increment this address by the number of bytes successfully received or sent, which will correspond to the size decrease in transfer.size. Note: DMA must be enabled in the AHB Configuration Register before this register can be used. Otherwise, the hardware is considered to be in Slave mode and must be controlled a different way, which we do not use in our driver and do not attempt to document. BCM2835-specific note: Addresses written to this register must be bus addresses, not ARM physical addresses.
|
Reserved0x0018:LongWord;
|
(0x0018 : Reserved)
|
Reserved0x001C:LongWord;
|
(0x001C : Reserved)
|
DWC registers
[Expand]
PDWCRegisters = ^TDWCRegisters;
TDWCRegisters = record
| Note: Layout of the registers of the DesignWare Hi-Speed USB 2.0 On-The-Go Controller. There is no official documentation for these, however, the register locations (and to some extent the meanings) can be found in other code, such as the Linux driver for this hardware that Synopsys contributed.
We do not explicitly define every bit in the registers because the majority are not used by our driver and would complicate this file. For example, we do not attempt to document any features that are specific to suspend, hibernation, the OTG protocol, or to the core acting in device mode rather than host mode.
The bits and fields we do use in our driver we have tried to completely document based on our understanding of what they do. We cannot guarantee that all the information is correct, as we do not have access to any official documentation.
|
| Core registers
|
OTGControl:LongWord;
|
(0x0000 : OTG Control and Status)
|
OTGInterrupt:LongWord;
|
(0x0004 : OTG Interrupt)
|
AHBConfiguration:LongWord;
|
(0x0008 : Core AHB Configuration) This register configures some of the interactions the DWC has with the rest of the system.
|
CoreUSBConfiguration:LongWord;
|
(0x000c : Core USB Configuration)
|
CoreReset:LongWord;
|
(0x0010 : Core Reset) Software can use this register to cause the DWC to reset itself.
|
CoreInterrupts:LongWord;
|
(0x0014 : Core Interrupt) This register contains the state of pending top-level DWC interrupts. 1 means interrupt pending while 0 means no interrupt pending. Note that at least for port_intr and host_channel_intr, software must clear the interrupt somewhere else rather than by writing to this register.
|
CoreInterruptMask:LongWord;
|
(0x0018 : Core Interrupt Mask) This register has the same format as the Core Interrupt Register and configures whether the corresponding interrupt is enabled (1) or disabled (0). Initial state after reset is all 0's.
|
ReceiveStatus:LongWord;
|
(0x001c : Receive Status Queue Read (Read Only))
|
ReceiveStatusPop:LongWord;
|
(0x0020 : Receive Status Queue Read & POP (Read Only))
|
ReceiveFIFOSize:LongWord;
|
(0x0024 : Receive FIFO Size) This register contains the size of the Receive FIFO, in 4-byte words. This register must be set by software before using the controller (see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs).
|
NonPeriodicTransmitFIFOSize:LongWord;
|
(0x0028 : Non Periodic Transmit FIFO Size) The low 16 bits of this register contain the offset of the Nonperiodic Transmit FIFO, in 4-byte words, from the start of the memory reserved by the controller for dynamic FIFOs. The high 16 bits of this register contain its size, in 4-byte words. This register must be set by software before using the controller (see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs).
|
NonPeriodicTransmitFIFOStatus:LongWord;
|
(0x002c : Non Periodic Transmit FIFO/Queue Status (Read Only))
|
I2CControl:LongWord;
|
(0x0030 : I2C Access)
|
PHYVendorControl:LongWord;
|
(0x0034 : PHY Vendor Control)
|
GPIO:LongWord;
|
(0x0038 : General Purpose Input/Output)
|
UserId:LongWord;
|
(0x003c : User ID)
|
VendorId:LongWord;
|
(0x0040 : Vendor ID (Read Only))
|
HWCfg1:LongWord;
|
(0x0044 : User HW Config1 (Read Only))
|
HWCfg2:LongWord;
|
(0x0048 : User HW Config2 (Read Only))
|
HWCfg3:LongWord;
|
(0x004c : User HW Config3 (Read Only)) The high 16 bits of this read-only register contain the maximum total size, in words, of the dynamic FIFOs (Rx, Nonperiodic Tx, and Periodic Tx). Software must set up these three dynamic FIFOs in the rx_fifo_size, nonperiodic_tx_fifo_size, and host_periodic_tx_fifo_size registers such that their total size does not exceed this maximum total size and no FIFOs overlap. Note: Software must explicitly configure the dynamic FIFOs even if the controller is operating in DMA mode, since the default values for the FIFO sizes and offsets may be invalid. For example, in Broadcom's instantiation of this controller for the BCM2835, only 4080 words are available for dynamic FIFOs, but the dynamic FIFO sizes are set to 4096, 32, and 0, which are invalid as they add up to more than 4080. IF YOU DO NOT DO THIS YOU WILL GET SILENT MEMORY CORRUPTION. The low 16 bits of this register contain various flags that are not documented here as we don't use any in our driver.
|
HWCfg4:LongWord;
|
(0x0050 : User HW Config4 (Read Only))
|
CoreLPMConfiguration:LongWord;
|
(0x0054 : Core LPM Configuration)
|
GlobalPowerDown:LongWord;
|
(0x0058 : Global PowerDown)
|
GlobalFIFOConfig:LongWord;
|
(0x005c : Global DFIFO SW Config)
|
ADPControl:LongWord;
|
(0x0060 : ADP Control (Attach Detection Protocol))
|
Reserved0x0064:array[1..39] of LongWord;
|
(0x0064 : Reserved)
|
HostPeriodicTransmitFIFOSize:LongWord;
|
(0x0100 : Host Periodic Transmit FIFO Size) The low 16 bits of this register configure the offset of the Periodic Transmit FIFO, in 4-byte words, from the start of the memory reserved by the controller for dynamic FIFOs. The high 16 bits of this register configure its size, in 4-byte words. This register should be set by software before using the controller (see the note in the documentation for the hwcfg3 register about configuring the dynamic FIFOs).
|
Reserved0x0104:array[1..191] of LongWord;
|
(0x0104 : Device Periodic Transmit FIFO#n) If dedicated fifos are disabled, otherwise Device Transmit FIFO#n.
|
| Host registers
|
| Note: The registers beginning at this point are considered to be the "Host" registers. These are used for the "Host" half of the OTG (On-The-Go) protocol, which allows this hardware to act as either a USB host or a USB device. This is the only half we are concerned with in this driver and we do not declare the corresponding Device registers.
|
HostConfiguration:LongWord;
|
(0x0400 : Host Configuration)
|
HostFrameInterval:LongWord;
|
(0x0404 : Host Frame Interval)
|
HostFrameNumber:LongWord;
|
(0x0408 : Host Frame Number/Frame Remaining)
|
Reserved0x040c:LongWord;
|
(0x040c : Reserved)
|
HostFIFOStatus:LongWord;
|
(0x0410 : Host Periodic Transmit FIFO/Queue Status)
|
HostChannelsInterrupt:LongWord;
|
(0x0414 : Host All Channels Interrupt) This register contains a bit for each host channel that indicates whether an interrupt has occurred on that host channel. You cannot clear the interrupts by writing to this register, use the channel-specific interrupt registers instead.
|
HostChannelsInterruptMask:LongWord;
|
(0x0418 : Host All Channels Interrupt Mask) Same format as the Host All Channels Interrupt Register, but a 1 in this register indicates that the corresponding host channel interrupt is enabled. Software can change this register. Defaults to all 0's after a reset.
|
HostFrameList:LongWord;
|
(0x041c : Host Frame List Base Address Register)
|
Reserved0x0420:array[1..8] of LongWord;
|
(0x0420)
|
HostPortControlStatus:LongWord;
|
(0x0440 : Host Port Control and Status) This register provides the information needed to respond to status queries about the "host port", which is the port that is logically attached to the root hub. When changing this register, software must read its value, then clear the enabled, connected_changed, enabled_changed, and overcurrent_changed members to avoid changing them, as those particular bits are cleared by writing 1.
|
Reserved0x0444:array[1..47] of LongWord;
|
(0x0444)
|
| Host channel registers
|
HostChannels:array[0..DWC_MAX_CHANNELS - 1] of TDWCHostChannel;
|
(0x0500 : Array of Host Channels) Each host channel can be used to execute an independent USB transfer or transaction simultaneously. A USB transfer may consist of multiple transactions, or packets. To avoid having to re-program the channel, it may be useful to use one channel for all transactions of a transfer before allowing other transfers to be scheduled on it.
|
Reserved0x0700:array[1..((($800 - $500) - (DWC_MAX_CHANNELS * SizeOf(TDWCHostChannel))) div SizeOf(LongWord))] of LongWord;
|
(0x0700)
|
| Device registers
|
Reserved0x0800:array[1..(($E00 - $800) div SizeOf(LongWord))] of LongWord;
|
(0x0800)
|
PowerClockControl:LongWord;
|
(0x0e00 : Power and Clock Gating Control)
|
DWC root hub configuration
[Expand]
PDWCRootHubConfiguration = ^TDWCRootHubConfiguration;
TDWCRootHubConfiguration = packed record
ConfigurationDescriptor:TUSBConfigurationDescriptor;
|
|
InterfaceDescriptor:TUSBInterfaceDescriptor;
|
|
EndpointDescriptor:TUSBEndpointDescriptor;
|
|
DWC USB transfer
[Expand]
PDWCUSBTransfer = ^TDWCUSBTransfer;
TDWCUSBTransfer = record
DWC USB host
[Expand]
PDWCUSBHost = ^TDWCUSBHost;
TDWCUSBHost = record
| USB Properties
|
Host:TUSBHost;
|
|
| DWCOTG Properties
|
Lock:TSpinHandle;
|
Host lock (Differs from lock in Host portion) (Spin lock due to use by interrupt handler)
|
IRQ:LongWord;
|
The IRQ assigned to this host
|
PowerID:LongWord;
|
The Power ID required to power on this host
|
Registers:PDWCRegisters;
|
Memory mapped registers of the Synopsys DesignWare Hi-Speed USB 2.0 OTG Controller
|
ChannelCount:LongWord;
|
The number of channels available on this host
|
SchedulerThread:TThreadHandle;
|
Thread ID of USB request scheduler thread
|
CompletionThread:TThreadHandle;
|
Thread ID of USB request completion thread
|
SchedulerMailslot:TMailslotHandle;
|
USB requests that have been submitted to the Host but not yet started on a channel
|
| Channel Properties
|
DMABuffers:array[0..DWC_MAX_CHANNELS - 1] of Pointer;
|
DMA buffers allocated for each hardware channel (4 byte aligned / 1 per channel)
|
ChannelRequests:array[0..DWC_MAX_CHANNELS - 1] of PUSBRequest;
|
Current USB request pending on each hardware channel (or nil of no request is pending)
|
ChannelFreeMask:LongWord;
|
Bitmap of channel free (1) or used (0) status
|
ChannelFreeLock:TMutexHandle;
|
Lock for access to ChannelFreeMask
|
ChannelFreeWait:TSemaphoreHandle;
|
Number of free channels in ChannelFreeMask
|
StartOfFrameMask:LongWord;
|
Bitmap of channels waiting for Start of Frame
|
StartOfFrameLock:TSpinHandle;
|
Lock for access to StartOfFrameMask (Spin lock due to use by interrupt handler)
|
LastFrameNumber:LongWord;
|
Frame Number at the last Start Of Frame interrupt
|
| Root Hub Properties
|
HubStatus:PUSBHubStatus;
|
Hub status for the root hub
|
PortStatus:PUSBPortStatus;
|
Host port status for the root hub (Obtained from port interrupt due to status change)
|
DeviceStatus:PUSBDeviceStatus;
|
Device status for the root hub
|
HubDescriptor:PUSBHubDescriptor;
|
Hub descriptor for the root hub
|
DeviceDescriptor:PUSBDeviceDescriptor;
|
Device descriptor for the root hub
|
HubConfiguration:PDWCRootHubConfiguration;
|
Configuration, Interface and Endpoint descriptors for the root hub
|
HubStringTable:array[0..2] of PUSBStringDescriptor;
|
String table for Language, Product and Manufacturer strings for the root hub
|
HubProductString:PUSBStringDescriptor;
|
Product identifier string for the root hub
|
HubLanguageString:PUSBStringDescriptor;
|
Language identifier string for the root hub
|
HubManufacturerString:PUSBStringDescriptor;
|
Manufacturer identifier string for the root hub
|
HubStatusChange:PUSBRequest;
|
Status change request to the root hub interrupt endpoint (nil if no request is pending)
|
| Statistics Properties
|
InterruptCount:LongWord;
|
Number of interrupt requests received by the host controller
|
PortInterruptCount:LongWord;
|
Number of port interrupts received by the host controller
|
ChannelInterruptCount:LongWord;
|
Number of channel interrupts received by the host controller
|
StartOfFrameInterruptCount:LongWord;
|
Number of start of frame interrupts received by the host controller
|
DisconnectInterruptCount:LongWord;
|
Number of disconnect interrupts received by the host controller
|
ResubmitCount:LongWord;
|
Number of requests resubmitted for later retry
|
StartOfFrameCount:LongWord;
|
Number of requests queued to wait for start of frame
|
DMABufferReadCount:LongWord;
|
Number of IN requests that required a DMA buffer copy
|
DMABufferWriteCount:LongWord;
|
Number of OUT requests that required a DMA buffer copy
|
|
|
NAKResponseCount:LongWord;
|
Number of NAK responses received by the host controller
|
NYETResponseCount:LongWord;
|
Number of NYET responses received by the host controller
|
StallResponseCount:LongWord;
|
Number of Stall responses received by the host controller
|
RequestCancelCount:LongWord;
|
Number of requests Cancelled by the host controller
|
|
|
AHBErrorCount:LongWord;
|
Number of AHB errors received by the host controller
|
TransactionErrorCount:LongWord;
|
Number of transaction errors received by the host controller
|
BabbleErrorCount:LongWord;
|
Number of babble errors received by the host controller
|
ExcessTransactionCount:LongWord;
|
Number of excess transaction errors received by the host controller
|
FrameListRolloverCount:LongWord;
|
Number of frame list rollover errors received by the host controller
|
DataToggleErrorCount:LongWord;
|
Number of data toggle errors received by the host controller
|
FrameOverrunCount:LongWord;
|
Number of frame overrun errors received by the host controller
|
|
|
ShortAttemptCount:LongWord;
|
Number of short attempts where transfer size was less than the request size
|
StartSplitCount:LongWord;
|
Number of start split transactions
|
CompleteSplitCount:LongWord;
|
Number of complete split transactions
|
CompleteSplitRestartCount:LongWord;
|
Number of times a complete split transaction has been restarted at start split due to errors
|
|
|
TransferRestartCount:LongWord;
|
Number of times a transfer is restarted to continue or retry the transfer
|
TransactionRestartCount:LongWord;
|
Number of times a transaction is restarted to continue or complete the transfer
|
|
|
NoChannelCompletedCount:LongWord;
|
Number of times the channel completed interrupt bit was not set when a request completed
|
NoPacketsTransferredCount:LongWord;
|
Number of times no packets were transferred but no error occured when a channel halted
|
Public variables
None defined
Function declarations
Initialization functions
[Expand]
procedure DWCInit;
Description: To be documented
DWCOTG functions
[Expand]
function DWCHostCreate(Address:PtrUInt; IRQ,PowerID:LongWord):PUSBHost;
Description: Create and register a new DWCOTG host which can be accessed using the USB API
| Address
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The address of the DWCOTG registers
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| IRQ
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The interrupt number for the DWCOTG host
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| PowerID
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The power ID value to power on the host using PowerOn (or POWER_ID_UNKNOWN if not applicable)
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| Return
|
Pointer to the new USB host or nil if the USB host could not be created
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function DWCHostDestroy(Host:PUSBHost):LongWord;
Description: Stop, deregister and destroy a DWCOTG USB host created by this driver
| Host
|
The USB host to destroy
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure
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DWCOTG USB functions
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function DWCHostStart(Host:PUSBHost):LongWord;
Description: Implementation of USBHostStart for the DesignWare Hi-Speed USB 2.0 On-The-Go Controller
| Note
|
See usb.pas for the documentation of this interface of the Host Controller Driver
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function DWCHostStop(Host:PUSBHost):LongWord;
Description: Implementation of USBHostStop for the DesignWare Hi-Speed USB 2.0 On-The-Go Controller
| Note
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See usb.pas for the documentation of this interface of the Host Controller Driver
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function DWCHostReset(Host:PUSBHost):LongWord;
Description: Performs a software reset of the DWC OTG Controller
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function DWCHostResetEx(Host:PDWCUSBHost):LongWord;
Description: Performs a software reset of the DWC OTG Controller
| Note
|
Caller must hold the Host lock
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function DWCHostSubmit(Host:PUSBHost; Request:PUSBRequest):LongWord;
Description: Implementation of USBHostSubmit for the DesignWare Hi-Speed USB 2.0 On-The-Go Controller
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
|
| Note
|
See usb.pas for the documentation of this interface of the Host Controller Driver
This Host Controller Driver implements this interface asynchronously, as intended. Furthermore, it uses a simplistic scheduling algorithm where it places requests into a single queue and executes them in the order they were submitted. Transfers that need to be retried, including periodic transfers that receive a NAK reply and split transactions that receive a NYET reply when doing the Complete Split transaction, are scheduled to be retried at an appropriate time by separate code that shortcuts the main queue when the timer expires.
Caller must hold the device lock.
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function DWCHostCancel(Host:PUSBHost; Request:PUSBRequest):LongWord;
Description: Implementation of USBHostCancel for the DesignWare Hi-Speed USB 2.0 On-The-Go Controller
| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
|
| Note
|
See usb.pas for the documentation of this interface of the Host Controller Driver
Caller must hold the device lock
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function DWCHostResubmit(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
Description: Called when a USB transfer needs to be retried at a later time due to no data being available from the endpoint
| Request
|
USB transfer to resubmit
|
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
|
| Note
|
For periodic transfers (e.g. polling an interrupt endpoint), the exact time at which the transfer must be retried is specified by the bInterval member of the endpoint descriptor. For low and full-speed devices, bInterval specifies the number of millisconds to wait before the next poll, while for high-speed devices it specifies the exponent (plus one) of a power-of-two number of milliseconds to wait before the next poll.
To actually implement delaying a transfer, we associate each transfer with a thread created on-demand. Each such thread simply enters a loop where it calls sleep() for the appropriate number of milliseconds, then retries the transfer. A semaphore is needed to make the thread do nothing until the request has actually been resubmitted.
This code gets used to schedule polling of IN interrupt endpoints, including those on hubs and HID devices. Thus, polling of these devices for status changes (in the case of hubs) or new input (in the case of HID devices) is done in software. This wakes up the CPU a lot and wastes time and energy. But with USB 2.0, there is no way around this, other than by suspending the USB device which we don't support.
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function DWCHostPowerOn(Host:PDWCUSBHost):LongWord;
Description: Power on the DWCOTG Host controller
| Host
|
The DWCOTG host to power on
|
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
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function DWCHostPowerOff(Host:PDWCUSBHost):LongWord;
Description: Powers off the DWCOTG Host controller
| Host
|
The DWCOTG host to power off
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| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
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function DWCHostCheck(Host:PDWCUSBHost):LongWord;
Description: Check the DWC OTG USB Host Controller to confirm it is valid
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
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function DWCHostInit(Host:PDWCUSBHost):LongWord;
Description: Initialize the DWC OTG USB Host Controller with core USB settings and perform a host reset
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
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function DWCHostSetup(Host:PDWCUSBHost):LongWord;
Description: Configure the DWC OTG USB Host Controller with....
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function DWCHostStartFrameInterrupt(Host:PDWCUSBHost; Enable:Boolean):LongWord;
Description: To be documented
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function DWCAllocateChannel(Host:PDWCUSBHost):LongWord;
Description: Get the next available host channel on the supplied DWC host
| Host
|
The DWC host to get available channel from
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| Return
|
Channel number of the next available channel
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function DWCReleaseChannel(Host:PDWCUSBHost; Channel:LongWord):LongWord;
Description: Mark the specified host channel on the supplied DWC host as available
| Host
|
The DWC host to mark available channel on
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| Channel
|
The channel number to mark as available
|
| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
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function DWCChannelStartTransfer(Host:PDWCUSBHost; Channel:LongWord; Request:PUSBRequest):LongWord;
Description: Start or restart a USB request on a channel of the supplied DWC host
| Host
|
The DWC host to start the request on
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| Channel
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The channel number to start the request on
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| Request
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USB request to start
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| Note
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Caller must hold the host lock
Can be called by the interrupt handler
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function DWCChannelStartTransaction(Host:PDWCUSBHost; Channel:LongWord; Request:PUSBRequest):LongWord;
Description: Start a USB transaction on a channel of the supplied DWC host
| Host
|
The DWC host to start the transaction on
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| Channel
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The host channel number to start the transaction on
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| Request
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USB request set up for the next transaction
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| Note
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Caller must hold the host lock
Can be called by the interrupt handler
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function DWCHostPortReset(Host:PDWCUSBHost):LongWord;
Description: Resets the DWC host port (The USB port that is attached to the root hub)
| Note
|
Caller must hold the Host lock
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function DWCHostPortPowerOn(Host:PDWCUSBHost):LongWord;
Description: Powers on the DWC host port (The USB port that is attached to the root hub)
| Note
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Caller must hold the Host lock
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function DWCHostPortGetStatus(Host:PDWCUSBHost):LongWord;
Description: Read the Host Port Control and Status register with the intention of modifying it. Due to the inconsistent design of the bits in this register, this requires zeroing the write-clear bits so they aren't unintentionally cleared by writing back 1's to them.
| Note
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Caller must hold the Host lock
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function DWCHostPortSetFeature(Host:PDWCUSBHost; Feature:Word):LongWord;
Description: Handle a SetPortFeature request on the port attached to the root hub
| Note
|
Caller must hold the Host lock
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function DWCHostPortClearFeature(Host:PDWCUSBHost; Feature:Word):LongWord;
Description: Handle a ClearPortFeature request on the port attached to the root hub
| Note
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Caller must hold the Host lock
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procedure DWCHostPortStatusChanged(Host:PDWCUSBHost);
Description: Complete any outstanding IN interrupt status change request
| Host
|
The DWCOTG host for the change request
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| Note
|
Caller must hold the Host lock
Can be called by the interrupt handler
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function DWCRootHubRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
Description: Perform a request to the root hub
| Host
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The DWCOTG host for the request
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| Request
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The USB request to perform
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| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
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| Note
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Caller must hold the Host lock
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function DWCRootHubControlRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
Description: Perform a control request to or from the root hub
| Host
|
The DWCOTG host for the request
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| Request
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The USB request to perform
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| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
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| Note
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Caller must hold the Host lock
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function DWCRootHubClassRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
Description: Perform a hub specific control request to the root hub
| Host
|
The DWCOTG host for the request
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| Request
|
Hub specific request to the root hub
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| Return
|
USB_STATUS_SUCCESS if completed or another error code on failure
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| Note
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Caller must hold the Host lock
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function DWCRootHubStandardRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
Description: Perform a standard (non hub specific) control request to the root hub
| Host
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The DWCOTG host for the request
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| Request
|
Standard request to the root hub
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| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
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| Note
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Caller must hold the Host lock
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function DWCSchedulerStart(Host:PDWCUSBHost):LongWord;
Description: Initialize a bitmask and semaphore that keep track of the Free/Used status of the host channels and a queue in which to place submitted USB transfer requests, then start the USB request scheduler thread
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function DWCSchedulerExecute(Host:PDWCUSBHost):PtrInt;
Description: USB request scheduler thread
| Host
|
USB host to service submitted requests for
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| Note
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This thread receives requests that have been submitted and schedules them on the next available channel.
This is a very simplistic scheduler that does not take into account bandwidth requirements or which endpoint a transfer is for.
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function DWCCompletionExecute(Host:PDWCUSBHost):PtrInt;
Description: USB request completion thread
| Host
|
USB host to service completed requests for
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| Note
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This thread receives completed requests which have either succeeded or failed and calls the completion handler which will call the registered callback for the request.
This thread also receives requests that need to be resubmitted and resubmits them for later processing by another thread.
Message contents are as follows:
Msg = Request to be completed
wParam = Channel that the request executed on (or INVALID_HANDLE_VALUE if no channel was allocated)
lParam = Status of the channel interrupt
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function DWCResubmitExecute(Request:PUSBRequest):PtrInt;
Description: USB request resubmit thread
| Request
|
USB request to resubmit
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| Note
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An instance of this thread is created for each request that needs to be resubmitted, this thread then either waits for a predetermined number of milliseconds before scheduling the request on the next available channel.
Once the request has been resubmitted the thread waits for the semaphore to be signaled again. If the request is a periodic polling of an endpoint then it will be resubmitted continuously at the predetermined interval, otherwise the semaphore will be destroyed by the completion handler and the thread will terminate.
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procedure DWCInterruptHandler(Host:PDWCUSBHost);
Description: Interrupt handler for the DWCOTG controller
| Host
|
The DWC host where the interrupt occurred
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function DWCChannelInterrupt(Host:PDWCUSBHost; Channel:LongWord):LongWord;
Description: Handle a channel interrupt on the specified channel
| Host
|
The DWC host where the interrupt occurred
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| Channel
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DWC host channel where the channel interrupt occurred
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| Return
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USB_STATUS_SUCCESS if completed or another error code on failure
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| Note
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Only called by DWCInterruptHandler
Caller must hold the host lock
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function DWCChannelCompleted(Host:PDWCUSBHost; Request:PUSBRequest; Channel,Interrupts:LongWord):LongWord;
Description: Handle a channel interrupt where no error occurred
| Request
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The USB request currently scheduled on this channel
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| Host
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The DWC host where the interrupt occurred
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| Channel
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DWC host channel where the channel interrupt occurred
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| Interrupts
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The currently pending interrupts on this channel
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| Note
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Only called by DWCChannelInterrupt
Caller must hold the host lock
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DWCOTG helper functions
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function DWCDivRoundUp(Number,Denominator:LongWord):LongWord;
Description: To be documented
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function DWCCalculateFrameInterval(Host:PDWCUSBHost):LongWord;
Description: Calculate the frame interval register value based on USB configuration and port speed
| Host
|
The DWCOTG host to calculate the interval for
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| Note
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The host frame interval register can only be modified when the port enabled bit is set in the host port control and status register
Caller must hold the Host lock
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