Difference between revisions of "Unit PlatformARMv6"

Note that this is also available in the FPC RTL as ReadBarrier/WriteBarrier See: \source\rtl\arm\arm.inc
Implementation is exactly the same for either.

See page 3-79 of the ARM1176JZF-S Technical Reference Manual

(See: ARMv6ThreadSetupStack for additional information)

(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-

d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-

fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)

This form of context switch uses r12 to save the cpsr value (and RFE to restore it). Because this context switch is called from a routine which will have saved the value of r12 (which is caller save in the ARM ABI) then we do not need to save the original value of r12.

The context switch will be performed from SYS mode to SYS mode, the cpsr value will include the control bits (Mode and IRQ/FIQ state) but not the flags values. Again the ARM ABI does not require that the flags be saved by the callee and so the caller would have accounted for any needed flags before calling. If the thread to be resumed was interrupted by an IRQ or FIQ then the cpsr will also contain the flags etc as they were at the point of interrupt. We do not need to account for the state bits in the cpsr since all operations are performed in ARM mode at present.

The main requirement of this routine is to ensure that the context record on the stack matches exactly that which is created on an interrupt and also that created by ThreadSetupStack for a new thread. If this is correct then the next context switch for any given thread can be either by a call to reschedule or by an interrupt. Equally a new thread can be first run from a context switch that resulted from either a call to reschedule or an interrupt.

Note that this routine could use:

pop (lr)
pop (r12)
msr cpsr_c, r12
mov pc, lr

To return but that would mess up the value of r12, lr and the cpsr flags etc if the thread being resumed was interrupted by an IRQ, FIQ or SWI. The use of RFE here allows for exactly the same behaviour no matter which way the context record is saved and restored.

(See: ARMv6ThreadSetupStack for additional information)

(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-

d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-

fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)

This form of context switch relies on the IRQ handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous IRQ or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.

The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to IRQ mode.

(See: ARMv6ThreadSetupStack for additional information)

(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-

d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-

fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)

This form of context switch relies on the FIQ handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous FIQ or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.

The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to FIQ mode.

(See: ARMv6ThreadSetupStack for additional information)

(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-

d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-

fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)

This form of context switch relies on the SWI handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous SWI or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.

The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to SWI (SVC) mode.