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Description
ARM PrimeCell PL180/181 Multimedia Card Interface Driver unit
The PL180/181 Multimedia Card is an ARM peripheral that is compatible with MMC multimedia cards and SD secure digital cards in memory mapped I/O format compatible with the ARM advanced peripheral bus (APB).
The design of the Pl180/181 allows for multiple cards per controller however this driver currently only supports attaching one card.
Constants
To be documented
Type definitions
PL18X version Id
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PPL18XVersionID = ^TPL18XVersionID;
TPL18XVersionID = record
PeripheralID:LongWord;
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PeripheralMask:LongWord;
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VersionData:PPL18XVersionData;
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PL18X version data
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PPL18XVersionData = ^TPL18XVersionData;
TPL18XVersionData = record
Name:String;
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Name of the device
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ClockRegister:LongWord;
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Default value for MCICLOCK register
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ClockEnable:LongWord;
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Enable value for MMCICLOCK register
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Clock8BitEnable:LongWord;
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Enable value for 8 bit bus
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ClockNegativeEdgeEnable:LongWord;
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Enable value for inverted data/cmd output
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DataLengthBits:LongWord;
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Number of bits in the MMCIDATALENGTH register
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FIFOSize:LongWord;
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Number of bytes that can be written when MMCI_TXFIFOEMPTY is asserted (likewise for RX)
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FIFOHalfSize:LongWord;
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Number of bytes that can be written when MCI_TXFIFOHALFEMPTY is asserted (likewise for RX)
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DataCommandEnable:LongWord;
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Enable value for data commands
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DataControlMaskDDR:LongWord;
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DDR mode mask in MMCIDATACTRL register
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DataControlMaskSDIO:LongWord;
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SDIO enable mask in MMCIDATACTRL register
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STSDIO:LongBool;
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Enable ST specific SDIO logic
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STClockDivider:LongBool;
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True if using a ST-specific clock divider algorithm
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BlockSizeDataControl16:LongBool;
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True if Block size is at b16..b30 position in MMCIDATACTRL register
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BlockSizeDataControl4:LongBool;
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True if Block size is at b4..b16 position in MMCIDATACTRL register
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PowerPowerUp:LongWord;
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Power up value for MMCIPOWER register
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ClockMaximum:LongWord;
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Maximum clk frequency supported by the controller
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SignalDirection:LongBool;
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Input/out direction of bus signals can be indicated
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PowerClockGate:LongBool;
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MMCIPOWER register must be used to gate the clock
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BusyDetect:LongBool;
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True if busy detection on dat0 is supported
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PowerNoPower:LongBool;
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Bits in MMCIPOWER don't control external power supply
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ExplicitMClockControl:LongBool;
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Enable explicit mclk control in driver
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QualcommFIFO:LongBool;
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Enable Qualcomm specific FIFO PIO read logic
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QualcommDMA:LongBool;
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Enable Qualcomm specific DMA glue for DMA transfers
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ReversedIRQ:LongBool;
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Handle data irq before cmd irq
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PL18X MMCI registers
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PPL18XMMCIRegisters = ^TPL18XMMCIRegisters;
TPL18XMMCIRegisters = record
| Note: Layout of the PL18X registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0172a/i1006458.html)
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Power:LongWord;
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Power control register
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Clock:LongWord;
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Clock control register
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Argument:LongWord;
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Argument register
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Command:LongWord;
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Command register
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RespCmd:LongWord;
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Response command register
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Response0:LongWord;
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Response register
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Response1:LongWord;
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Response register
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Response2:LongWord;
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Response register
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Response3:LongWord;
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Response register
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DataTimer:LongWord;
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Data timer
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DataLength:LongWord;
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Data length register
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DataCtrl:LongWord;
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Data control register
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DataCnt:LongWord;
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Data counter
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Status:LongWord;
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Status register
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Clear:LongWord;
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Clear register
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Mask0:LongWord;
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Interrupt 0 mask register
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Mask1:LongWord;
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Interrupt 1 mask register
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Select:LongWord;
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Secure digital memory card select register
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FifoCnt:LongWord;
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FIFO counter
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Reserved:array[$4C..$7C] of Byte;
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Reserved
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FIFO:LongWord;
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Data FIFO register (0x80 to 0xBC)
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PL18X SDHCI get RXFIFO count
TPL18XSDHCIGetRXFIFOCount = function(SDHCI:PPL18XSDHCIHost; Status,Remain:LongWord):LongWord;
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PL18X SDHCI host
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PPL18XSDHCIHost = ^TPL18XSDHCIHost;
TPL18XSDHCIHost = record
| SDHCI Properties
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SDHCI:TSDHCIHost;
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| PL18X Properties
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IRQ0:LongWord;
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IRQ1:LongWord;
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Lock:TSpinHandle;
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Host lock (Differs from lock in Host portion) Spin lock due to use by interrupt handler
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SingleIRQ:LongBool;
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The host only has a single IRQ line instead of the standard 2 lines
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Registers:PPL18XMMCIRegisters;
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Host registers
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Version:PPL18XVersionData;
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Host version data
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ClockRegister:LongWord;
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Current clock register value
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PowerRegister:LongWord;
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Current power register value
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DataCtrlRegister:LongWord;
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Current data control register value
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MaximumBlockSize:LongWord;
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Host maximum block size
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MaximumRequestSize:LongWord;
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Host maximum request size
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BusyStatus:LongWord;
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Current Busy Status for ST Micro variants
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GetRXFIFOCount:TPL18XSDHCIGetRXFIFOCount;
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Model specific GetRXFIFOCount function
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Public variables
PL18X specific variables
PL18X_MMCI_FIQ_ENABLED:LongBool;
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The SDHCI uses Fast Interrupt Requests (FIQ) instead of IRQ
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PL18X_MMCI_MIN_FREQ:LongWord = 400000;
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Minimum clock frequency for SDHCI (Default minimum of 400KHz)
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PL18X_MMCI_MAX_FREQ:LongWord = 400000;
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Maximum clock frequency for SDHCI (Default maximum of 400KHz)
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Function declarations
To be documented
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