Unit PL18X
From Ultibo.org
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Description
ARM PrimeCell PL180/181 Multimedia Card Interface Driver unit
The PL180/181 Multimedia Card is an ARM peripheral that is compatible with MMC multimedia cards and SD secure digital cards in memory mapped I/O format compatible with the ARM advanced peripheral bus (APB).
The design of the Pl180/181 allows for multiple cards per controller however this driver currently only supports attaching one card.
Constants
To be documented
Type definitions
PL18X version Id
PPL18XVersionID = ^TPL18XVersionID;
TPL18XVersionID = record
PeripheralID:LongWord;
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PeripheralMask:LongWord;
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VersionData:PPL18XVersionData;
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PL18X version data
PPL18XVersionData = ^TPL18XVersionData;
TPL18XVersionData = record
Name:String;
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Name of the device |
ClockRegister:LongWord;
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Default value for MCICLOCK register |
ClockEnable:LongWord;
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Enable value for MMCICLOCK register |
Clock8BitEnable:LongWord;
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Enable value for 8 bit bus |
ClockNegativeEdgeEnable:LongWord;
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Enable value for inverted data/cmd output |
DataLengthBits:LongWord;
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Number of bits in the MMCIDATALENGTH register |
FIFOSize:LongWord;
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Number of bytes that can be written when MMCI_TXFIFOEMPTY is asserted (likewise for RX) |
FIFOHalfSize:LongWord;
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Number of bytes that can be written when MCI_TXFIFOHALFEMPTY is asserted (likewise for RX) |
DataCommandEnable:LongWord;
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Enable value for data commands |
DataControlMaskDDR:LongWord;
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DDR mode mask in MMCIDATACTRL register |
DataControlMaskSDIO:LongWord;
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SDIO enable mask in MMCIDATACTRL register |
STSDIO:LongBool;
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Enable ST specific SDIO logic |
STClockDivider:LongBool;
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True if using a ST-specific clock divider algorithm |
BlockSizeDataControl16:LongBool;
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True if Block size is at b16..b30 position in MMCIDATACTRL register |
BlockSizeDataControl4:LongBool;
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True if Block size is at b4..b16 position in MMCIDATACTRL register |
PowerPowerUp:LongWord;
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Power up value for MMCIPOWER register |
ClockMaximum:LongWord;
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Maximum clk frequency supported by the controller |
SignalDirection:LongBool;
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Input/out direction of bus signals can be indicated |
PowerClockGate:LongBool;
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MMCIPOWER register must be used to gate the clock |
BusyDetect:LongBool;
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True if busy detection on dat0 is supported |
PowerNoPower:LongBool;
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Bits in MMCIPOWER don't control external power supply |
ExplicitMClockControl:LongBool;
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Enable explicit mclk control in driver |
QualcommFIFO:LongBool;
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Enable Qualcomm specific FIFO PIO read logic |
QualcommDMA:LongBool;
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Enable Qualcomm specific DMA glue for DMA transfers |
ReversedIRQ:LongBool;
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Handle data irq before cmd irq |
PL18X MMCI registers
PPL18XMMCIRegisters = ^TPL18XMMCIRegisters;
TPL18XMMCIRegisters = record
| Note: Layout of the PL18X registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0172a/i1006458.html) | |
Power:LongWord;
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Power control register |
Clock:LongWord;
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Clock control register |
Argument:LongWord;
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Argument register |
Command:LongWord;
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Command register |
RespCmd:LongWord;
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Response command register |
Response0:LongWord;
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Response register |
Response1:LongWord;
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Response register |
Response2:LongWord;
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Response register |
Response3:LongWord;
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Response register |
DataTimer:LongWord;
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Data timer |
DataLength:LongWord;
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Data length register |
DataCtrl:LongWord;
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Data control register |
DataCnt:LongWord;
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Data counter |
Status:LongWord;
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Status register |
Clear:LongWord;
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Clear register |
Mask0:LongWord;
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Interrupt 0 mask register |
Mask1:LongWord;
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Interrupt 1 mask register |
Select:LongWord;
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Secure digital memory card select register |
FifoCnt:LongWord;
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FIFO counter |
Reserved:array[$4C..$7C] of Byte;
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Reserved |
FIFO:LongWord;
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Data FIFO register (0x80 to 0xBC) |
PL18X SDHCI get RXFIFO count
TPL18XSDHCIGetRXFIFOCount = function(SDHCI:PPL18XSDHCIHost; Status,Remain:LongWord):LongWord;
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PL18X SDHCI host
PPL18XSDHCIHost = ^TPL18XSDHCIHost;
TPL18XSDHCIHost = record
| SDHCI Properties | |
SDHCI:TSDHCIHost;
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| PL18X Properties | |
IRQ0:LongWord;
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IRQ1:LongWord;
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Lock:TSpinHandle;
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Host lock (Differs from lock in Host portion) Spin lock due to use by interrupt handler |
SingleIRQ:LongBool;
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The host only has a single IRQ line instead of the standard 2 lines |
Registers:PPL18XMMCIRegisters;
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Host registers |
Version:PPL18XVersionData;
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Host version data |
ClockRegister:LongWord;
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Current clock register value |
PowerRegister:LongWord;
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Current power register value |
DataCtrlRegister:LongWord;
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Current data control register value |
MaximumBlockSize:LongWord;
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Host maximum block size |
MaximumRequestSize:LongWord;
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Host maximum request size |
BusyStatus:LongWord;
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Current Busy Status for ST Micro variants |
GetRXFIFOCount:TPL18XSDHCIGetRXFIFOCount;
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Model specific GetRXFIFOCount function |
Public variables
PL18X specific variables
PL18X_MMCI_FIQ_ENABLED:LongBool;
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The SDHCI uses Fast Interrupt Requests (FIQ) instead of IRQ |
PL18X_MMCI_MIN_FREQ:LongWord = 400000;
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Minimum clock frequency for SDHCI (Default minimum of 400KHz) |
PL18X_MMCI_MAX_FREQ:LongWord = 400000;
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Maximum clock frequency for SDHCI (Default maximum of 400KHz) |
Function declarations
To be documented
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