Unit SMC91X
From Ultibo.org
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Description
SMSC 91C9x/91C1xx Ethernet Driver unit
The SMSC 91C9x/91C1xx are a family of Non-PCI 10/100 Ethernet Single Chip MAC + PHY devices.
This driver is primarily intended to support the LAN91C111 Ethernet device included in the QEMU Verstile PB emulation however the driver is based on the equivalent Linux driver and as such includes (untested) support for a number of chip variants (see SMC91X_CHIP_* constants below).
The QEMU emulation does not include support for a number of the features provided in the real chip so they are either currently not supported or are untested without access to a physical chip implementation for testing.
Constants
SMC91X specific constants
SMC91X_* SMC91X_NETWORK_DESCRIPTION = 'SMSC 91C9x/91C1xx Ethernet';
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Description of SMC91X device |
SMC91X_COMPLETION_THREAD_STACK_SIZE = SIZE_128K;
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Stack size of receive and transmit completion thread |
SMC91X_COMPLETION_THREAD_PRIORITY = THREAD_PRIORITY_HIGHER;
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Priority of receive and transmit completion thread |
SMC91X_COMPLETION_THREAD_NAME = 'SMSC 91C9x/91C1xx Completion';
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Name of receive and transmit completion thread |
SMC91X_COMPLETION_RECEIVE = 0;
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A receive message sent to the completion thread |
SMC91X_COMPLETION_TRANSMIT = 1;
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A transmit message sent to the completion thread |
SMC91X_COMPLETION_ALLOCATE = 2;
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An allocate message sent to the completion thread |
SMC91X_COMPLETION_TERMINATE = 3;
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A terminate message sent to the completion thread |
SMC91X_MAX_TX_ENTRIES = SIZE_16;
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Number of Transmit buffers allocated |
SMC91X_MAX_RX_ENTRIES = SIZE_256;
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Number of Receive buffers allocated |
SMC91X_MAX_PACKET_SIZE = 2048;
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SMC91X transmit control register
SMC91X_TCR_* SMC91X_TCR_ENABLE = $0001;
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Transmit enabled when set |
SMC91X_TCR_LOOP = $0002;
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Loopback. General purpose output port used to control the LBK pin. |
SMC91X_TCR_FORCOL = $0004;
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When set, the FORCOL bit will force a collision by not deferring deliberately. |
SMC91X_TCR_PAD_EN = $0080;
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When set, will pad transmit frames shorter than 64 bytes with 00. |
SMC91X_TCR_NOCRC = $0100;
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Does not append CRC to transmitted frames when set |
SMC91X_TCR_MON_CSN = $0400;
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When set monitors carrier while transmitting |
SMC91X_TCR_FDUPLX = $0800;
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When set will cause frames to be received if they pass the address filter regardless of the source for the frame. When clear the node will not receive a frame sourced by itself. |
SMC91X_TCR_STP_SQET = $1000;
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Stop transmission on SQET error. If this bit is set, will stop and disable the transmitter on SQE test error. |
SMC91X_TCR_EPH_LOOP = $2000;
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Internal loopback at the EPH block |
SMC91X_TCR_SWFDUP = $8000;
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Enables Switched Full Duplex mode |
| Default settings | |
SMC91X_TCR_DEFAULT = SMC91X_TCR_ENABLE or SMC91X_TCR_PAD_EN;
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SMC91X_TCR_CLEAR = 0;
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SMC91X EPH status (Ethernet Protocol Handler)
SMC91X_EPH_STATUS_* SMC91X_EPH_STATUS_TX_SUC = $0001;
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Last transmit was successful. Set if transmit completes without a fatal error. |
SMC91X_EPH_STATUS_SNGL_COL = $0002;
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Single collision detected for the last transmit frame. Set when a collision is detected. |
SMC91X_EPH_STATUS_MUL_COL = $0004;
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Multiple collision detected for the last transmit frame. Set when more than one collision was experienced. |
SMC91X_EPH_STATUS_LTX_MULT = $0008;
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Last transmit frame was a multicast. Set if frame was a multicast. |
SMC91X_EPH_STATUS_16COL = $0010;
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16 collisions reached. Set when 16 collisions are detected for a transmit frame. |
SMC91X_EPH_STATUS_SQET = $0020;
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Signal Quality Error Test |
SMC91X_EPH_STATUS_LTXBRD = $0040;
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Last transmit frame was a broadcast. Set if frame was broadcast. |
SMC91X_EPH_STATUS_TXDEFR = $0080;
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Transmit Deferred. When set, carrier was detected during the first 6.4us of the inter frame gap. |
SMC91X_EPH_STATUS_LATCOL = $0200;
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Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into the frame). |
SMC91X_EPH_STATUS_LOSTCARR = $0400;
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Lost Carrier Sense. When set indicates that Carrier Sense was not present at end of preamble. |
SMC91X_EPH_STATUS_EXC_DEF = $0800;
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Excessive Deferral. When set last/current transmit was deferred for more than 1518 * 2 byte times. |
SMC91X_EPH_STATUS_CTR_ROL = $1000;
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Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). |
SMC91X_EPH_STATUS_LINK_OK = $4000;
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General purpose input port driven by nLNK pin inverted |
SMC91X_EPH_STATUS_TXUNRN = $8000;
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TX Underrun |
SMC91X receive control register
SMC91X_RCR_* SMC91X_RCR_RX_ABORT = $0001;
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This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be received. The bit is cleared by RESET or by the CPU writing it low. |
SMC91X_RCR_PRMS = $0002;
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Promiscuous mode. When set receives all frames. Does not receive its own transmission unless it is in Full Duplex. |
SMC91X_RCR_ALMUL = $0004;
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When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear accepts only the multicast frames that match the multicast table setting. Defaults low. |
SMC91X_RCR_RXEN = $0100;
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Enables the receiver when set. If cleared, completes receiving current frame and then goes idle. Defaults low on reset. |
SMC91X_RCR_STRIP_CRC = $0200;
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When set, it strips the CRC on received frames. As a result, both the Byte Count and the frame format do not contain the CRC. When clear, the CRC is stored in memory following the packet. Defaults low. |
SMC91X_RCR_ABORT_ENB = $0200;
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Enables abort of receive when collision occurs. Defaults low. When set, will automatically abort a packet being received when the appropriate collision input is activated. |
SMC91X_RCR_FILT_CAR = $0400;
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Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherwise recognizes a receive frame as soon as carrier sense is active. (Does NOT filter RX DV on MII) |
SMC91X_RCR_SOFTRST = $8000;
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Software-Activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. |
| Default settings | |
SMC91X_RCR_DEFAULT = SMC91X_RCR_STRIP_CRC or SMC91X_RCR_RXEN;
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SMC91X_RCR_CLEAR = 0;
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SMC91X receive/PHY control
SMC91X_RPC_* SMC91X_RPC_SPEED = $2000;
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Speed select Input (1=100Mbps / 0=0Mbps) |
SMC91X_RPC_DPLX = $1000;
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Duplex Select - This bit selects Full/Half Duplex operation (1=Full Duplex / 0=Half Duplex)) |
SMC91X_RPC_ANEG = $0800;
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Auto-Negotiation mode select |
SMC91X_RPC_LS2A = $0080;
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LED select Signal Enable. These bits define what LED control signals are routed to the LEDA output pin on the Ethernet Controller. The default is 10/100 Link detected. |
SMC91X_RPC_LS1A = $0040;
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SMC91X_RPC_LS0A = $0020;
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SMC91X_RPC_LS2B = $0010;
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LED select Signal Enable. These bits define what LED control signals are routed to the LEDB output pin on the Ethernet Controller. The default is 10/100 Link detected. |
SMC91X_RPC_LS1B = $0008;
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SMC91X_RPC_LS0B = $0004;
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| Default Settings | |
SMC91X_RPC_DEFAULT = SMC91X_RPC_ANEG or SMC91X_RPC_SPEED or SMC91X_RPC_DPLX;
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| RPC LS2A/LS1A/LS0A and LS2B/LS1B/LS0B values | |
SMC91X_RPC_LED_100_10 = $00;
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LED = 100Mbps OR's with 10Mbps link detect |
SMC91X_RPC_LED_RES = $01;
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LED = Reserved |
SMC91X_RPC_LED_10 = $02;
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LED = 10Mbps link detect |
SMC91X_RPC_LED_FD = $03;
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LED = Full Duplex Mode |
SMC91X_RPC_LED_TX_RX = $04;
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LED = TX or RX packet occurred |
SMC91X_RPC_LED_100 = $05;
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LED = 100Mbps link detect |
SMC91X_RPC_LED_TX = $06;
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LED = TX packet occurred |
SMC91X_RPC_LED_RX = $07;
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LED = RX packet occurred |
SMC91X configuration
SMC91X_CONFIG_* SMC91X_CONFIG_EXT_PHY = $0200;
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External PHY Enabled (1=Enables the external MII / 0=Internal PHY is enabled) |
SMC91X_CONFIG_GPCNTRL = $0400;
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This bit is a general purpose output port. Its inverse value drives pin nCNTRL and it is typically connected to a SELECT pin of the external PHY device such as a power enable. |
SMC91X_CONFIG_NO_WAIT = $1000;
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When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. |
SMC91X_CONFIG_EPH_POWER_EN = $8000;
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Used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the Host will place the EPH into a low power mode. |
SMC91X_CONFIG_RESERVED = $20B1;
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Reserved values |
| Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
SMC91X_CONFIG_DEFAULT = SMC91X_CONFIG_EPH_POWER_EN;
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SMC91X control
SMC91X_CTL_* SMC91X_CTL_RCV_BAD = $4000;
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When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their memory is released. |
SMC91X_CTL_AUTO_RELEASE = $0800;
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When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). |
SMC91X_CTL_LE_ENABLE = $0080;
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Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the EPH INT bit. |
SMC91X_CTL_CR_ENABLE = $0040;
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Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into the EPH INT bit. |
SMC91X_CTL_TE_ENABLE = $0020;
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Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH INT bit. |
SMC91X_CTL_EEPROM_SELECT = $0004;
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This bit allows the CPU to specify which registers the EEPROM RELOAD or STORE refers to |
SMC91X_CTL_RELOAD = $0002;
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When set it will read the EEPROM and update relevant registers with its contents |
SMC91X_CTL_STORE = $0001;
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When set, stores the contents of all relevant registers in the serial EEPROM. |
SMC91X MMU command
SMC91X_MMU_CMD_* SMC91X_MMU_CMD_BUSY = 1;
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When 1 the last command has not completed |
SMC91X_MMU_CMD_NOP = (0 shl 5);
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NOOP - NO OPERATION |
SMC91X_MMU_CMD_ALLOC = (1 shl 5);
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ALLOCATE MEMORY FOR TX (OR with number of 256 byte packets) |
SMC91X_MMU_CMD_RESET = (2 shl 5);
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RESET MMU TO INITIAL STATE (Frees all memory allocations, clears relevant interrupts, resets packet FIFO pointers) |
SMC91X_MMU_CMD_REMOVE = (3 shl 5);
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REMOVE FRAME FROM TOP OF RX FIFO (To be issued after CPU has completed processing of present receive frame) |
SMC91X_MMU_CMD_RELEASE = (4 shl 5);
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REMOVE AND RELEASE TOP OF RX FIFO (Like 3) but also releases all memory used by the packet presently at the RX FIFO output) |
SMC91X_MMU_CMD_FREEPKT = (5 shl 5);
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RELEASE SPECIFIC PACKET (Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER) |
SMC91X_MMU_CMD_ENQUEUE = (6 shl 5);
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ENQUEUE PACKET NUMBER INTO TX FIFO (This is the normal method of transmitting a packet just loaded into RAM) |
SMC91X_MMU_CMD_RSTTXFIFO = (7 shl 5);
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RESET TX FIFOs (This command will reset both TX FIFOs) |
SMC91X allocation result
SMC91X_AR_* SMC91X_AR_FAILED = $80;
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FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. |
SMC91X TX FIFO ports
SMC91X_TXFIFO_* SMC91X_TXFIFO_TEMPTY = $80;
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TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status Register. |
SMC91X RX FIFO ports
SMC91X_RXFIFO_* SMC91X_RXFIFO_REMPTY = $80;
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REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Status Register. |
SMC91X pointer
SMC91X_PTR_* SMC91X_PTR_RCV = $8000;
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When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. |
SMC91X_PTR_AUTOINC = $4000;
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It will auto-increment on accesses to the data register when AUTO INCR is set. The increment is by one for every byte access, by two for every word access, and by four for every double word access. |
SMC91X_PTR_READ = $2000;
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Determines the type of access to follow. If the READ bit is high the operation intended is a read. |
SMC91X interrupt mask
SMC91X_IM_* SMC91X_IM_MDINT = $80;
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PHY MI Register 18 Interrupt |
SMC91X_IM_ERCV_INT = $40;
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Early Receive Interrupt |
SMC91X_IM_EPH_INT = $20;
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Set by Ethernet Protocol Handler section |
SMC91X_IM_RX_OVRN_INT = $10;
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Set by Receiver Overruns |
SMC91X_IM_ALLOC_INT = $08;
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Set when allocation request is completed |
SMC91X_IM_TX_EMPTY_INT = $04;
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Set if the TX FIFO goes empty |
SMC91X_IM_TX_INT = $02;
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Transmit Interrupt |
SMC91X_IM_RCV_INT = $01;
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Receive Interrupt |
SMC91X management interface
SMC91X_MII_* SMC91X_MII_MSK_CRS100 = $4000;
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Disables CRS100 detection during tx half dup |
SMC91X_MII_MDOE = $0008;
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MII Output Enable |
SMC91X_MII_MCLK = $0004;
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MII Clock, pin MDCLK |
SMC91X_MII_MDI = $0002;
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MII Input, pin MDI |
SMC91X_MII_MDO = $0001;
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MII Output, pin MDO |
SMC91X_MII_DELAY = 1;
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The MII clock high/low times. 2 x this number gives the MII clock period in microseconds. |
SMC91X receive
SMC91X_RCV_THRESHOLD* SMC91X_RCV_RCV_DISCRD = $0080;
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Set to discard a packet being received. Will discard packets only in the process of being received. |
SMC91X_RCV_THRESHOLD = $001F;
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RCV Threshold Mask |
SMC91X receive status
SMC91X_RCV_* SMC91X_RCV_ALGNERR = $8000;
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Frame has alignment error |
SMC91X_RCV_BRODCAST = $4000;
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Receive frame was Broadcast (The Multicast bit may also be set, software must ignore the Multicast bit for a Bradcast packet). |
SMC91X_RCV_BADCRC = $2000;
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Frame has CRC error or RX_ER was asserted during reception |
SMC91X_RCV_ODDFRAME = $1000;
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This bit when set indicates that the received frame has an odd number of bytes |
SMC91X_RCV_TOOLONG = $0800;
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Frame length was longer than 802.3 maximum size (1518 bytes on the cable) |
SMC91X_RCV_TOOSHORT = $0400;
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Frame length was shorter than 802.3 minimum size (64 bytes on the cable) |
SMC91X_RCV_MULTICAST = $0001;
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Receive frame was Multicast |
SMC91X_RCV_ERRORS = (SMC91X_RCV_ALGNERR or SMC91X_RCV_BADCRC or SMC91X_RCV_TOOLONG or SMC91X_RCV_TOOSHORT);
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SMC91X bank select
SMC91X_BANK_SELECT_* SMC91X_BANK_SELECT_0 = 0;
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SMC91X_BANK_SELECT_1 = 1;
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SMC91X_BANK_SELECT_2 = 2;
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SMC91X_BANK_SELECT_3 = 3;
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SMC91X chip
SMC91X_CHIP_* | Bits 4-7 of the Revision register | |
SMC91X_CHIP_COUNT = 16;
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SMC91X_CHIP_9192 = 3;
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SMC91X_CHIP_9194 = 4;
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SMC91X_CHIP_9195 = 5;
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SMC91X_CHIP_9196 = 6;
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SMC91X_CHIP_91100 = 7;
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SMC91X_CHIP_91100FD = 8;
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SMC91X_CHIP_91111FD = 9;
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SMC91X_CHIP_NAMES:array[0..SMC91X_CHIP_COUNT - 1] of String = (
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' ',
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' ',
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' ',
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'SMC91C90/91C92',
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3 |
'SMC91C94',
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4 |
'SMC91C95',
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5 |
'SMC91C96',
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6 |
'SMC91C100',
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7 |
'SMC91C100FD',
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8 |
'SMC91C11xFD',
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9 |
' ',
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' ',
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' ',
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' ',
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' ',
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' ');
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SMC91X PHY Ids
SMC91X_PHY_* SMC91X_PHY_LAN83C183 = $0016f840;
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LAN83C183 = LAN91C111 Internal PHY |
SMC91X_PHY_LAN83C180 = $02821c50;
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| SMC91X PHY Register Addresses (LAN91C111 Internal PHY) | |
| Register 0. Control Register | |
| See: Network Generic MII registers (MII_BMCR) | |
| Register 1. Status Register | |
| See: Network Generic MII registers (MII_BMSR) | |
| Register 2 & 3. PHY Identifier Register | |
| See: Network Generic MII registers (MII_PHYSID1 / MII_PHYSID2) | |
| Register 4. Auto-Negotiation Advertisement Register | |
| See: Network Generic MII registers (MII_ADVERTISE) | |
| Register 5. Auto-Negotiation Remote End Capability Register | |
| See: Network Generic MII registers (MII_LPA) | |
| Register 16. Configuration 1- Structure and Bit Definition | |
SMC91X_PHY_CFG1_REG = $10;
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SMC91X_PHY_CFG1_LNKDIS = $8000;
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1=Rx Link Detect Function disabled |
SMC91X_PHY_CFG1_XMTDIS = $4000;
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1=TP Transmitter Disabled |
SMC91X_PHY_CFG1_XMTPDN = $2000;
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1=TP Transmitter Powered Down |
SMC91X_PHY_CFG1_BYPSCR = $0400;
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1=Bypass scrambler/descrambler |
SMC91X_PHY_CFG1_UNSCDS = $0200;
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1=Unscramble Idle Reception Disable |
SMC91X_PHY_CFG1_EQLZR = $0100;
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1=Rx Equalizer Disabled |
SMC91X_PHY_CFG1_CABLE = $0080;
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1=STP(150ohm), 0=UTP(100ohm) |
SMC91X_PHY_CFG1_RLVL0 = $0040;
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1=Rx Squelch level reduced by 4.5db |
SMC91X_PHY_CFG1_TLVL_SHIFT = 2;
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Transmit Output Level Adjust |
SMC91X_PHY_CFG1_TLVL_MASK = $003C;
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SMC91X_PHY_CFG1_TRF_MASK = $0003;
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Transmitter Rise/Fall time |
| Register 17. Configuration 2 - Structure and Bit Definition | |
SMC91X_PHY_CFG2_REG = $11;
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SMC91X_PHY_CFG2_APOLDIS = $0020;
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1=Auto Polarity Correction disabled |
SMC91X_PHY_CFG2_JABDIS = $0010;
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1=Jabber disabled |
SMC91X_PHY_CFG2_MREG = $0008;
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1=Multiple register access (MII mgt) |
SMC91X_PHY_CFG2_INTMDIO = $0004;
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1=Interrupt signaled with MDIO pulseo |
| Register 18. Status Output - Structure and Bit Definition | |
SMC91X_PHY_INT_REG = $12;
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Status Output (Interrupt Status) |
SMC91X_PHY_INT_INT = $8000;
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1=bits have changed since last read |
SMC91X_PHY_INT_LNKFAIL = $4000;
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1=Link Not detected |
SMC91X_PHY_INT_LOSSSYNC = $2000;
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1=Descrambler has lost sync |
SMC91X_PHY_INT_CWRD = $1000;
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1=Invalid 4B5B code detected on rx |
SMC91X_PHY_INT_SSD = $0800;
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1=No Start Of Stream detected on rx |
SMC91X_PHY_INT_ESD = $0400;
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1=No End Of Stream detected on rx |
SMC91X_PHY_INT_RPOL = $0200;
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1=Reverse Polarity detected |
SMC91X_PHY_INT_JAB = $0100;
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1=Jabber detected |
SMC91X_PHY_INT_SPDDET = $0080;
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1=100Base-TX mode, 0=10Base-T mode |
SMC91X_PHY_INT_DPLXDET = $0040;
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1=Device in Full Duplex |
| Register 19. Mask - Structure and Bit Definition | |
SMC91X_PHY_MASK_REG = $13;
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Interrupt Mask (Uses the same bit definitions as PHY_INT_REG) |
| Register 20. Reserved - Structure and Bit Definition | |
| Nothing | |
Type definitions
To be documented
Public variables
To be documented
Function declarations
To be documented
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