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Description
The ARMv7 does not support the SWP/SWPB instructions for syncronisation (Lock/Mutex/Semaphore etc) unless enabled.
On ARMv7 Unaligned memory access is always enabled.
On ARMv7 the Extended Page Table format is always enabled.
For usage of barriers (DMB/DSB/ISB) after cache maintenance operations see: ARM.Reference_Manual_1.pdf - Appendix G Barrier Litmus Tests
Constants
To be documented
Type definitions
To be documented
Public variables
To be documented
Function declarations
Initialization functions
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procedure ARMv7Init;
Description: To be documented
ARMv7 platform functions
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procedure ARMv7CPUInit; assembler; nostackframe;
Description: To be documented
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procedure ARMv7FPUInit; assembler; nostackframe;
Description: To be documented
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procedure ARMv7MMUInit;
Description: To be documented
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procedure ARMv7CacheInit; assembler; nostackframe;
Description: To be documented
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procedure ARMv7TimerInit(Frequency:LongWord); assembler; nostackframe;
Description: To be documented
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procedure ARMv7PageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU
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procedure ARMv7SystemCall(Number:LongWord; Param1,Param2,Param3:LongWord); assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetMode:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetState:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetCurrent:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetMainID:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetMultiprocessorID:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7CPUGetModel:LongWord;
Description: To be documented
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function ARMv7CPUGetRevision:LongWord;
Description: To be documented
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function ARMv7CPUGetDescription:String;
Description: To be documented
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function ARMv7FPUGetState:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L1CacheGetType:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L1DataCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L1DataCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L1InstructionCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L1InstructionCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L2CacheGetType:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L2CacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented
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function ARMv7L2CacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented
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procedure ARMv7Halt; assembler; nostackframe; public name'_haltproc';
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state
| Note
|
See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual
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procedure ARMv7Pause; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state
| Note
|
See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual
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procedure ARMv7SendEvent; assembler; nostackframe;
Description: To be documented
| Note
|
See Page A8-316 of the ARMv7 Architecture Reference Manual
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procedure ARMv7WaitForEvent; assembler; nostackframe;
Description: To be documented
| Note
|
See Page A8-808 of the ARMv7 Architecture Reference Manual
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procedure ARMv7WaitForInterrupt; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state
| Note
|
See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual
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procedure ARMv7DataMemoryBarrier; assembler; nostackframe;
Description: Perform a data memory barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15
| Note
|
See page A8-90 of the ARMv7 Architecture Reference Manual
Note that this is also available in the FPC RTL as ReadBarrier/WriteBarrier See: \source\rtl\arm\arm.inc
Implementation is exactly the same for either.
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procedure ARMv7DataSynchronizationBarrier; assembler; nostackframe;
Description: Perform a data synchronization barrier operation
| Note
|
See page A8-92 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InstructionMemoryBarrier; assembler; nostackframe;
Description: Perform a instruction synchronization barrier operation
| Note
|
See page A8-102 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateTLB; assembler; nostackframe;
Description: Perform an invalidate entire TLB operation using the c8 (TLB Operations) register of system control coprocessor CP15
| Note
|
See page B3-138 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateDataTLB; assembler; nostackframe;
Description: Perform an invalidate data TLB (Unlocked/Data) operation using the c8 (TLB Operations) register of system control coprocessor CP15
| Note
|
See page B3-138 of the ARMv7 Architecture Reference Manual
|
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procedure ARMv7InvalidateInstructionTLB; assembler; nostackframe;
Description: Perform an invalidate instruction TLB (Unlocked/Instruction) operation using the c8 (TLB Operations) register of system control coprocessor CP15
| Note
|
See page B3-138 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateCache; assembler; nostackframe;
Description: Perform an invalidate both caches operation using the c7 (Cache Operations) register of system control coprocessor CP15
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7CleanDataCache; assembler; nostackframe;
Description: Perform a clean entire data cache operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateDataCache; assembler; nostackframe;
Description: Perform an invalidate entire data cache operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateL1DataCache; assembler; nostackframe;
Description: Perform an invalidate entire L1 data cache operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7CleanAndInvalidateDataCache; assembler; nostackframe;
Description: Perform a clean and invalidate entire data cache operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateInstructionCache; assembler; nostackframe;
Description: Perform an invalidate entire instruction cache operation using the c7 (Cache Operations) register of system control coprocessor CP15
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7CleanDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform a clean data cache by MVA to PoC operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate data cache by MVA to PoC operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
|
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procedure ARMv7CleanAndInvalidateDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform a clean and invalidate data cache by MVA to PoC operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateInstructionCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate instruction caches by MVA to PoU operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7CleanDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;
Description: Perform a clean data cache line by set/way operation
| SetWay
|
Set/Way/Level will be passed in r0
|
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7InvalidateDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;
Description: Perform an invalidate data cache line by set/way operation
| SetWay
|
Set/Way/Level will be passed in r0
|
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7CleanAndInvalidateDataCacheSetWay(SetWay:LongWord); assembler; nostackframe;
Description: Perform a clean and invalidate data cache line by set/way operation
| SetWay
|
Set/Way/Level will be passed in r0
|
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7FlushPrefetchBuffer; assembler; nostackframe;
Description: Perform an Instruction Synchronization Barrier operation
| Note
|
See page A8-102 of the ARMv7 Architecture Reference Manual
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procedure ARMv7FlushBranchTargetCache; assembler; nostackframe;
Description: Perform a Flush Entire Branch Target Cache operation
| Note
|
See page B3-127 of the ARMv7 Architecture Reference Manual
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procedure ARMv7ContextSwitch(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a thread yielding, sleeping or waiting
| OldStack
|
The address to save the stack pointer to for the current thread (Passed in r0)
|
| NewStack
|
The address to restore the stack pointer from for the new thread (Passed in r1)
|
| NewThread
|
The handle of the new thread to switch to (Passed in r2)
|
| Note
|
At the point of the actual context switch (str sp / ldr sp) the thread stacks will look like this:
(See: ARMv7ThreadSetupStack for additional information)
(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-
d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-
fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)
This form of context switch uses r12 to save the cpsr value (and RFE to restore it). Because this context switch is called from a routine which will have saved the value of r12 (which is caller save in the ARM ABI) then we do not need to save the original value of r12.
The context switch will be performed from SYS mode to SYS mode, the cpsr value will include the control bits (Mode and IRQ/FIQ state) but not the flags values. Again the ARM ABI does not require that the flags be saved by the callee and so the caller would have accounted for any needed flags before calling. If the thread to be resumed was interrupted by an IRQ or FIQ then the cpsr will also contain the flags etc as they were at the point of interrupt. We do not need to account for the state bits in the cpsr since all operations are performed in ARM mode at present.
The main requirement of this routine is to ensure that the context record on the stack matches exactly that which is created on an interrupt and also that created by ThreadSetupStack for a new thread. If this is correct then the next context switch for any given thread can be either by a call to reschedule or by an interrupt. Equally a new thread can be first run from a context switch that resulted from either a call to reschedule or an interrupt.
Note that this routine could use:
pop (lr)
pop (r12)
msr cpsr_c, r12
mov pc, lr
To return but that would mess up the value of r12, lr and the cpsr flags etc if the thread being resumed was interrupted by an IRQ, FIQ or SWI. The use of RFE here allows for exactly the same behaviour no matter which way the context record is saved and restored.
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procedure ARMv7ContextSwitchIRQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of an interrupt request (IRQ)
| OldStack
|
The address to save the stack pointer to for the current thread (Passed in r0)
|
| NewStack
|
The address to restore the stack pointer from for the new thread (Passed in r1)
|
| NewThread
|
The handle of the new thread to switch to (Passed in r2)
|
| Note
|
At the point of the actual context switch (str sp / ldr sp) the thread stacks will look like this:
(See: ARMv7ThreadSetupStack for additional information)
(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-
d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-
fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)
This form of context switch relies on the IRQ handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous IRQ or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.
The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to IRQ mode.
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procedure ARMv7ContextSwitchFIQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a fast interrupt request (FIQ)
| OldStack
|
The address to save the stack pointer to for the current thread (Passed in r0)
|
| NewStack
|
The address to restore the stack pointer from for the new thread (Passed in r1)
|
| NewThread
|
The handle of the new thread to switch to (Passed in r2)
|
| Note
|
At the point of the actual context switch (str sp / ldr sp) the thread stacks will look like this:
(See: ARMv7ThreadSetupStack for additional information)
(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-
d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-
fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)
This form of context switch relies on the FIQ handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous FIQ or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.
The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to FIQ mode.
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procedure ARMv7ContextSwitchSWI(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a software interrupt (SWI)
| OldStack
|
The address to save the stack pointer to for the current thread (Passed in r0)
|
| NewStack
|
The address to restore the stack pointer from for the new thread (Passed in r1)
|
| NewThread
|
The handle of the new thread to switch to (Passed in r2)
|
| Note
|
At the point of the actual context switch (str sp / ldr sp) the thread stacks will look like this:
(See: ARMv7ThreadSetupStack for additional information)
(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
lr/pc <- The address to return to from the context switch
lr <- The lr value prior to the context switch
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <-
r4 <-
r3 <-
r2 <-
r1 <-
r0 <-
d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <-
d6 <-
d5 <-
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-
fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)
This form of context switch relies on the SWI handler to save the necessary registers including the lr, cpsr and other general registers from the point at which the thread was interrupted. The thread to be resumed may have been saved by a previous SWI or by a call to the standard context switch from SchedulerReschule or it may be a new thread to be run for the first time. All of these result in the same context record on the stack and therefore can be resumed the same way.
The context switch will be performed by switching to SYS mode, exchanging the stack pointers and then returning to SWI (SVC) mode.
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function ARMv7InterlockedOr(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic OR operation using LDREX/STREX
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function ARMv7InterlockedXor(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic XOR operation using LDREX/STREX
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function ARMv7InterlockedAnd(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic AND operation using LDREX/STREX
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function ARMv7InterlockedDecrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic decrement operation using LDREX/STREX
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function ARMv7InterlockedIncrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic increment operation using LDREX/STREX
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function ARMv7InterlockedExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic exchange operation using LDREX/STREX
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function ARMv7InterlockedAddExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic add and exchange operation using LDREX/STREX
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function ARMv7InterlockedCompareExchange(var Target:LongInt; Source,Compare:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic compare and exchange operation using LDREX/STREX
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function ARMv7PageTableGetEntry(Address:PtrUInt):TPageTableEntry;
Description: Get and Decode the entry in the Page Table that corresponds to the supplied virtual address
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function ARMv7PageTableSetEntry(const Entry:TPageTableEntry):LongWord;
Description: Encode and Set an entry in the Page Table that corresponds to the supplied virtual address
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function ARMv7VectorTableGetEntry(Number:LongWord):PtrUInt;
Description: Return the address of the specified vector table entry number
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function ARMv7VectorTableSetEntry(Number:LongWord; Address:PtrUInt):LongWord;
Description: Set the supplied address as the value of the specified vector table entry number
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function ARMv7FirstBitSet(Value:LongWord):LongWord; assembler; nostackframe;
Description: To be documented
| Note
|
ARM arm states that CLZ is supported for ARMv5 and above
|
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function ARMv7CountLeadingZeros(Value:LongWord):LongWord; assembler; nostackframe;
Description: Equivalent of the GCC Builtin function __builtin_clz
| Note
|
ARM arm states that CLZ is supported for ARMv5 and above
|
ARMv7 thread functions
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procedure ARMv7PrimaryInit; assembler; nostackframe;
Description: To be documented
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function ARMv7SpinLock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinUnlock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
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function ARMv7SpinLockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and save the previous IRQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinUnlockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinLockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable FIQ and save the previous FIQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinUnlockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous FIQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinLockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and FIQ and save the previous IRQ/FIQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinUnlockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ/FIQ state
| Spin
|
Pointer to the Spin entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7SpinCheckIRQ(Spin:PSpinEntry):Boolean;
Description: To be documented
| Return
|
True if the mask would enable IRQ on restore, False if it would not
|
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function ARMv7SpinCheckFIQ(Spin:PSpinEntry):Boolean;
Description: To be documented
| Return
|
True if the mask would enable FIQ on restore, False if it would not
|
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function ARMv7SpinExchangeIRQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented
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function ARMv7SpinExchangeFIQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented
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function ARMv7MutexLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Mutex entry
| Mutex
|
Pointer to the Mutex entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7MutexUnlock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Mutex entry
| Mutex
|
Pointer to the Mutex entry to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure (Returned in R0)
|
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function ARMv7MutexTryLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Try to lock an existing Mutex entry
| Mutex
|
Pointer to the Mutex entry to try to lock (Passed in R0)
|
| Return
|
ERROR_SUCCESS if completed, ERROR_LOCKED if already locked or another error code on failure (Returned in R0)
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function ARMv7ThreadGetCurrent:TThreadHandle; assembler; nostackframe;
Description: Get the current thread id from the c13 (Thread and process ID) register of system control coprocessor CP15
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function ARMv7ThreadSetCurrent(Thread:TThreadHandle):LongWord; assembler; nostackframe;
Description: Set the current thread id in the c13 (Thread and process ID) register of system control coprocessor CP15
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function ARMv7ThreadSetupStack(StackBase:Pointer; StartProc:TThreadStart; ReturnProc:TThreadEnd; Parameter:Pointer):Pointer;
Description: Set up the context record and arguments on the stack for a new thread
| StackBase
|
Pointer to the base (highest address) of the allocated stack (as returned by ThreadAllocateStack
|
| StartProc
|
The procedure the thread will start executing when resumed
|
| ReturnProc
|
The procedure the thread will return to on exit
|
| Return
|
Pointer to the starting address of the stack, which will be the Stack Pointer on the first context switch
|
| Note
|
At the point of a context switch the thread stack will look like this:
(Base "Highest Address" of Stack)
.
.
.
.
cpsr <- The current program status register value to load on return from the context switch
(On Interrupt: Includes the flags and control bits for the interrupted thread)
(On Yield: Includes the control bits only for the yielded thread)
(On Create: Includes the control bits only for the new thread)
lr/pc <- The address to return to from the context switch
(On Interrupt: The location the thread was at before interrupt)
(On Yield: The location to return to in SchedulerReschedule)
(On Create: The location of StartProc for the new thread)
lr <- The lr value prior to the context switch
(On Interrupt: The value of lr before the thread was interrupted)
(On Yield: The location to return to in SchedulerReschedule)
(On Create: The location of ReturnProc for the new thread)
r12 <-
r11 <-
r10 <-
r9 <-
r8 <-
r7 <-
r6 <- The value of these registers prior to the context switch
r5 <- (On Interrupt: The values before the thread was interrupted)
r4 <- (On Yield: The values on return to SchedulerReschedule)
r3 <- (On Create: The values on entry to StartProc as set by ThreadSetupStack)
r2 <-
r1 <-
r0 <-
d15 <-
d14 <-
d13 <-
d12 <-
d11 <-
d10 <-
d9 <-
d8 <- The value of these floating point registers prior to the context switch
d7 <- (On Interrupt: The values before the thread was interrupted)
d6 <- (On Yield: The values on return to SchedulerReschedule)
d5 <- (On Create: The values on entry to StartProc as set by ThreadSetupStack)
d4 <-
d3 <-
d2 <-
d1 <-
d0 <-
fpscr <- The floating point FPSCR register
fpexc <- The floating point FPEXC register (Current StackPointer points to here)
.
.
.
.
(Top "Lowest Address" of Stack)
On exit from a standard context switch as performed by SchedulerReschedule the first value (Highest Address) of lr is used by the RFE (Return From Exception) instruction to load the pc which also loads the saved cpsr value.
On exit from an IRQ or FIQ context switch as performed by SchedulerSwitch the first value (Highest Address) of lr is used by the interrupt handler to return from the interrupt.
A standard context switch uses r12 to save the cpsr value (and RFE to restore it). Because the standard context switch is called from a routine which will have saved the value of r12 (which is caller save in the ARM ABI) then we do not need to save the original value of r12.
An IRQ or FIQ context switch uses the SRS (Store Return State) and RFE (Return From Exception) instructions to save and restore the cpsr value from the spsr value of either IRQ or FIQ mode.
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ARMv7 IRQ functions
[Expand]
function ARMv7DispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented
ARMv7 FIQ functions
[Expand]
function ARMv7DispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented
ARMv7 SWI functions
[Expand]
function ARMv7DispatchSWI(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle; inline;
Description: To be documented
ARMv7 interrupt functions
[Expand]
procedure ARMv7ResetHandler; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMv7UndefinedInstructionHandler; assembler; nostackframe;
Description: Handle an undefined instruction exception
| Note
|
This routine is registered as the vector for undefined instruction exception in the vector table loaded during startup
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[Expand]
procedure ARMv7SoftwareInterruptHandler; assembler; nostackframe;
Description: Handle a software interrupt (SWI) from a system call (SVC)
| Note
|
This routine is registered as the vector for SWI requests in the vector table loaded during startup. When the processor executes an SVC it switches to SWI mode, stores the address of the next instruction in the SWI mode link register (lr_svc) and saves the current program status register into the SWI mode saved program status register (spsr_svc).
The SWI handler first saves the SWI mode lr and spsr (which represent the location and state to return to) onto the SYS mode stack using the srsdb (Store Return State Decrement Before) instruction.
The SWI handler then switches to SYS mode and saves all the neccessary registers for the return to the interrupted thread before switching back to SWI mode in order to process the software interrupt. Because we arrive here from an interrupt the thread that was executing has no opportunity to save registers and will be unaware on return that it was interrupted. For this reason we must save all of the general purpose registers (r0 to r12) as well as the SYS mode link register (lr). We do not save the stack pointer (r13) because we use it to store the other registers and will return it to the correct value before we return from the SWI handler. The program counter (r15) does not need to be saved as it now points to this code.
The SystemCall function should pass the parameters of the call as follows:
R0 - System Call Number (eg SYSTEM_CALL_CONTEXT_SWITCH)
R1 - Parameter 1
R2 - Parameter 2
R3 - Parameter 3
To process the software interrupt
??????
To return from the software interrupt
??????
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[Expand]
procedure ARMv7PrefetchAbortHandler; assembler; nostackframe;
Description: Handle a prefetch abort exception
| Note
|
This routine is registered as the vector for prefetch abort exception in the vector table loaded during startup
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[Expand]
procedure ARMv7DataAbortHandler; assembler; nostackframe;
Description: Handle a data abort exception
| Note
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This routine is registered as the vector for data abort exception in the vector table loaded during startup
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[Expand]
procedure ARMv7ReservedHandler; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMv7IRQHandler; assembler; nostackframe;
Description: Handle an interrupt request IRQ from an interrupt source
| Note
|
This routine is registered as the vector for IRQ requests in the vector table loaded during startup.
At the end of each instruction the processor checks the IRQ line and if triggered it will lookup the vector in the vector table and jump to the routine listed.
When the processor receives an IRQ it switches to IRQ mode, stores the address of the next instruction in the IRQ mode link register (lr_irq) and saves the current program status register into the IRQ mode saved program status register (spsr_irq).
The IRQ handler first saves the IRQ mode lr and spsr (which represent the location and state to return to) onto the SYS mode stack using the srsdb (Store Return State Decrement Before) instruction.
The IRQ handler then switches to SYS mode and saves all the neccessary registers for the return to the interrupted thread before switching back to IRQ mode in order to process the interrupt request. Because we arrive here from an interrupt the thread that was executing has no opportunity to save registers and will be unaware on return that it was interrupted. For this reason we must save all of the general purpose registers (r0 to r12) as well as the SYS mode link register (lr). We do not save the stack pointer (r13) because we use it to store the other registers and will return it to the correct value before we return from the IRQ handler. The program counter (r15) does not need to be saved as it now points to this code.
To process the interrupt request the handler calls the DispatchIRQ function which will dispatch the interrupt to a registered handler for processing. The handler must clear the interrupt source before it returns or the interrupt will simply occur again immediately once reenabled.
To return from the interrupt request the handler uses the rfeia (Return From Exception Increment After) instruction which will load the pc and cpsr from the SYS mode stack.
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[Expand]
procedure ARMv7FIQHandler; assembler; nostackframe;
Description: Handle a fast interrupt request FIQ from an interrupt source
| Note
|
This routine is registered as the vector for FIQ requests in the vector table loaded during startup.
At the end of each instruction the processor checks the FIQ line and if triggered it will lookup the vector in the vector table and jump to the routine listed.
When the processor receives an FIQ it switches to FIQ mode, stores the address of the next instruction in the FIQ mode link register (lr_fiq) and saves the current program status register into the FIQ mode saved program status register (spsr_fiq).
The FIQ handler first checks the spsr to determine if the task being interrupted is a normal thread or an exception or interrupt handler.
The FIQ handler then saves the FIQ mode lr and spsr (which represent the location and state to return to) onto eihter the SYS mode or SVC mode stack using the srsdb (Store Return State Decrement Before) instruction depending on the value of spsr.
The FIQ handler switches to SYS or SVC mode and saves all the neccessary registers for the return to the interrupted task before switching back to FIQ mode in order to process the interrupt request. Because we arrive here from an interrupt the task that was executing has no opportunity to save registers and will be unaware on return that it was interrupted. For this reason we must save all of the general purpose registers (r0 to r12) as well as the SYS mode link register (lr). We do not save the stack pointer (r13) because we use it to store the other registers and will return it to the correct value before we return from the FIQ handler. The program counter (r15) does not need to be saved as it now points to this code.
To process the fast interrupt request the handler calls the DispatchFIQ function which will dispatch the interrupt to a registered handler for processing. The handler must clear the interrupt source before it returns or the fast interrupt will simply occur again immediately once reenabled.
To return from the fast interrupt request the handler uses the rfeia (Return From Exception Increment After) instruction which will load the pc and cpsr from the stack of the current mode (SYS or SVC).
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ARMv7 helper functions
[Expand]
function ARMv7GetFPEXC:LongWord; assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetFPSCR:LongWord; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMv7StartMMU; assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetTimerState(Timer:LongWord):LongWord; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMv7SetTimerState(Timer,State:LongWord); assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetTimerCount(Timer:LongWord):Int64; assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetTimerValue(Timer:LongWord):LongWord; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMV7SetTimerValue(Timer,Value:LongWord); assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetTimerCompare(Timer:LongWord):Int64; assembler; nostackframe;
Description: To be documented
[Expand]
procedure ARMV7SetTimerCompare(Timer,High,Low:LongWord);
Description: To be documented
[Expand]
function ARMv7GetTimerFrequency:LongWord; assembler; nostackframe;
Description: To be documented
[Expand]
function ARMv7GetPageTableCoarse(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Coarse Page Table entry (1MB)
[Expand]
function ARMv7SetPageTableCoarse(Address,CoarseAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Coarse Page Table entry (1MB)
| Note
|
See page ???
Caller must call ARMv7InvalidateTLB after changes if MMU is enabled
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[Expand]
function ARMv7GetPageTableLarge(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Large Page Table entry (64KB)
[Expand]
function ARMv7SetPageTableLarge(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Large Page Table entry (64KB)
| Note
|
Large Page Table descriptors must begin on a 16 longword (64 byte) boundary and be repeated for 16 consecutive longwords
See page ???
Caller must call ARMv7InvalidateTLB after changes if MMU is enabled
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[Expand]
function ARMv7GetPageTableSmall(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Small Page Table entry (4KB)
[Expand]
function ARMv7SetPageTableSmall(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Small Page Table entry (4KB)
| Note
|
See page ???
Caller must call ARMv7InvalidateTLB after changes if MMU is enabled
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[Expand]
function ARMv7GetPageTableSection(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Page Table Section (1MB) or Supersection (16MB)/div>
[Expand]
function ARMv7SetPageTableSection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Section (1MB)
| Note
|
See page ???
Caller must call ARMv7InvalidateTLB after changes if MMU is enabled
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[Expand]
function ARMv7SetPageTableSupersection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Supersection (16MB)
| Note
|
Supersection Page Table descriptors must begin on a 16 longword (64 byte) boundary and be repeated for 16 consecutive longwords
See page ???
Caller must call ARMv7InvalidateTLB after changes if MMU is enabled
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Unit Reference
