Difference between revisions of "Unit PlatformARMv6"

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----
 
----
  
−
''To be documented''
+
 
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 page table shift constants''' <code> ARMV6_PAGE_TABLES_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_PAGE_TABLES_SHIFT = 10;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C0 main ID constants''' <code> ARMV6_CP15_C0_MAINID_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_IMPLEMENTOR_MASK = ($FF shl 24);</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_VARIANT_MASK = ($F shl 20);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_ARCHITECTURE_MASK = ($F shl 16);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_PARTNUMBER_MASK = ($FFF shl 4);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_REVISION_MASK = ($F shl 0);</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_IMPLEMENTOR_ARM = ($41 shl 24);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_ARCHITECTURE_CPUID = ($F shl 16);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_MAINID_PARTNUMBER_1176JZSF = ($B76 shl 4);</code>
 +
| &nbsp;
 +
|-
 +
| <code>NAME_</code>
 +
| &nbsp;
 +
|-
 +
| <code>NAME_</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C0 cache type constants''' <code> ARMV6_CP15_C0_CTR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_CTYPE_MASK = ($F shl 25);</code>
 +
| The Cache type bits provide information about the cache architecture (b1110 in the ARM1176JZF-S processor)
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_S = (1 shl 24);</code>
 +
| S = 1, indicates that the processor has separate instruction and data caches and not a unified cache
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DP = (1 shl 23);</code>
 +
| The P, Page, bit indicates restrictions on page allocation for bits [13:12] of the VA For ARM1176JZF-S processors, the P bit is set if the cache size is greater than 16KB.
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_MASK = ($F shl 18);</code>
 +
| The Size field indicates the cache size in conjunction with the M bit
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_128K = (8 shl 18);</code>
 +
| 128KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_64K = (7 shl 18);</code>
 +
| 64KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_32K = (6 shl 18);</code>
 +
| 32KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_16K = (5 shl 18);</code>
 +
| 16KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_8K = (4 shl 18);</code>
 +
| 8KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_4K = (3 shl 18);</code>
 +
| 4KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_2K = (2 shl 18);</code>
 +
| 2KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_1K = (1 shl 18);</code>
 +
| 1KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DSIZE_05K = (0 shl 18);</code>
 +
| 0.5KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DASSOC_MASK = (7 shl 15);</code>
 +
| b010, indicates that the ARM1176JZF-S processor has 4-way associativity
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DM = (1 shl 14);</code>
 +
| Indicates the cache size and cache associativity values in conjunction with the Size and Assoc fields (In the ARM1176JZF-S processor the M bit is set to 0).
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DLEN_MASK = (3 shl 12);</code>
 +
| b10, indicates that ARM1176JZF-S processor has a cache line length of 8 words, that is 32 byte.
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_DLEN_32 = (2 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_IP = (1 shl 11);</code>
 +
| The P, Page, bit indicates restrictions on page allocation for bits [13:12] of the VA For ARM1176JZF-S processors, the P bit is set if the cache size is greater than 16KB.
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_MASK = ($F shl 6);</code>
 +
| The Size field indicates the cache size in conjunction with the M bit
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_128K = (8 shl 6);</code>
 +
| 128KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_64K = (7 shl 6);</code>
 +
| 64KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_32K = (6 shl 6);</code>
 +
| 32KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_16K = (5 shl 6);</code>
 +
| 16KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_8K = (4 shl 6);</code>
 +
| 8KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_4K = (3 shl 6);</code>
 +
| 4KB cache
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_2K = (2 shl 6);</code>
 +
| 2KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_1K = (1 shl 6);</code>
 +
| 1KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ISIZE_05K = (0 shl 6);</code>
 +
| 0.5KB cache, not supported
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_IASSOC_MASK = (7 shl 3);</code>
 +
| b010, indicates that the ARM1176JZF-S processor has 4-way associativity
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_IM = (1 shl 2);</code>
 +
| Indicates the cache size and cache associativity values in conjunction with the Size and Assoc fields (In the ARM1176JZF-S processor the M bit is set to 0).
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ILEN_MASK = (3 shl 0);</code>
 +
| b10, indicates that ARM1176JZF-S processor has a cache line length of 8 words, that is 32 bytes.
 +
|-
 +
| <code>ARMV6_CP15_C0_CTR_ILEN_32 = (2 shl 0);</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C1 control constants''' <code> ARMV6_CP15_C1_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C1_FA_BIT = (1 shl 29);</code>
 +
| Force AP functionality in the MMU is enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_TR_BIT = (1 shl 28);</code>
 +
| TEX remap enabled when set to 1 (TEX[2:1] become page table bits for OS) (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_EE_BIT = (1 shl 25);</code>
 +
| CPSR E bit is set to 1 on an exception when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_VE_BIT = (1 shl 24);</code>
 +
| Interrupt vectors are defined by the VIC interface when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_XP_BIT = (1 shl 23);</code>
 +
| Subpage AP bits disabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_U_BIT = (1 shl 22);</code>
 +
| Unaligned data access support enabled when set to 1 (Default 0). The processor permits unaligned loads and stores and support for mixed endian data is enabled.
 +
|-
 +
| <code>ARMV6_CP15_C1_FI_BIT = (1 shl 21);</code>
 +
| Low interrupt latency configuration enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_L4_BIT = (1 shl 15);</code>
 +
| Loads to PC do not set the T bit when set to 1 (ARMv4 behavior) (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_RR_BIT = (1 shl 14);</code>
 +
| Predictable cache replacement strategy by round-robin replacement when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_V_BIT = (1 shl 13);</code>
 +
| High exception vectors selected when set to 1, address range = 0xFFFF0000-0xFFFF001C (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_I_BIT = (1 shl 12);</code>
 +
| L1 Instruction Cache enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_Z_BIT = (1 shl 11);</code>
 +
| Branch prediction enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_B_BIT = (1 shl 7);</code>
 +
| Big-endian word-invariant memory system when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_C_BIT = (1 shl 2);</code>
 +
| L1 Data cache enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_A_BIT = (1 shl 1);</code>
 +
| Strict alignment fault checking enabled when set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C1_M_BIT = (1 shl 0);</code>
 +
| MMU enabled when set to 1 (Default 0)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C1 auxiliary control constants''' <code> ARMV6_CP15_C1_AUX_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C1_AUX_CZ = (1  shl 6);</code>
 +
| Controls the restriction of cache size to 16KB
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C1 coprocessor access control constants''' <code> ARMV6_CP15_C1_CP* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C1_CP0_NONE = (0 shl 0);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP0_SYS = (1 shl 0);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP0_USER = (3 shl 0);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP1_NONE = (0 shl 2);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP1_SYS = (1 shl 2);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP1_USER = (3 shl 2);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP2_NONE = (0 shl 4);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP2_SYS = (1 shl 4);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP2_USER = (3 shl 4);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP3_NONE = (0 shl 6);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP3_SYS = (1 shl 6);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP3_USER = (3 shl 6);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP4_NONE = (0 shl 8);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP4_SYS = (1 shl 8);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP4_USER = (3 shl 8);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP5_NONE = (0 shl 10);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP5_SYS = (1 shl 10);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP5_USER = (3 shl 10);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP6_NONE = (0 shl 12);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP6_SYS = (1 shl 12);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP6_USER = (3 shl 12);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP7_NONE = (0 shl 14);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP7_SYS = (1 shl 14);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP7_USER = (3 shl 14);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP8_NONE = (0 shl 16);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP8_SYS = (1 shl 16);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP8_USER = (3 shl 16);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP9_NONE = (0 shl 18);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP9_SYS  = (1 shl 18);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP9_USER = (3 shl 18);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP10_NONE = (0 shl 20);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP10_SYS = (1 shl 20);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP10_USER = (3 shl 20);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP11_NONE = (0 shl 22);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP11_SYS = (1 shl 22);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP11_USER = (3 shl 22);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP12_NONE = (0 shl 24);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP12_SYS = (1 shl 24);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP12_USER = (3 shl 24);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C1_CP13_NONE = (0 shl 26);</code>
 +
| Access denied (Default)
 +
|-
 +
| <code>ARMV6_CP15_C1_CP13_SYS = (1 shl 26);</code>
 +
| Privileged mode access only
 +
|-
 +
| <code>ARMV6_CP15_C1_CP13_USER = (3 shl 26);</code>
 +
| Privileged and User mode access
 +
|-
 +
|colspan="2"|''Coprocessors CP14 (Debug Control) and CP15 (System Control) are not affected by the Coprocessor Access Control Register''
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C2 translation table base constants''' <code> ARMV6_CP15_C2_TTBR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_BASE_MASK = $FFFFC000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_RGN_OUTER_NONCACHED = (0 shl 3);</code>
 +
| Outer Noncacheable (Default)
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_RGN_OUTER_WRITE_ALLOCATE = (1 shl 3);</code>
 +
| Outer Write-back, Write Allocate
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_RGN_OUTER_WRITE_THROUGH = (2 shl 3);</code>
 +
| Outer Write-through, No Allocate on Write
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_RGN_OUTER_WRITE_BACK = (3 shl 3);</code>
 +
| Outer Write-back, No Allocate on Write
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_P = (1 shl 2);</code>
 +
| If the processor supports ECC, it indicates to the memory controller it is enabled or disabled. For ARM1176JZF-S processors this is 0.
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_S = (1 shl 1);</code>
 +
| Indicates the page table walk is to Shared memory if set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_CP15_C2_TTBR_C_INNER_CACHED = (1 shl 0);</code>
 +
| Indicates the page table walk is Inner Cacheable if set to 1 (Default 0)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 CP15 C3 domain access control constants''' <code> ARMV6_CP15_C3_DOMAIN* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN0_NONE = (0 shl 0);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN0_CLIENT = (1 shl 0);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN0_MANAGER = (3 shl 0);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN1_NONE = (0 shl 2);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN1_CLIENT = (1 shl 2);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN1_MANAGER = (3 shl 2);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN2_NONE = (0 shl 4);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN2_CLIENT = (1 shl 4);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN2_MANAGER = (3 shl 4);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN3_NONE = (0 shl 6);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN3_CLIENT = (1 shl 6);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN3_MANAGER = (3 shl 6);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN4_NONE = (0 shl 8);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN4_CLIENT = (1 shl 8);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN4_MANAGER = (3 shl 8);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN5_NONE = (0 shl 10);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN5_CLIENT = (1 shl 10);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN5_MANAGER = (3 shl 10);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN6_NONE = (0 shl 12);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN6_CLIENT = (1 shl 12);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN6_MANAGER = (3 shl 12);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN7_NONE = (0 shl 14);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN7_CLIENT = (1 shl 14);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN7_MANAGER = (3 shl 14);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN8_NONE = (0 shl 16);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN8_CLIENT = (1 shl 16);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN8_MANAGER = (3 shl 16);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN9_NONE = (0 shl 18);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN9_CLIENT = (1 shl 18);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN9_MANAGER = (3 shl 18);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN10_NONE = (0 shl 20);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN10_CLIENT = (1 shl 20);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN10_MANAGER = (3 shl 20);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN11_NONE = (0 shl 22);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN11_CLIENT = (1 shl 22);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN11_MANAGER = (3 shl 22);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN12_NONE = (0 shl 24);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN12_CLIENT = (1 shl 24);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN12_MANAGER = (3 shl 24);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
| <code>|colspan="2"|&nbsp;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN13_NONE = (0 shl 26);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN13_CLIENT = (1 shl 26);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN13_MANAGER = (3 shl 26);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN14_NONE = (0 shl 28);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN14_CLIENT = (1 shl 28);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN14_MANAGER = (3 shl 28);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN15_NONE = (0 shl 30);</code>
 +
| No access, Any access generates a domain fault (Default)
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN15_CLIENT = (1 shl 30);</code>
 +
| Client, Accesses are checked against the access permission bits in the TLB entry
 +
|-
 +
| <code>ARMV6_CP15_C3_DOMAIN15_MANAGER = (3 shl 30);</code>
 +
| Manager, Accesses are not checked against the access permission bits in the TLB entry, so a permission fault cannot be generated
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 floating-point exception constants''' <code> ARMV6_FPEXC_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_FPEXC_EN = (1 shl 30);</code>
 +
| Floating-point system is enabled and operates normally if set to 1 (Default 0)
 +
|-
 +
| <code>ARMV6_FPEXC_EX = (1 shl 31);</code>
 +
| If EX is set to 0 then only FPSCR and FPEXC need to be preseved on a context switch (Default 0)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor type constants ''' <code> ARMV6_L1D_TYPE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-36 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|These formats assume that the XP bit in the C1 control register is set to one to enable the ARMv6 format Page Tables
 +
|-
 +
|colspan="2"|See page 6-39 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|Level One Page Table contains 4096 32bit (4 byte) entries for a total size of 16KB
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_TYPE_COARSE = 1;</code>
 +
| The entry points to a 1MB second-level page table. See page 6-40.
 +
|-
 +
| <code>ARMV6_L1D_TYPE_SECTION = 2;</code>
 +
| The entry points to a either a 1MB Section of memory or a 16MB Supersection of memory
 +
|-
 +
| <code>ARMV6_L1D_TYPE_SUPERSECTION = 2;</code>
 +
| Bit[18] of the descriptor selects between a Section and a Supersection
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor flag constants''' <code> ARMV6_L1D_FLAG_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-39 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_FLAG_COARSE_NS = (1 shl 3);</code>
 +
| NS (Non Secure) Attribute bit to enable the support of TrustZone
 +
|-
 +
| <code>ARMV6_L1D_FLAG_SECTION_NS = (1 shl 19);</code>
 +
| NS (Non Secure) Attribute bit to enable the support of TrustZone
 +
|-
 +
| <code>ARMV6_L1D_FLAG_SUPERSECTION = (1 shl 18);</code>
 +
| The descriptor is a 16MB Supersection instead of a 1MB Section (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_FLAG_NOT_GLOBAL = (1 shl 17);</code>
 +
| The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1) (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_FLAG_SHARED = (1 shl 16);</code>
 +
| The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions.
 +
<br />Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits (Section Only).
 +
|-
 +
| <code>ARMV6_L1D_FLAG_APX = (1 shl 15);</code>
 +
| The access permissions extension (APX) bit, provides an extra access permission bit (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_FLAG_P = (1 shl 9);</code>
 +
| If the P bit is supported and set for the memory region, it indicates to the system memory controller that this memory region has ECC enabled. ARM1176JZF-S processors do not support the P bit.
 +
|-
 +
| <code>ARMV6_L1D_FLAG_XN = (1 shl 4);</code>
 +
| The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1) (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_FLAG_C = (1 shl 3);</code>
 +
| Cacheable (C) bit (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_FLAG_B = (1 shl 2);</code>
 +
| Bufferable (B) bit (Section Only)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor masks ''' <code> ARMV6_L1D_*_MASK </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-39 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_COARSE_BASE_MASK = $FFFFFC00;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_SECTION_BASE_MASK = $FFF00000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_SUPERSECTION_BASE_MASK = $FF000000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_DOMAIN_MASK = ($F shl 5);</code>
 +
| Security Domain of the Descriptor
 +
|-
 +
| <code>ARMV6_L1D_TEX_MASK = (7 shl 12);</code>
 +
| Type extension field bits (Section Only)
 +
|-
 +
| <code>ARMV6_L1D_AP_MASK = (3 shl 10);</code>
 +
| Access permission bits (Section Only)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor TEX value constants''' <code> ARMV6_L1D_TEX* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual (Section Only)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_TEX0 = (0 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_TEX1 = (1 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_TEX2 = (2 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_TEX4 = (4 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L1D_TEX5 = (5 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L1D_TEX6 = (6 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L1D_TEX7 = (7 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor AP value constants''' <code> ARMV6_L1D_AP* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-12 of the ARM1176JZF-S Technical Reference Manual (Section Only)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_AP0 = (0 shl 10);</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_AP1 = (1 shl 10); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_AP2 = (2 shl 10); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L1D_AP3 = (3 shl 10);</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor permission value constants''' <code> ARMV6_L1D_ACCESS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-12 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|This is not the full set of permissions as Ultibo always runs in priviledged mode
 +
|-
 +
|colspan="2"|The XN bit can also be applied to control whether memory regions are executable or not
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_ACCESS_NONE = ARMV6_L1D_AP0;</code>
 +
| No Access for both Privileged and Unprivileged code
 +
|-
 +
| <code>ARMV6_L1D_ACCESS_READONLY = ARMV6_L1D_FLAG_APX or ARMV6_L1D_AP3;</code>
 +
| Read-Only for both Privileged and Unprivileged code
 +
|-
 +
| <code>ARMV6_L1D_ACCESS_READWRITE = ARMV6_L1D_AP3;</code>
 +
| Read-Write for both Privileged and Unprivileged code
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level one descriptor cache value constants''' <code> ARMV6_L1D_CACHE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L1D_CACHE_STRONGLY_ORDERED = ARMV6_L1D_TEX0;</code>
 +
| Strongly Ordered. (Always Shared)
 +
|-
 +
| <code>ARMV6_L1D_CACHE_SHARED_DEVICE = ARMV6_L1D_TEX0 or ARMV6_L1D_FLAG_B;</code>
 +
| Device. (Always Shared)
 +
|-
 +
| <code>ARMV6_L1D_CACHE_NORMAL_WRITE_THROUGH = ARMV6_L1D_TEX0 or ARMV6_L1D_FLAG_C;</code>
 +
| Normal. Write Through (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L1D_CACHE_NORMAL_WRITE_BACK = ARMV6_L1D_TEX0 or ARMV6_L1D_FLAG_C or ARMV6_L1D_FLAG_B;</code>
 +
| Normal. Write Back (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L1D_CACHE_NORMAL_NONCACHED = ARMV6_L1D_TEX1;</code>
 +
| Normal. Noncacheable (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L1D_CACHE_NONSHARED_DEVICE = ARMV6_L1D_TEX2;</code>
 +
| Device. (Not Shared)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor type constants''' <code> ARMV6_L2D_TYPE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-40 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|Level Two Page Table contains 256 32bit (4 byte) entries for a total size of 1KB
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_TYPE_LARGE = 1;</code>
 +
| The entry points to a 64KB Large page in memory
 +
|-
 +
| <code>ARMV6_L2D_TYPE_SMALL = 2;</code>
 +
| The entry points to a 4KB Extended small page in memory. Bit[0] of the entry is the XN (Execute Never) bit for the entry.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor flag constants''' <code> ARMV6_L2D_FLAG_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-40 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_FLAG_LARGE_XN = (1 shl 15);</code>
 +
| The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1)
 +
|-
 +
| <code>ARMV6_L2D_FLAG_SMALL_XN = (1 shl 0);</code>
 +
| The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable(1)
 +
|-
 +
| <code>ARMV6_L2D_FLAG_NOT_GLOBAL = (1 shl 11);</code>
 +
| The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1)
 +
|-
 +
| <code>ARMV6_L2D_FLAG_SHARED = (1 shl 10);</code>
 +
| The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions.
 +
<br />Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits
 +
|-
 +
| <code>ARMV6_L2D_FLAG_APX = (1 shl 9);</code>
 +
| The access permissions extension (APX) bit, provides an extra access permission bit.
 +
|-
 +
| <code>ARMV6_L2D_FLAG_C = (1 shl 3);</code>
 +
| Cacheable (C) bit
 +
|-
 +
| <code>ARMV6_L2D_FLAG_B = (1 shl 2);</code>
 +
| Bufferable (B) bit
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor mask constants''' <code> ARMV6_L2D_*_MASK </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-40 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_BASE_MASK = $FFFF0000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_BASE_MASK = $FFFFF000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX_MASK = (7 shl 12);</code>
 +
| Type extension field bits
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX_MASK = (7 shl 6);</code>
 +
| Type extension field bits
 +
|-
 +
| <code>ARMV6_L2D_AP_MASK = (3 shl 4);</code>
 +
| Access permission bits
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor large TEX value constants''' <code> ARMV6_L2D_LARGE_TEX* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX0 = (0 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX1 = (1 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX2 = (2 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX4 = (4 shl 12);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX5 = (5 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX6 = (6 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L2D_LARGE_TEX7 = (7 shl 12);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor small TEX value constants''' <code> ARMV6_L2D_SMALL_TEX* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX0 = (0 shl 6);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX1 = (1 shl 6); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX2 = (2 shl 6);</code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX4 = (4 shl 6); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX5 = (5 shl 6);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX6 = (6 shl 6);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
| <code>ARMV6_L2D_SMALL_TEX7 = (7 shl 6);</code>
 +
| Only used for Cacheable memory values
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor AP value constants ''' <code> ARMV6_L2D_AP* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-12 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_AP0 = (0 shl 4);</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_AP1 = (1 shl 4); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_AP2 = (2 shl 4); </code>
 +
| &nbsp;
 +
|-
 +
| <code>ARMV6_L2D_AP3 = (3 shl 4);</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor permission value constants''' <code> ARMV6_L2D_ACCESS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-12 of the ARM1176JZF-S Technical Reference Manual)
 +
|-
 +
|colspan="2"|This is not the full set of permissions as Ultibo always runs in priviledged mode
 +
|-
 +
|colspan="2"|The XN bit can also be applied to control whether memory regions are executable or not
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_ACCESS_NONE = ARMV6_L2D_AP0;</code>
 +
| No Access for both Privileged and Unprivileged code
 +
|-
 +
| <code>ARMV6_L2D_ACCESS_READONLY = ARMV6_L2D_FLAG_APX or ARMV6_L2D_AP3;</code>
 +
| Read-Only for both Privileged and Unprivileged code
 +
|-
 +
| <code>ARMV6_L2D_ACCESS_READWRITE = ARMV6_L2D_AP3;</code>
 +
| Read-Write for both Privileged and Unprivileged code
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor large cache value constants ''' <code> ARMV6_L2D_LARGE_CACHE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_STRONGLY_ORDERED = ARMV6_L2D_LARGE_TEX0;</code>
 +
| Strongly Ordered. (Always Shared)
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_SHARED_DEVICE = ARMV6_L2D_LARGE_TEX0 or ARMV6_L2D_FLAG_B;</code>
 +
| Device. (Always Shared)
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_NORMAL_WRITE_THROUGH = ARMV6_L2D_LARGE_TEX0 or ARMV6_L2D_FLAG_C;</code>
 +
| Normal. Write Through (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_NORMAL_WRITE_BACK = ARMV6_L2D_LARGE_TEX0 or ARMV6_L2D_FLAG_C or ARMV6_L2D_FLAG_B;</code>
 +
| Normal. Write Back (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_NORMAL_NONCACHED = ARMV6_L2D_LARGE_TEX1;</code>
 +
| Normal. Noncacheable (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_LARGE_CACHE_NONSHARED_DEVICE = ARMV6_L2D_LARGE_TEX2;</code>
 +
| Device. (Not Shared)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 level two descriptor small cache value constants''' <code> ARMV6_L2D_SMALL_CACHE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See page 6-15 of the ARM1176JZF-S Technical Reference Manual
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_STRONGLY_ORDERED = ARMV6_L2D_SMALL_TEX0;</code>
 +
| Strongly Ordered. (Always Shared)
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_SHARED_DEVICE = ARMV6_L2D_SMALL_TEX0 or ARMV6_L2D_FLAG_B;</code>
 +
| Device. (Always Shared)
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_NORMAL_WRITE_THROUGH = ARMV6_L2D_SMALL_TEX0 or ARMV6_L2D_FLAG_C;</code>
 +
| Normal. Write Through (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_NORMAL_WRITE_BACK = ARMV6_L2D_SMALL_TEX0 or ARMV6_L2D_FLAG_C or ARMV6_L2D_FLAG_B;</code>
 +
| Normal. Write Back (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_NORMAL_NONCACHED = ARMV6_L2D_SMALL_TEX1;</code>
 +
| Normal. Noncacheable (Shared if S bit set)
 +
|-
 +
| <code>ARMV6_L2D_SMALL_CACHE_NONSHARED_DEVICE = ARMV6_L2D_SMALL_TEX2;</code>
 +
| Device. (Not Shared)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''ARMv6 specific constants''' <code> ARMV6_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>ARMV6_CONTEXT_LENGTH = 50;</code>
 +
| Length of ARM context switch record in 32 bit words (includes fpexc, fpscr, d0-d15, r0-r12, lr, pc, cpsr)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
  
 
=== Type definitions ===
 
=== Type definitions ===

Revision as of 00:19, 15 December 2016

Return to Unit Reference


Description

The ARMv6 (ARM11) does not support WFI, WFE, DMB, DSB or ISB instructions, these must be done using MCR operations on the system control processor registers.

The ARMv6 supports the LDREX/STREX instructions for syncronisation (Lock/Mutex/Semaphore etc) but only if the MMU is enabled.

Constants


[Expand]
ARMv6 page table shift constants ARMV6_PAGE_TABLES_*


[Expand]
ARMv6 CP15 C0 main ID constants ARMV6_CP15_C0_MAINID_*


[Expand]
ARMv6 CP15 C0 cache type constants ARMV6_CP15_C0_CTR_*


[Expand]
ARMv6 CP15 C1 control constants ARMV6_CP15_C1_*


[Expand]
ARMv6 CP15 C1 auxiliary control constants ARMV6_CP15_C1_AUX_*


[Expand]
ARMv6 CP15 C1 coprocessor access control constants ARMV6_CP15_C1_CP*


[Expand]
ARMv6 CP15 C2 translation table base constants ARMV6_CP15_C2_TTBR_*


[Expand]
ARMv6 CP15 C3 domain access control constants ARMV6_CP15_C3_DOMAIN*


[Expand]
ARMv6 floating-point exception constants ARMV6_FPEXC_*


[Expand]
ARMv6 level one descriptor type constants ARMV6_L1D_TYPE_*


[Expand]
ARMv6 level one descriptor flag constants ARMV6_L1D_FLAG_*


[Expand]
ARMv6 level one descriptor masks ARMV6_L1D_*_MASK


[Expand]
ARMv6 level one descriptor TEX value constants ARMV6_L1D_TEX*


[Expand]
ARMv6 level one descriptor AP value constants ARMV6_L1D_AP*


[Expand]
ARMv6 level one descriptor permission value constants ARMV6_L1D_ACCESS_*


[Expand]
ARMv6 level one descriptor cache value constants ARMV6_L1D_CACHE_*


[Expand]
ARMv6 level two descriptor type constants ARMV6_L2D_TYPE_*


[Expand]
ARMv6 level two descriptor flag constants ARMV6_L2D_FLAG_*


[Expand]
ARMv6 level two descriptor mask constants ARMV6_L2D_*_MASK


[Expand]
ARMv6 level two descriptor large TEX value constants ARMV6_L2D_LARGE_TEX*


[Expand]
ARMv6 level two descriptor small TEX value constants ARMV6_L2D_SMALL_TEX*


[Expand]
ARMv6 level two descriptor AP value constants ARMV6_L2D_AP*


[Expand]
ARMv6 level two descriptor permission value constants ARMV6_L2D_ACCESS_*


[Expand]
ARMv6 level two descriptor large cache value constants ARMV6_L2D_LARGE_CACHE_*


[Expand]
ARMv6 level two descriptor small cache value constants ARMV6_L2D_SMALL_CACHE_*


[Expand]
ARMv6 specific constants ARMV6_*


Type definitions

To be documented

Public variables

To be documented

Function declarations


Initialization functions

[Expand] 
procedure ARMv6Init;
Description: To be documented


ARMv6 platform functions

[Expand] 
procedure ARMv6CPUInit; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6FPUInit; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6MMUInit;
Description: To be documented


[Expand] 
procedure ARMv6CacheInit; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6PageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU


[Expand] 
procedure ARMv6SystemCall(Number:LongWord; Param1,Param2,Param3:PtrUInt); assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6CPUGetMode:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6CPUGetState:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6CPUGetMainID:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6CPUGetModel:LongWord;
Description: To be documented


[Expand] 
function ARMv6CPUGetRevision:LongWord;
Description: To be documented


[Expand] 
function ARMv6CPUGetDescription:String;
Description: To be documented


[Expand] 
function ARMv6FPUGetState:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6L1CacheGetType:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6L1DataCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6L1DataCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6L1InstructionCacheGetSize:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6L1InstructionCacheGetLineSize:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6Halt; assembler; nostackframe; public name'_haltproc';
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


[Expand] 
procedure ARMv6Pause; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


[Expand] 
procedure ARMv6WaitForEvent; assembler; nostackframe;
Description: Wait For Event not available in ARMv6, do a Wait For Interrupt instead


[Expand] 
procedure ARMv6WaitForInterrupt; assembler; nostackframe;
Description: The purpose of the Wait For Interrupt operation is to put the processor in to a low power state


[Expand] 
procedure ARMv6DataMemoryBarrier; assembler; nostackframe;
Description: Perform a data memory barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15


[Expand] 
procedure ARMv6DataSynchronizationBarrier; assembler; nostackframe;
Description: Perform a data synchronization barrier operation using the c7 (Cache Operations) register of system control coprocessor CP15


[Expand] 
procedure ARMv6InstructionMemoryBarrier; assembler; nostackframe;
Description: Perform a Flush Prefetch Buffer operation


[Expand] 
procedure ARMv6InvalidateTLB; assembler; nostackframe;
Description: Perform an invalidate entire TLB (Unlocked/Unified) operation using the c8 (TLB Operations) register of system control coprocessor CP15


[Expand] 
procedure ARMv6InvalidateDataTLB; assembler; nostackframe;
Description: Perform an invalidate data TLB (Unlocked/Data) operation using the c8 (TLB Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateInstructionTLB; assembler; nostackframe;
Description: Perform an invalidate instruction TLB (Unlocked/Instruction) operation using the c8 (TLB Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateCache; assembler; nostackframe;
Description: Perform an invalidate both caches operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanDataCache; assembler; nostackframe;
Description: Perform a clean entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateDataCache; assembler; nostackframe;
Description: Perform an invalidate entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanAndInvalidateDataCache; assembler; nostackframe;
Description: Perform a clean and invalidate entire data cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6InvalidateInstructionCache; assembler; nostackframe;
Description: Perform an invalidate entire instruction cache operation using the c7 (Cache Operations) register of system control coprocessor CP15


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procedure ARMv6CleanDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform a clean data cache range operation


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procedure ARMv6InvalidateDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate data cache range operation


[Expand] 
procedure ARMv6CleanAndInvalidateDataCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform a clean and invalidate data cache range operation


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procedure ARMv6InvalidateInstructionCacheRange(Address,Size:LongWord); assembler; nostackframe;
Description: Perform an invalidate instruction cache range operation


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procedure ARMv6FlushPrefetchBuffer; assembler; nostackframe;
Description: Perform a Flush Prefetch Buffer operation


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procedure ARMv6FlushBranchTargetCache; assembler; nostackframe;
Description: Perform a Flush Entire Branch Target Cache


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procedure ARMv6ContextSwitch(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a thread yielding, sleeping or waiting


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procedure ARMv6ContextSwitchIRQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of an interrupt request (IRQ)


[Expand] 
procedure ARMv6ContextSwitchFIQ(OldStack,NewStack:Pointer; NewThread:TThreadHandle); assembler; nostackframe;
Description: Perform a context switch from one thread to another as a result of a fast interrupt request (FIQ)


[Expand] 
procedure ARMv6ContextSwitchSWI(OldStack,NewStack:Pointer; NewThread:TThreadHandle);
Description: Perform a context switch from one thread to another as a result of a software interrupt (SWI)


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function ARMv6InterlockedOr(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic OR operation using LDREX/STREX


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function ARMv6InterlockedXor(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic XOR operation using LDREX/STREX


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function ARMv6InterlockedAnd(var Target:LongInt; Value:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic AND operation using LDREX/STREX


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function ARMv6InterlockedDecrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic decrement operation using LDREX/STREX


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function ARMv6InterlockedIncrement(var Target:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic increment operation using LDREX/STREX


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function ARMv6InterlockedExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic exchange operation using LDREX/STREX


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function ARMv6InterlockedAddExchange(var Target:LongInt; Source:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic add and exchange operation using LDREX/STREX


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function ARMv6InterlockedCompareExchange(var Target:LongInt; Source,Compare:LongInt):LongInt; assembler; nostackframe;
Description: Perform an atomic compare and exchange operation using LDREX/STREX


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function ARMv6PageTableGetEntry(Address:PtrUInt):TPageTableEntry;
Description: Get and Decode the entry in the Page Table that corresponds to the supplied virtual address


[Expand] 
function ARMv6PageTableSetEntry(const Entry:TPageTableEntry):LongWord;
Description: Encode and Set an entry in the Page Table that corresponds to the supplied virtual address


[Expand] 
function ARMv6VectorTableGetEntry(Number:LongWord):PtrUInt;
Description: Return the address of the specified vector table entry number


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function ARMv6VectorTableSetEntry(Number:LongWord; Address:PtrUInt):LongWord;
Description: Set the supplied address as the value of the specified vector table entry number


[Expand] 
function ARMv6FirstBitSet(Value:LongWord):LongWord; assembler; nostackframe;
Description: To be documented


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function ARMv6CountLeadingZeros(Value:LongWord):LongWord; assembler; nostackframe;
Description: Equivalent of the GCC Builtin function __builtin_clz


ARMv6 thread functions

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procedure ARMv6PrimaryInit; assembler; nostackframe;
Description: To be documented


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function ARMv6SpinLock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry


[Expand] 
function ARMv6SpinUnlock(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry


[Expand] 
function ARMv6SpinLockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and save the previous IRQ state


[Expand] 
function ARMv6SpinUnlockIRQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ state


[Expand] 
function ARMv6SpinLockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable FIQ and save the previous FIQ state


[Expand] 
function ARMv6SpinUnlockFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous FIQ state


[Expand] 
function ARMv6SpinLockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Spin entry, disable IRQ and FIQ and save the previous IRQ/FIQ state


[Expand] 
function ARMv6SpinUnlockIRQFIQ(Spin:PSpinEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Spin entry and restore the previous IRQ/FIQ state


[Expand] 
function ARMv6SpinCheckIRQ(Spin:PSpinEntry):Boolean;
Description: To be documented


[Expand] 
function ARMv6SpinCheckFIQ(Spin:PSpinEntry):Boolean;
Description: To be documented


[Expand] 
function ARMv6SpinExchangeIRQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented


[Expand] 
function ARMv6SpinExchangeFIQ(Spin1,Spin2:PSpinEntry):LongWord;
Description: To be documented


[Expand] 
function ARMv6MutexLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Lock an existing Mutex entry


[Expand] 
function ARMv6MutexUnlock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Unlock an existing Mutex entry


[Expand] 
function ARMv6MutexTryLock(Mutex:PMutexEntry):LongWord; assembler; nostackframe;
Description: Try to lock an existing Mutex entry


[Expand] 
function ARMv6ThreadGetCurrent:TThreadHandle; assembler; nostackframe;
Description: Get the current thread id from the c13 (Thread and process ID) register of system control coprocessor CP15


[Expand] 
function ARMv6ThreadSetCurrent(Thread:TThreadHandle):LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6ThreadSetupStack(StackBase:Pointer; StartProc:TThreadStart; ReturnProc:TThreadEnd; Parameter:Pointer):Pointer;
Description: Set up the context record and arguments on the stack for a new thread


ARMv6 IRQ functions

[Expand] 
function ARMv6DispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented


ARMv6 FIQ functions

[Expand] 
function ARMv6DispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle; inline;
Description: To be documented


ARMv6 SWI functions

[Expand] 
function ARMv6DispatchSWI(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle; inline;
Description: To be documented


ARMv6 interrupt functions

[Expand] 
procedure ARMv6ResetHandler; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6UndefinedInstructionHandler; assembler; nostackframe;
Description: Handle an undefined instruction exception


[Expand] 
procedure ARMv6SoftwareInterruptHandler; assembler; nostackframe;
Description: Handle a software interrupt (SWI) from a system call (SVC)


[Expand] 
procedure ARMv6PrefetchAbortHandler; assembler; nostackframe;
Description: Handle a prefetch abort exception


[Expand] 
procedure ARMv6DataAbortHandler; assembler; nostackframe;
Description: Handle a data abort exception


[Expand] 
procedure ARMv6ReservedHandler; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6IRQHandler; assembler; nostackframe;
Description: Handle an interrupt request IRQ from an interrupt source


[Expand] 
procedure ARMv6FIQHandler; assembler; nostackframe;
Description: Handle a fast interrupt request FIQ from an interrupt source


ARMv6 helper functions

[Expand] 
function ARMv6GetFPEXC:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6GetFPSCR:LongWord; assembler; nostackframe;
Description: To be documented


[Expand] 
procedure ARMv6StartMMU; assembler; nostackframe;
Description: To be documented


[Expand] 
function ARMv6GetPageTableCoarse(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Coarse Page Table entry (1MB)


[Expand] 
function ARMv6SetPageTableCoarse(Address,CoarseAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Coarse Page Table entry (1MB)


[Expand] 
function ARMv6GetPageTableLarge(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Large Page Table entry (64KB)


[Expand] 
function ARMv6SetPageTableLarge(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Large Page Table entry (64KB)


[Expand] 
function ARMv6GetPageTableSmall(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Small Page Table entry (4KB)


[Expand] 
function ARMv6SetPageTableSmall(Address,PhysicalAddress:PtrUInt; Flags:Word):Boolean;
Description: Set the descriptor for a Small Page Table entry (4KB)


[Expand] 
function ARMv6GetPageTableSection(Address:PtrUInt):LongWord;
Description: Get the descriptor for a Page Table Section (1MB) or Supersection (16MB)


[Expand] 
function ARMv6SetPageTableSection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Section (1MB)


[Expand] 
function ARMv6SetPageTableSupersection(Address,PhysicalAddress:PtrUInt; Flags:LongWord):Boolean;
Description: Set the descriptor for a Page Table Supersection (16MB)


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