Difference between revisions of "Unit DWCOTG"
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! '''Note''' | ! '''Note''' | ||
| See usb.pas for the documentation of this interface of the Host Controller Driver | | See usb.pas for the documentation of this interface of the Host Controller Driver | ||
− | + | This Host Controller Driver implements this interface asynchronously, as intended. Furthermore, it uses a simplistic scheduling algorithm where it places requests into a single queue and executes them in the order they were submitted. Transfers that need to be retried, including periodic transfers that receive a NAK reply and split transactions that receive a NYET reply when doing the Complete Split transaction, are scheduled to be retried at an appropriate time by separate code that shortcuts the main queue when the timer expires | |
<br />Caller must hold the device lock | <br />Caller must hold the device lock | ||
|- | |- | ||
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! '''Note''' | ! '''Note''' | ||
| See usb.pas for the documentation of thisinterface of the Host Controller Driver | | See usb.pas for the documentation of thisinterface of the Host Controller Driver | ||
− | + | Caller must hold the device lock | |
|- | |- | ||
|} | |} | ||
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|- | |- | ||
! '''Note''' | ! '''Note''' | ||
− | | For periodic transfers (e.g. polling an interrupt endpoint), the exact time at which the transfer must be retried is specified by the bInterval member of the endpoint descriptor. For low and full-speed devices, bInterval specifies the number of millisconds to wait before the next poll, while for high-speed devices it specifies the exponent (plus one) of a power-of-two number of | + | | For periodic transfers (e.g. polling an interrupt endpoint), the exact time at which the transfer must be retried is specified by the bInterval member of the endpoint descriptor. For low and full-speed devices, bInterval specifies the number of millisconds to wait before the next poll, while for high-speed devices it specifies the exponent (plus one) of a power-of-two number of milliseconds to wait before the next poll. |
− | milliseconds to wait before the next poll. | + | <br />To actually implement delaying a transfer, we associate each transfer with a thread created on-demand. Each such thread simply enters a loop where it calls sleep() for the appropriate number of milliseconds, then retries the transfer. A semaphore is needed to make the thread do nothing until the request has actually been resubmitted. |
− | <br />To actually implement delaying a transfer, we associate each transfer with a thread created on-demand. | + | |
<br />This code gets used to scheduling polling of IN interrupt endpoints, including those on hubs and HID devices. Thus, polling of these devices for status changes (in the case of hubs) or new input (in the case of HID devices) is done in software. This wakes up the CPU a lot and wastes time and energy. But with USB 2.0, there is no way around this, other than by suspending the USB device which we don't support. | <br />This code gets used to scheduling polling of IN interrupt endpoints, including those on hubs and HID devices. Thus, polling of these devices for status changes (in the case of hubs) or new input (in the case of HID devices) is done in software. This wakes up the CPU a lot and wastes time and energy. But with USB 2.0, there is no way around this, other than by suspending the USB device which we don't support. | ||
|- | |- | ||
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! '''Note''' | ! '''Note''' | ||
| The DWC contains several levels of interrupt registers, detailed in the following list. Note that for each level, each bit of the "interrupt" register contains the state of a pending interrupt (1 means interrupt pending; write 1 to clear), while the "interrupt mask" register has the same format but is used to turn the corresponding interrupt on or off (1 means on; write 1 to turn on; write 0 to turn off). | | The DWC contains several levels of interrupt registers, detailed in the following list. Note that for each level, each bit of the "interrupt" register contains the state of a pending interrupt (1 means interrupt pending; write 1 to clear), while the "interrupt mask" register has the same format but is used to turn the corresponding interrupt on or off (1 means on; write 1 to turn on; write 0 to turn off). | ||
− | + | - The AHB configuration register contains a mask bit used to enable/disable all interrupts whatsoever from the DWC hardware. | |
<br />- The "Core" interrupt and interrupt mask registers control top-level interrupts. For example, a single bit in these registers corresponds to all channel interrupts. | <br />- The "Core" interrupt and interrupt mask registers control top-level interrupts. For example, a single bit in these registers corresponds to all channel interrupts. | ||
<br />- The "Host All Channels" interrupt and interrupt mask registers control all interrupts on each channel. | <br />- The "Host All Channels" interrupt and interrupt mask registers control all interrupts on each channel. | ||
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! '''Note''' | ! '''Note''' | ||
| Caller must hold the host lock | | Caller must hold the host lock | ||
− | + | Can be called by the interrupt handler | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| Caller must hold the host lock | | Caller must hold the host lock | ||
− | + | Can be called by the interrupt handler | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| Caller must hold the Host lock | | Caller must hold the Host lock | ||
− | + | Can be called by the interrupt handler | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| This thread receives requests that have been submitted and schedules them on the next available channel | | This thread receives requests that have been submitted and schedules them on the next available channel | ||
− | + | This is a very simplistic scheduler that does not take into account bandwidth requirements or which endpoint a transfer is for | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| This thread receives completed requests which have either succeeded or failed and calls the completion handler which will call the registered callback for the request | | This thread receives completed requests which have either succeeded or failed and calls the completion handler which will call the registered callback for the request | ||
− | + | This thread also receives requests that need to be resubmitted and resubmits them for later processing by another thread | |
<br />Message contents are as follows: | <br />Message contents are as follows: | ||
<br />Msg = Request to be completed | <br />Msg = Request to be completed | ||
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! '''Note''' | ! '''Note''' | ||
| An instance of this thread is created for each request that needs to be resubmitted, this thread then either waits for a predetermined number of milliseconds before scheduling the request on the next available channel or waits for a signal from the interrupt handler to indicate a start of frame before scheduling the request on the allocated channel | | An instance of this thread is created for each request that needs to be resubmitted, this thread then either waits for a predetermined number of milliseconds before scheduling the request on the next available channel or waits for a signal from the interrupt handler to indicate a start of frame before scheduling the request on the allocated channel | ||
− | + | Once the request has been resubmitted the thread waits for the semaphore to be signaled again. If the request is a periodic polling of an endpoint then it will be resubmitted continuously at the predetermined interval, otherwise the semaphore will be destroyed by the completion handler and the thread will terminate | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| Only called by DWCInterruptHandler | | Only called by DWCInterruptHandler | ||
− | + | Caller must hold the host lock | |
|- | |- | ||
|} | |} | ||
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! '''Note''' | ! '''Note''' | ||
| Only called by DWCChannelInterrupt | | Only called by DWCChannelInterrupt | ||
− | + | Caller must hold the host lock | |
|- | |- | ||
|} | |} |
Revision as of 05:21, 19 October 2016
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Contents
[hide]Description
This is a USB Host Controller Driver (HCD) that interfaces with the Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller, henceforth abbreviated as "DWC". This is the USB Host Controller used on the BCM2835 SoC used on the Raspberry Pi.
Please note that there is no publicly available official documentation for this particular piece of hardware, and it uses its own custom host controller interface rather than a standard one such as EHCI. Therefore, this driver was written on a best-effort basis using several sources to glean the necessary hardware details, including the extremely complicated and difficult to understand vendor provided Linux driver.
This file implements the Host Controller Driver Interface defined in TUSBHost. Most importantly, it implements a function to power on and start the host controller (HostStart) and a function to send and receive messages over the USB (HostSubmit).
The DWC is controlled by reading and writing to/from memory-mapped registers. The most important registers are the host channel registers. On this particular hardware, a "host channel", or simply "channel", is a set of registers to which software can read and write to cause transactions to take place on the USB. A fixed number of host channels exist, on the Raspberry Pi there are 8. From the software's perspective, transactions using different host channels can be executed at the same time.
Some of the host channel registers, as well as other registers, deal with interrupts. This driver makes heavy use of these and performs all USB transfers in an interrupt-driven manner. However, due to design flaws in this hardware and in USB 2.0 itself, "interrupt" and "isochronous" transfers still need to make use of software polling when checking for new data, even though each individual transfer is itself interrupt-driven. This means that, for example, if your USB mouse specifies a polling rate of 100 times per second, then it will, unfortunately, be polled 100 times per second in software. For more detail about how interrupts can be controlled on this particular hardware, see the comment above DWCSetupInterrupts. Another important concept is the idea of "packets", "transactions", and "transfers". A USB transfer, such as a single control message or bulk request, may need to be split into multiple packets if it exceeds the endpoint's maximum packet size. Unfortunately, this has to be dealt with explicitly in this code, as this hardware doesn't do it for us. But at least, from the viewpoint of this software, a "transaction" is essentially the same as a "packet".
The "On-The-Go" in the name of this hardware means that it supports the USB On-The-Go protocol, which allows it to act either as a host or a device. However, we only are concerned with it acting as a host, which simplifies our driver.
To simplify the USB core software, a useful design technique (as recommended by the USB 2.0 standard and used in other implementations such as Linux's) is to have the HCD present the root hub as a standard USB hub, even if the root hub is integrated with the host controller and does not appear as a standard hub at the hardware level. This is the case with the DWC, and we implement this design. Therefore, some code in this file deals with faking requests sent to the root hub.
Constants
To be documented
Type definitions
To be documented
Public variables
To be documented
Function declarations
Initialization functions
DWCOTG functions
function DWCHostStart(Host:PUSBHost):LongWord;
function DWCHostStop(Host:PUSBHost):LongWord;
function DWCHostReset(Host:PUSBHost):LongWord;
function DWCHostResetEx(Host:PDWCUSBHost):LongWord;
function DWCHostSubmit(Host:PUSBHost; Request:PUSBRequest):LongWord;
function DWCHostCancel(Host:PUSBHost; Request:PUSBRequest):LongWord;
function DWCHostResubmit(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
function DWCHostPowerOn(Host:PDWCUSBHost):LongWord;
function DWCHostPowerOff(Host:PDWCUSBHost):LongWord;
function DWCHostCheck(Host:PDWCUSBHost):LongWord;
function DWCHostInit(Host:PDWCUSBHost):LongWord;
function DWCHostSetup(Host:PDWCUSBHost):LongWord;
function DWCHostSetupDMA(Host:PDWCUSBHost):LongWord;
function DWCHostSetupInterrupts(Host:PDWCUSBHost):LongWord;
function DWCHostStartFrameInterrupt(Host:PDWCUSBHost; Enable:Boolean):LongWord;
function DWCAllocateChannel(Host:PDWCUSBHost):LongWord;
function DWCReleaseChannel(Host:PDWCUSBHost; Channel:LongWord):LongWord;
function DWCChannelStartTransfer(Host:PDWCUSBHost; Channel:LongWord; Request:PUSBRequest):LongWord;
function DWCChannelStartTransaction(Host:PDWCUSBHost; Channel:LongWord; Request:PUSBRequest):LongWord;
function DWCHostPortReset(Host:PDWCUSBHost):LongWord;
function DWCHostPortPowerOn(Host:PDWCUSBHost):LongWord;
function DWCHostPortGetStatus(Host:PDWCUSBHost):LongWord;
function DWCHostPortSetFeature(Host:PDWCUSBHost; Feature:Word):LongWord;
function DWCHostPortClearFeature(Host:PDWCUSBHost; Feature:Word):LongWord;
procedure DWCHostPortStatusChanged(Host:PDWCUSBHost);
function DWCRootHubRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
function DWCRootHubControlRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
function DWCRootHubClassRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
function DWCRootHubStandardRequest(Host:PDWCUSBHost; Request:PUSBRequest):LongWord;
function DWCSchedulerStart(Host:PDWCUSBHost):LongWord;
function DWCSchedulerExecute(Host:PDWCUSBHost):PtrInt;
function DWCCompletionExecute(Host:PDWCUSBHost):PtrInt;
function DWCResubmitExecute(Request:PUSBRequest):PtrInt;
procedure DWCInterruptHandler(Host:PDWCUSBHost);
function DWCChannelInterrupt(Host:PDWCUSBHost; Channel:LongWord):LongWord;
function DWCChannelCompleted(Host:PDWCUSBHost; Request:PUSBRequest; Channel,Interrupts:LongWord):LongWord;
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