smc91x.h

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/*
 * This file is part of the Ultibo project, https://ultibo.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2026 Garry Wood <garry@softoz.com.au>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef _ULTIBO_SMC91X_H
#define _ULTIBO_SMC91X_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "ultibo/network.h"
#include "ultibo/threads.h"

#define SMC91X_NETWORK_DESCRIPTION  "SMSC 91C9x/91C1xx Ethernet" 
 
#define SMC91X_COMPLETION_THREAD_STACK_SIZE SIZE_128K 
#define SMC91X_COMPLETION_THREAD_PRIORITY   THREAD_PRIORITY_HIGHER 
 
#define SMC91X_COMPLETION_THREAD_NAME   "SMSC 91C9x/91C1xx Completion" 
 
#define SMC91X_COMPLETION_RECEIVE   0 
#define SMC91X_COMPLETION_TRANSMIT  1 
#define SMC91X_COMPLETION_ALLOCATE  2 
#define SMC91X_COMPLETION_TERMINATE 3 
 
#define SMC91X_MAX_TX_ENTRIES   SIZE_16 
#define SMC91X_MAX_RX_ENTRIES   SIZE_256 
 
#define SMC91X_MAX_PACKET_SIZE  2048

#define SMC91X_TCR_ENABLE   0x0001 
#define SMC91X_TCR_LOOP 0x0002 
#define SMC91X_TCR_FORCOL   0x0004 
#define SMC91X_TCR_PAD_EN   0x0080 
#define SMC91X_TCR_NOCRC    0x0100 
#define SMC91X_TCR_MON_CSN  0x0400 
#define SMC91X_TCR_FDUPLX   0x0800 
#define SMC91X_TCR_STP_SQET 0x1000 
#define SMC91X_TCR_EPH_LOOP 0x2000 
#define SMC91X_TCR_SWFDUP   0x8000 

#define SMC91X_TCR_DEFAULT  SMC91X_TCR_ENABLE | SMC91X_TCR_PAD_EN
#define SMC91X_TCR_CLEAR    0

#define SMC91X_EPH_STATUS_TX_SUC    0x0001 
#define SMC91X_EPH_STATUS_SNGL_COL  0x0002 
#define SMC91X_EPH_STATUS_MUL_COL   0x0004 
#define SMC91X_EPH_STATUS_LTX_MULT  0x0008 
#define SMC91X_EPH_STATUS_16COL 0x0010 
#define SMC91X_EPH_STATUS_SQET  0x0020 
#define SMC91X_EPH_STATUS_LTXBRD    0x0040 
#define SMC91X_EPH_STATUS_TXDEFR    0x0080 
#define SMC91X_EPH_STATUS_LATCOL    0x0200 
#define SMC91X_EPH_STATUS_LOSTCARR  0x0400 
#define SMC91X_EPH_STATUS_EXC_DEF   0x0800 
#define SMC91X_EPH_STATUS_CTR_ROL   0x1000 
#define SMC91X_EPH_STATUS_LINK_OK   0x4000 
#define SMC91X_EPH_STATUS_TXUNRN    0x8000 

#define SMC91X_RCR_RX_ABORT 0x0001 
#define SMC91X_RCR_PRMS 0x0002 
#define SMC91X_RCR_ALMUL    0x0004 
#define SMC91X_RCR_RXEN 0x0100 
#define SMC91X_RCR_STRIP_CRC    0x0200 
#define SMC91X_RCR_ABORT_ENB    0x0200 
#define SMC91X_RCR_FILT_CAR 0x0400 
#define SMC91X_RCR_SOFTRST  0x8000 

#define SMC91X_RCR_DEFAULT  SMC91X_RCR_STRIP_CRC | SMC91X_RCR_RXEN
#define SMC91X_RCR_CLEAR    0

#define SMC91X_RPC_SPEED    0x2000 
#define SMC91X_RPC_DPLX 0x1000 
#define SMC91X_RPC_ANEG 0x0800 
#define SMC91X_RPC_LS2A 0x0080 
#define SMC91X_RPC_LS1A 0x0040
#define SMC91X_RPC_LS0A 0x0020
#define SMC91X_RPC_LS2B 0x0010 
#define SMC91X_RPC_LS1B 0x0008
#define SMC91X_RPC_LS0B 0x0004

#define SMC91X_RPC_DEFAULT  SMC91X_RPC_ANEG | SMC91X_RPC_SPEED | SMC91X_RPC_DPLX

#define SMC91X_RPC_LED_100_10   0x00 
#define SMC91X_RPC_LED_RES  0x01 
#define SMC91X_RPC_LED_10   0x02 
#define SMC91X_RPC_LED_FD   0x03 
#define SMC91X_RPC_LED_TX_RX    0x04 
#define SMC91X_RPC_LED_100  0x05 
#define SMC91X_RPC_LED_TX   0x06 
#define SMC91X_RPC_LED_RX   0x07 

#define SMC91X_CONFIG_EXT_PHY   0x0200 
#define SMC91X_CONFIG_GPCNTRL   0x0400 
#define SMC91X_CONFIG_NO_WAIT   0x1000 
#define SMC91X_CONFIG_EPH_POWER_EN  0x8000 
#define SMC91X_CONFIG_RESERVED  0x20B1 

#define SMC91X_CONFIG_DEFAULT   SMC91X_CONFIG_EPH_POWER_EN

#define SMC91X_CTL_RCV_BAD  0x4000 
#define SMC91X_CTL_AUTO_RELEASE 0x0800 
#define SMC91X_CTL_LE_ENABLE    0x0080 
#define SMC91X_CTL_CR_ENABLE    0x0040 
#define SMC91X_CTL_TE_ENABLE    0x0020 
#define SMC91X_CTL_EEPROM_SELECT    0x0004 
#define SMC91X_CTL_RELOAD   0x0002 
#define SMC91X_CTL_STORE    0x0001 

#define SMC91X_MMU_CMD_BUSY 1 
#define SMC91X_MMU_CMD_NOP  (0 << 5) 
#define SMC91X_MMU_CMD_ALLOC    (1 << 5) 
#define SMC91X_MMU_CMD_RESET    (2 << 5) 
#define SMC91X_MMU_CMD_REMOVE   (3 << 5) 
#define SMC91X_MMU_CMD_RELEASE  (4 << 5) 
#define SMC91X_MMU_CMD_FREEPKT  (5 << 5) 
#define SMC91X_MMU_CMD_ENQUEUE  (6 << 5) 
#define SMC91X_MMU_CMD_RSTTXFIFO    (7 << 5) 

#define SMC91X_AR_FAILED    0x80 

#define SMC91X_TXFIFO_TEMPTY    0x80 

#define SMC91X_RXFIFO_REMPTY    0x80 

#define SMC91X_PTR_RCV  0x8000 
#define SMC91X_PTR_AUTOINC  0x4000 
#define SMC91X_PTR_READ 0x2000 

#define SMC91X_IM_MDINT 0x80 
#define SMC91X_IM_ERCV_INT  0x40 
#define SMC91X_IM_EPH_INT   0x20 
#define SMC91X_IM_RX_OVRN_INT   0x10 
#define SMC91X_IM_ALLOC_INT 0x08 
#define SMC91X_IM_TX_EMPTY_INT  0x04 
#define SMC91X_IM_TX_INT    0x02 
#define SMC91X_IM_RCV_INT   0x01 

#define SMC91X_MII_MSK_CRS100   0x4000 
#define SMC91X_MII_MDOE 0x0008 
#define SMC91X_MII_MCLK 0x0004 
#define SMC91X_MII_MDI  0x0002 
#define SMC91X_MII_MDO  0x0001 
 
#define SMC91X_MII_DELAY    1 

#define SMC91X_RCV_RCV_DISCRD   0x0080 
#define SMC91X_RCV_THRESHOLD    0x001F 

#define SMC91X_RCV_ALGNERR  0x8000 
#define SMC91X_RCV_BRODCAST 0x4000 
#define SMC91X_RCV_BADCRC   0x2000 
#define SMC91X_RCV_ODDFRAME 0x1000 
#define SMC91X_RCV_TOOLONG  0x0800 
#define SMC91X_RCV_TOOSHORT 0x0400 
#define SMC91X_RCV_MULTICAST    0x0001 
#define SMC91X_RCV_ERRORS   (SMC91X_RCV_ALGNERR | SMC91X_RCV_BADCRC | SMC91X_RCV_TOOLONG | SMC91X_RCV_TOOSHORT)

#define SMC91X_BANK_SELECT_0    0
#define SMC91X_BANK_SELECT_1    1
#define SMC91X_BANK_SELECT_2    2
#define SMC91X_BANK_SELECT_3    3

#define SMC91X_CHIP_COUNT   16
 
#define SMC91X_CHIP_9192    3
#define SMC91X_CHIP_9194    4
#define SMC91X_CHIP_9195    5
#define SMC91X_CHIP_9196    6
#define SMC91X_CHIP_91100   7
#define SMC91X_CHIP_91100FD 8
#define SMC91X_CHIP_91111FD 9

#define SMC91X_PHY_LAN83C183    0x0016f840 
#define SMC91X_PHY_LAN83C180    0x02821c50






#define SMC91X_PHY_CFG1_REG 0x10
#define SMC91X_PHY_CFG1_LNKDIS  0x8000 
#define SMC91X_PHY_CFG1_XMTDIS  0x4000 
#define SMC91X_PHY_CFG1_XMTPDN  0x2000 
#define SMC91X_PHY_CFG1_BYPSCR  0x0400 
#define SMC91X_PHY_CFG1_UNSCDS  0x0200 
#define SMC91X_PHY_CFG1_EQLZR   0x0100 
#define SMC91X_PHY_CFG1_CABLE   0x0080 
#define SMC91X_PHY_CFG1_RLVL0   0x0040 
#define SMC91X_PHY_CFG1_TLVL_SHIFT  2 
#define SMC91X_PHY_CFG1_TLVL_MASK   0x003C
#define SMC91X_PHY_CFG1_TRF_MASK    0x0003 

#define SMC91X_PHY_CFG2_REG 0x11
#define SMC91X_PHY_CFG2_APOLDIS 0x0020 
#define SMC91X_PHY_CFG2_JABDIS  0x0010 
#define SMC91X_PHY_CFG2_MREG    0x0008 
#define SMC91X_PHY_CFG2_INTMDIO 0x0004 

#define SMC91X_PHY_INT_REG  0x12 
#define SMC91X_PHY_INT_INT  0x8000 
#define SMC91X_PHY_INT_LNKFAIL  0x4000 
#define SMC91X_PHY_INT_LOSSSYNC 0x2000 
#define SMC91X_PHY_INT_CWRD 0x1000 
#define SMC91X_PHY_INT_SSD  0x0800 
#define SMC91X_PHY_INT_ESD  0x0400 
#define SMC91X_PHY_INT_RPOL 0x0200 
#define SMC91X_PHY_INT_JAB  0x0100 
#define SMC91X_PHY_INT_SPDDET   0x0080 
#define SMC91X_PHY_INT_DPLXDET  0x0040 

#define SMC91X_PHY_MASK_REG 0x13 


typedef struct
{
    uint16_t tcr; 
    uint16_t eph_status; 
    uint16_t rcr; 
    uint16_t counter; 
    uint16_t mir; 
    uint16_t rpcr; 
    uint16_t reserved; 
    uint16_t bank; 
} PACKED SMC91X_BANK0_REGISTERS;
 
 
typedef struct
{
    uint16_t config; 
    uint16_t base; 
    uint16_t addr0; 
    uint16_t addr1; 
    uint16_t addr2; 
    uint16_t gp; 
    uint16_t ctl; 
    uint16_t bank; 
} PACKED SMC91X_BANK1_REGISTERS;
 
 
typedef union
{
    uint16_t fifo;
    struct
    {
        uint8_t tx;
        uint8_t rx;
    };
} PACKED SMC91X_FIFO_REGISTERS;
 
 
typedef union
{
    uint32_t data;
    struct
    {
        uint16_t datah;
        uint16_t datal;
    };
    struct
    {
        uint8_t data0;
        uint8_t data1;
        uint8_t data2;
        uint8_t data3;
    };
} PACKED SMC91X_DATA_REGISTERS;
 
 
typedef struct
{
    uint16_t mmu_cmd; 
    uint8_t pn; 
    uint8_t ar; 
    SMC91X_FIFO_REGISTERS fifo; 
    uint16_t ptr; 
    SMC91X_DATA_REGISTERS data; 
    uint8_t int_sts; 
    uint8_t im; 
    uint16_t bank; 
} PACKED SMC91X_BANK2_REGISTERS;
 
 
typedef struct
{
    uint16_t mcast1; 
    uint16_t mcast2; 
    uint16_t mcast3; 
    uint16_t mcast4; 
    uint16_t mii; 
    uint16_t rev; 
    uint16_t rcv; 
    uint16_t bank; 
} PACKED SMC91X_BANK3_REGISTERS;
 
 
typedef union _SMC91X_REGISTERS SMC91X_REGISTERS;
union _SMC91X_REGISTERS
{
    SMC91X_BANK0_REGISTERS bank0; 
    SMC91X_BANK1_REGISTERS bank1; 
    SMC91X_BANK2_REGISTERS bank2; 
    SMC91X_BANK3_REGISTERS bank3; 
} PACKED;
 
 
typedef struct _SMC91X_NETWORK SMC91X_NETWORK;
struct _SMC91X_NETWORK
{
    // Network Properties
    NETWORK_DEVICE network;
    // SMC91X Properties
    uint32_t irq;
    SPIN_HANDLE lock; 
    THREAD_HANDLE thread; 
    uint32_t start; 
    uint32_t count; 
    NETWORK_ENTRY *entries[SMC91X_MAX_RX_ENTRIES]; 
    SMC91X_REGISTERS *registers; 
    uint16_t revision; 
    uint32_t phyid; 
    uint32_t phytype; 
    uint32_t tcrflags; 
    uint32_t rcrflags; 
    uint32_t rpcflags; 
    // Statistics Properties
    uint32_t interruptcount; 
    uint32_t collisioncount; 
};


NETWORK_DEVICE * STDCALL smc91x_network_create(size_t address, char *name, uint32_t irq);

uint32_t STDCALL smc91x_network_destroy(NETWORK_DEVICE *network);
 
#ifdef __cplusplus
}
#endif
 
#endif // _ULTIBO_SMC91X_H