pl011.h

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/*
 * This file is part of the Ultibo project, https://ultibo.org/
 *
 * The MIT License (MIT)
 *
 * Copyright (c) 2026 Garry Wood <garry@softoz.com.au>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#ifndef _ULTIBO_PL011_H
#define _ULTIBO_PL011_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include "ultibo/uart.h"
#include "ultibo/threads.h"
 
#define PL011_UART_RX_BUFFER

#define PL011_UART_DESCRIPTION  "ARM PrimeCell PL011 UART" 
 
#define PL011_UART_MIN_BAUD 300 
#define PL011_UART_MAX_BAUD 1500000 
 
#define PL011_UART_MIN_DATABITS SERIAL_DATA_5BIT
#define PL011_UART_MAX_DATABITS SERIAL_DATA_8BIT
 
#define PL011_UART_MIN_STOPBITS SERIAL_STOP_1BIT
#define PL011_UART_MAX_STOPBITS SERIAL_STOP_2BIT
 
#define PL011_UART_MAX_PARITY   SERIAL_PARITY_EVEN
 
#define PL011_UART_MAX_FLOW SERIAL_FLOW_RTS_CTS
 
#define PL011_UART_CLOCK_RATE   24000000
#ifdef PL011_UART_RX_BUFFER
#define PL011_UART_RX_POLL_LIMIT    256 
#define PL011_UART_RX_BUFFER_SIZE   1024
#endif

#define PL011_UART_DR_OE    (1 << 11) 
#define PL011_UART_DR_BE    (1 << 10) 
#define PL011_UART_DR_PE    (1 << 9) 
#define PL011_UART_DR_FE    (1 << 8) 
#define PL011_UART_DR_DATA  (0xFF << 0) 
#define PL011_UART_DR_ERROR PL011_UART_DR_OE | PL011_UART_DR_BE | PL011_UART_DR_PE | PL011_UART_DR_FE

#define PL011_UART_RSRECR_OE    (1 << 3) 
#define PL011_UART_RSRECR_BE    (1 << 2) 
#define PL011_UART_RSRECR_PE    (1 << 1) 
#define PL011_UART_RSRECR_FE    (1 << 0) 

#define PL011_UART_FR_RI    (1 << 8) 
#define PL011_UART_FR_TXFE  (1 << 7) 
#define PL011_UART_FR_RXFF  (1 << 6) 
#define PL011_UART_FR_TXFF  (1 << 5) 
#define PL011_UART_FR_RXFE  (1 << 4) 
#define PL011_UART_FR_BUSY  (1 << 3) 
#define PL011_UART_FR_DCD   (1 << 2) 
#define PL011_UART_FR_DSR   (1 << 1) 
#define PL011_UART_FR_CTS   (1 << 0) 


#define PL011_UART_IBRD_MASK    (0xFFFF << 0)

#define PL011_UART_FBRD_MASK    (0x3F << 0)

#define PL011_UART_LCRH_SPS (1 << 7) 
#define PL011_UART_LCRH_WLEN    (3 << 5) 
#define PL011_UART_LCRH_WLEN8   (3 << 5) 
#define PL011_UART_LCRH_WLEN7   (2 << 5) 
#define PL011_UART_LCRH_WLEN6   (1 << 5) 
#define PL011_UART_LCRH_WLEN5   (0 << 5) 
#define PL011_UART_LCRH_FEN (1 << 4) 
#define PL011_UART_LCRH_STP2    (1 << 3) 
#define PL011_UART_LCRH_EPS (1 << 2) 
#define PL011_UART_LCRH_PEN (1 << 1) 
#define PL011_UART_LCRH_BRK (1 << 0) 

#define PL011_UART_CR_CTSEN (1 << 15) 
#define PL011_UART_CR_RTSEN (1 << 14) 
#define PL011_UART_CR_OUT2  (1 << 13) 
#define PL011_UART_CR_OUT1  (1 << 12) 
#define PL011_UART_CR_RTS   (1 << 11) 
#define PL011_UART_CR_DTR   (1 << 10) 
#define PL011_UART_CR_RXE   (1 << 9) 
#define PL011_UART_CR_TXE   (1 << 8) 
#define PL011_UART_CR_LBE   (1 << 7) 
#define PL011_UART_CR_SIRLP (1 << 2) 
#define PL011_UART_CR_SIREN (1 << 1) 
#define PL011_UART_CR_UARTEN    (1 << 0) 

#define PL011_UART_IFLS_RXIFPSEL    (7 << 9) 
#define PL011_UART_IFLS_TXIFPSEL    (7 << 6) 
#define PL011_UART_IFLS_RXIFLSEL    (7 << 3) 
#define PL011_UART_IFLS_RXIFLSEL1_8 (0 << 3) 
#define PL011_UART_IFLS_RXIFLSEL1_4 (1 << 3) 
#define PL011_UART_IFLS_RXIFLSEL1_2 (2 << 3) 
#define PL011_UART_IFLS_RXIFLSEL3_4 (3 << 3) 
#define PL011_UART_IFLS_RXIFLSEL7_8 (4 << 3) 
#define PL011_UART_IFLS_TXIFLSEL    (7 << 0) 
#define PL011_UART_IFLS_TXIFLSEL1_8 (0 << 0) 
#define PL011_UART_IFLS_TXIFLSEL1_4 (1 << 0) 
#define PL011_UART_IFLS_TXIFLSEL1_2 (2 << 0) 
#define PL011_UART_IFLS_TXIFLSEL3_4 (3 << 0) 
#define PL011_UART_IFLS_TXIFLSEL7_8 (4 << 0) 

#define PL011_UART_IMSC_OEIM    (1 << 10) 
#define PL011_UART_IMSC_BEIM    (1 << 9) 
#define PL011_UART_IMSC_PEIM    (1 << 8) 
#define PL011_UART_IMSC_FEIM    (1 << 7) 
#define PL011_UART_IMSC_RTIM    (1 << 6) 
#define PL011_UART_IMSC_TXIM    (1 << 5) 
#define PL011_UART_IMSC_RXIM    (1 << 4) 
#define PL011_UART_IMSC_DSRMIM  (1 << 3) 
#define PL011_UART_IMSC_DCDMIM  (1 << 2) 
#define PL011_UART_IMSC_CTSMIM  (1 << 1) 
#define PL011_UART_IMSC_RIMIM   (1 << 0) 

#define PL011_UART_RIS_OERIS    (1 << 10) 
#define PL011_UART_RIS_BERIS    (1 << 9) 
#define PL011_UART_RIS_PERIS    (1 << 8) 
#define PL011_UART_RIS_FERIS    (1 << 7) 
#define PL011_UART_RIS_RTRIS    (1 << 6) 
#define PL011_UART_RIS_TXRIS    (1 << 5) 
#define PL011_UART_RIS_RXRIS    (1 << 4) 
#define PL011_UART_RIS_DSRMRIS  (1 << 3) 
#define PL011_UART_RIS_DCDMRIS  (1 << 2) 
#define PL011_UART_RIS_CTSMRIS  (1 << 1) 
#define PL011_UART_RIS_RIMRIS   (1 << 0) 

#define PL011_UART_MIS_OEMIS    (1 << 10) 
#define PL011_UART_MIS_BEMIS    (1 << 9) 
#define PL011_UART_MIS_PEMIS    (1 << 8) 
#define PL011_UART_MIS_FEMIS    (1 << 7) 
#define PL011_UART_MIS_RTMIS    (1 << 6) 
#define PL011_UART_MIS_TXMIS    (1 << 5) 
#define PL011_UART_MIS_RXMIS    (1 << 4) 
#define PL011_UART_MIS_DSRMMIS  (1 << 3) 
#define PL011_UART_MIS_DCDMMIS  (1 << 2) 
#define PL011_UART_MIS_CTSMMIS  (1 << 1) 
#define PL011_UART_MIS_RIMMIS   (1 << 0) 

#define PL011_UART_ICR_OEIC (1 << 10) 
#define PL011_UART_ICR_BEIC (1 << 9) 
#define PL011_UART_ICR_PEIC (1 << 8) 
#define PL011_UART_ICR_FEIC (1 << 7) 
#define PL011_UART_ICR_RTIC (1 << 6) 
#define PL011_UART_ICR_TXIC (1 << 5) 
#define PL011_UART_ICR_RXIC (1 << 4) 
#define PL011_UART_ICR_DSRMIC   (1 << 3) 
#define PL011_UART_ICR_DCDMIC   (1 << 2) 
#define PL011_UART_ICR_CTSMIC   (1 << 1) 
#define PL011_UART_ICR_RIMIC    (1 << 0) 






typedef struct _PL011_UART_REGISTERS PL011_UART_REGISTERS;
struct _PL011_UART_REGISTERS
{
    uint32_t dr; 
    uint32_t rsrecr; 
    uint32_t reserved01;
    uint32_t reserved02;
    uint32_t reserved03;
    uint32_t reserved04;
    uint32_t fr; 
    uint32_t reserved05;
    uint32_t ilpr; 
    uint32_t ibrd; 
    uint32_t fbrd; 
    uint32_t lcrh; 
    uint32_t cr; 
    uint32_t ifls; 
    uint32_t imsc; 
    uint32_t ris; 
    uint32_t mis; 
    uint32_t icr; 
    uint32_t dmacr; 
    uint32_t reserved11;
    uint32_t reserved12;
    uint32_t reserved13;
    uint32_t reserved14;
    uint32_t reserved15;
    uint32_t reserved16;
    uint32_t reserved17;
    uint32_t reserved18;
    uint32_t reserved19;
    uint32_t reserved1a;
    uint32_t reserved1b;
    uint32_t reserved1c;
    uint32_t reserved1d;
    uint32_t itcr; 
    uint32_t itip; 
    uint32_t itop; 
    uint32_t tdr; 
};
 
 
typedef struct _PL011_UART PL011_UART;
struct _PL011_UART
{
    // UART Properties
    UART_DEVICE uart;
    // PL011 Properties
    uint32_t irq;
    SPIN_HANDLE lock; 
    uint32_t clockrate; 
    PL011_UART_REGISTERS *registers; 
    #ifdef PL011_UART_RX_BUFFER
    uint32_t start; 
    uint32_t count; 
    uint16_t buffer[PL011_UART_RX_BUFFER_SIZE]; 
    #endif
    // Statistics Properties
    uint32_t interruptcount; 
};


UART_DEVICE * STDCALL pl011_uart_create(size_t address, char *name, uint32_t irq, uint32_t clockrate);

uint32_t STDCALL pl011_uart_destroy(UART_DEVICE *uart);
 
#ifdef __cplusplus
}
#endif
 
#endif // _ULTIBO_PL011_H