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Ultibo API
C/C++ API for Ultibo Core
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Ultibo API
C/C++ API for Ultibo Core
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Go to the source code of this file.
Data Structures | |
| struct | _DWC_HOST_CHANNEL |
| struct | _DWC_REGISTERS |
| struct | _DWC_ROOTHUB_CONFIGURATION |
| struct | _DWC_USB_HOST |
Typedefs | |
| typedef struct _DWC_HOST_CHANNEL | DWC_HOST_CHANNEL |
| typedef struct _DWC_REGISTERS | DWC_REGISTERS |
| typedef struct _DWC_ROOTHUB_CONFIGURATION | DWC_ROOTHUB_CONFIGURATION |
| typedef struct _DWC_USB_HOST | DWC_USB_HOST |
Functions | |
| USB_HOST *STDCALL | dwc_host_create (size_t address, uint32_t irq, uint32_t powerid) |
| Create and register a new DWCOTG host which can be accessed using the USB API. | |
| uint32_t STDCALL | dwc_host_destroy (USB_HOST *host) |
| Stop, deregister and destroy a DWCOTG USB host created by this driver. | |
Variables | |
| struct _DWC_ROOTHUB_CONFIGURATION | PACKED |
| #define DWCOTG_USBHOST_DESCRIPTION "DWCOTG USB Host" |
Description of DWCOTG host.
DWCOTG specific constants
| #define DWC_MAX_CHANNELS 16 |
Maximum number of DWC host channels.
| #define DWC_SCHEDULER_MAILSLOT_SIZE SIZE_1K |
Mailslot size for USB request scheduler.
| #define DWC_SCHEDULER_THREAD_STACK_SIZE SIZE_32K |
Stack size of USB request scheduler thread.
| #define DWC_SCHEDULER_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST |
Priority of USB request scheduler thread (should be fairly high so that USB transfers can be started as soon as possible).
| #define DWC_SCHEDULER_THREAD_NAME "DWC Transfer Scheduler" |
Name of USB request scheduler thread.
| #define DWC_COMPLETION_THREAD_STACK_SIZE SIZE_32K |
Stack size of USB request completion thread.
| #define DWC_COMPLETION_THREAD_PRIORITY THREAD_PRIORITY_HIGHEST |
Priority of USB request completion thread (should be fairly high so that USB transfers can be completed as soon as possible).
| #define DWC_COMPLETION_THREAD_NAME "DWC Transfer Completion" |
Name of USB request completion thread.
| #define DWC_RESUBMIT_THREAD_STACK_SIZE SIZE_32K |
Stack size of USB request resubmit threads.
| #define DWC_RESUBMIT_THREAD_PRIORITY THREAD_PRIORITY_CRITICAL |
Priority of USB request resubmit threads (should be very high since these threads are used for the necessary software polling of interrupt endpoints, which are supposed to have guaranteed bandwidth).
| #define DWC_RESUBMIT_THREAD_NAME "DWC Transfer Resubmit" |
Name of USB request resubmit threads.
| #define DWC_USB_PID_DATA0 0 |
DWC USB packet ID constants recognized by the DWC hardware
| #define DWC_USB_PID_DATA1 2 |
| #define DWC_USB_PID_DATA2 1 |
| #define DWC_USB_PID_SETUP 3 |
| #define DWC_USB_PID_MDATA 3 |
| #define DWC_RECEIVE_WORDS 1024 |
Size of Rx FIFO in 4-byte words.
DWC FIFO values
| #define DWC_TRANSMIT_WORDS 1024 |
Size of Non-periodic Tx FIFO in 4-byte words.
| #define DWC_PERIODIC_TRANSMIT_WORDS 1024 |
Size of Periodic Tx FIFO in 4-byte words.
| #define DWC_STATUS_SUCCESS 0 |
DWC Status codes
| #define DWC_STATUS_STALLED 1 |
| #define DWC_STATUS_FAILED 2 |
| #define DWC_STATUS_TRANSFER_RESUBMIT 3 |
| #define DWC_STATUS_TRANSFER_RESTART 4 |
| #define DWC_STATUS_TRANSACTION_RESTART 5 |
| #define DWC_STATUS_HOST_PORT_CHANGE 6 |
| #define DWC_STATUS_ROOT_HUB_REQUEST 7 |
| #define DWC_STATUS_INVALID 8 |
| #define DWC_STATUS_CANCELLED 9 |
| #define DWC_SPLIT_ERROR_RETRIES 3 |
DWC Complete Split
| #define DWC_COMPLETE_SPLIT_RETRIES 10 |
| #define DWC_OTG_CTRL_HST_SET_HNP_EN (1 << 10) |
DWC Register values TDWCRegisters: 0x0000 : OTG Control Register
| #define DWC_AHB_INTERRUPT_ENABLE (1 << 0) |
TDWCRegisters: 0x0008 : AHB Configuration Register Enable interrupts from the USB controller. Disabled by default
| #define BCM_DWC_AHB_AXI_BURST_MASK (3 << 1) |
Bits [4:1] of the AHB Configuration register were redefined by Broadcom for the BCM2835 Max AXI burst length
| #define BCM_DWC_AHB_AXI_WAIT (1 << 4) |
Wait for all outstanding AXI writes to complete before signalling (internally) that DMA is done
| #define DWC_AHB_DMA_ENABLE (1 << 5) |
Writing 1 to this bit in the AHB Configuration Register allows the USB controller to perform DMA (Disabled by default)
| #define DWC_AHB_MASTER_IDLE (1 << 31) |
Unknown
| #define DWC_USB_CFG_TOUTCAL_MASK (7 << 0) |
TDWCRegisters: 0x000c : Core USB Configuration Register
| #define DWC_USB_CFG_TOUTCAL_LIMIT (7 << 0) |
| #define DWC_USB_CFG_PHYIF16 (1 << 3) |
| #define DWC_USB_CFG_ULPI_UTMI_SEL (1 << 4) |
| #define DWC_USB_CFG_FS_INTF (1 << 5) |
| #define DWC_USB_CFG_PHY_SEL (1 << 6) |
| #define DWC_USB_CFG_DDR_SEL (1 << 7) |
| #define DWC_USB_CFG_SRP_CAPABLE (1 << 8) |
| #define DWC_USB_CFG_HNP_CAPABLE (1 << 9) |
| #define DWC_USB_CFG_USB_TRDTIM_MASK (0xF << 10) |
| #define DWC_USB_CFG_RESERVED14 (1 << 14) |
| #define DWC_USB_CFG_PHY_LOW_PWR_CLK_SEL (1 << 15) |
| #define DWC_USB_CFG_OTG_UTMI_FS_SEL (1 << 16) |
| #define DWC_USB_CFG_ULPI_FSLS (1 << 17) |
| #define DWC_USB_CFG_ULPI_AUTO_RES (1 << 18) |
| #define DWC_USB_CFG_ULPI_CLK_SUS_M (1 << 19) |
| #define DWC_USB_CFG_ULPI_EXT_VBUS_DRV (1 << 20) |
| #define DWC_USB_CFG_ULPI_INT_VBUS_INDICATOR (1 << 21) |
| #define DWC_USB_CFG_TERM_SEL_DL_PULSE (1 << 22) |
| #define DWC_USB_CFG_INDICATOR_COMPLEMENT (1 << 23) |
| #define DWC_USB_CFG_INDICATOR_PASS_THROUGH (1 << 24) |
| #define DWC_USB_CFG_ULPI_INT_PROT_DIS (1 << 25) |
| #define DWC_USB_CFG_IC_USB_CAP (1 << 26) |
| #define DWC_USB_CFG_IC_TRAFFIC_PULL_REMOVE (1 << 27) |
| #define DWC_USB_CFG_TX_END_DELAY (1 << 28) |
| #define DWC_USB_CFG_FORCE_HOST_MODE (1 << 29) |
| #define DWC_USB_CFG_FORCE_DEV_MODE (1 << 30) |
| #define DWC_USB_CFG_RESERVED31 (1 << 31) |
| #define DWC_SOFT_RESET (1 << 0) |
TDWCRegisters: 0x0010 : Core Reset Register Write 1 to this location in the Core Reset Register to start a soft reset. This bit will then be cleared by the hardware when the reset is complete
| #define DWC_CORE_INTERRUPTS_SOF_INTR (1 << 3) |
Bit 3.
TDWCRegisters: 0x0014 : Core Interrupt Register This register contains the state of pending top-level DWC interrupts. 1 means interrupt pending while 0 means no interrupt pending Note that at least for port_intr and host_channel_intr, software must clear the interrupt somewhere else rather than by writing to this register Start of Frame.
| #define DWC_CORE_INTERRUPTS_PORT_INTR (1 << 24) |
Bit 24.
Host port status changed. Software must examine the Host Port Control and Status Register to determine the current status of the host port and clear any flags in it that indicate a status change
| #define DWC_CORE_INTERRUPTS_HOST_CHANNEL_INTR (1 << 25) |
Bit 25.
Channel interrupt occurred. Software must examine the Host All Channels Interrupt Register to determine which channel(s) have pending interrupts, then handle and clear the interrupts for these channels
| #define DWC_CORE_INTERRUPTS_DISCONNECT (1 << 29) |
Bit 29.
Disconnect interrupt indicated that a device has been disconnected from the root port
| #define DWC_VENDOR_ID_OTG2 0x4f542000 |
TDWCRegisters: 0x0040 : Vendor Id Register
| #define DWC_VENDOR_ID_OTG3 0x4f543000 |
| #define DWC_VENDOR_ID_MASK 0xfffff000 |
| #define DWC_HWCFG2_OP_MODE_MASK (7 << 0) |
TDWCRegisters: 0x0048 : Hardware Configuration 2
| #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG (0 << 0) |
| #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG (1 << 0) |
| #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG (2 << 0) |
| #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (3 << 0) |
| #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (4 << 0) |
| #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST (5 << 0) |
| #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (6 << 0) |
| #define DWC_HWCFG2_ARCHITECTURE_MASK (3 << 3) |
| #define DWC_HWCFG2_ARCHITECTURE_SLAVE_ONLY (0 << 3) |
| #define DWC_HWCFG2_ARCHITECTURE_EXT_DMA (1 << 3) |
| #define DWC_HWCFG2_ARCHITECTURE_INT_DMA (2 << 3) |
| #define DWC_HWCFG2_POINT2POINT (1 << 5) |
| #define DWC_HWCFG2_HS_PHY_TYPE_MASK (3 << 6) |
| #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0 << 6) |
| #define DWC_HWCFG2_HS_PHY_TYPE_UTMI (1 << 6) |
| #define DWC_HWCFG2_HS_PHY_TYPE_ULPI (2 << 6) |
| #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI (3 << 6) |
| #define DWC_HWCFG2_FS_PHY_TYPE_MASK (3 << 8) |
| #define DWC_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0 << 8) |
| #define DWC_HWCFG2_FS_PHY_TYPE_DEDICATED (1 << 8) |
| #define DWC_HWCFG2_FS_PHY_TYPE_SHARED_UTMI (2 << 8) |
| #define DWC_HWCFG2_FS_PHY_TYPE_SHARED_ULPI (3 << 8) |
| #define DWC_HWCFG2_NUM_DEV_ENDPOINTS (0xF << 10) |
| #define DWC_HWCFG2_NUM_HOST_CHANNELS (0xF << 14) |
| #define DWC_HWCFG2_PERIODIC_ENDPOINT_SUPPORTED (1 << 18) |
| #define DWC_HWCFG2_DYNAMIC_FIFO (1 << 19) |
| #define DWC_HWCFG2_MULTI_PROC_INT (1 << 20) |
| #define DWC_HWCFG2_RESERVED21 (1 << 21) |
| #define DWC_HWCFG2_NON_PERIODIC_TX_QUEUE_DEPTH (3 << 22) |
| #define DWC_HWCFG2_HOST_PERIODIC_TX_QUEUE_DEPTH (3 << 24) |
| #define DWC_HWCFG2_DEV_TOKEN_QUEUE_DEPTH (0x1F << 26) |
| #define DWC_HWCFG2_OTG_ENABLE_IC_USB (1 << 31) |
| #define DWC_HCFG_FS_LS_PHY_CLK_SEL_MASK (3 << 0) |
FS/LS Phy Clock Select.
TDWCRegisters: 0x0400 : Host Configuration Register
| #define DWC_HCFG_FS_LS_PHY_CLK_SEL_SHIFT 0 |
| #define DWC_HCFG_FS_LS_PHY_CLK_SEL_30_60_MHZ 0 |
| #define DWC_HCFG_FS_LS_PHY_CLK_SEL_48_MHZ 1 |
| #define DWC_HCFG_FS_LS_PHY_CLK_SEL_6_MHZ 2 |
| #define DWC_HCFG_FS_LS_SUPPORT_ONLY (1 << 2) |
FS/LS Only Support.
| #define DWC_HCFG_ENABLE_32KHZ (1 << 7) |
Enable 32-KHz Suspend Mode.
| #define DWC_HCFG_RESUME_VALID_MASK (0xFF << 8) |
Resume Validation Period.
| #define DWC_HCFG_RESUME_VALID_SHIFT 8 |
| #define DWC_HCFG_DESC_DMA (1 << 23) |
Enable Scatter/gather DMA in Host mode.
| #define DWC_HCFG_FRAME_LIST_ENTRIES_MASK (3 << 24) |
Frame List Entries.
| #define DWC_HCFG_FRAME_LIST_ENTRIES_SHIFT 24 |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_8 (0 << 24) |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_8_SIZE 8 |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_16 (1 << 24) |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_16_SIZE 16 |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_32 (3 << 24) |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_32_SIZE 32 |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_64 (3 << 24) |
| #define DWC_HCFG_FRAME_LIST_ENTRIES_64_SIZE 64 |
| #define DWC_HCFG_PERSCHED_ENA (1 << 26) |
Enable Periodic Scheduling.
| #define DWC_HCFG_MODE_CH_TIM_EN (1 << 31) |
| #define DWC_HFIR_FRAME_INTERVAL_MASK (0xFFFF << 0) |
TDWCRegisters: 0x0404 : Host Frame Interval Register
| #define DWC_HFIR_FRAME_INT_RELOAD_CTL (1 << 16) |
| #define DWC_HFIR_RESERVED1 (0xFFFE << 17) |
| #define DWC_HFNUM_FRAME_NUMBER_MASK 0xFFFF |
TDWCRegisters: 0x0408 : Host Frame Register
| #define DWC_HOST_PORT_CTRLSTATUS_CONNECTED (1 << 0) |
Bit 0.
TDWCRegisters: 0x0440 : Host Port Control and Status Register This register provides the information needed to respond to status queries about the "host port", which is the port that is logically attached to the root hub When changing this register, software must read its value, then clear the enabled, connected_changed, enabled_changed, and overcurrent_changed members to avoid changing them, as those particular bits are cleared by writing 1 1: a device is connected to this port. 0: no device is connected to this port. Changed by hardware only
| #define DWC_HOST_PORT_CTRLSTATUS_CONNECTED_CHANGED (1 << 1) |
Bit 1.
Set by hardware when connected bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register
| #define DWC_HOST_PORT_CTRLSTATUS_ENABLED (1 << 2) |
Bit 2.
1: port is enabled. 0: port is disabled. Note: the host port is enabled by default after it is reset. Note: Writing 1 here appears to disable the port
| #define DWC_HOST_PORT_CTRLSTATUS_ENABLED_CHANGED (1 << 3) |
Bit 3.
Set by hardware when enabled bit changes. Software can write 1 to acknowledge and clear. The setting of this bit by hardware generates an interrupt that can be enabled by setting port_intr in the core_interrupt_mask register
| #define DWC_HOST_PORT_CTRLSTATUS_OVERCURRENT (1 << 4) |
Bit 4.
1: overcurrent condition active on this port 0: no overcurrent condition active on this port Changed by hardware only
| #define DWC_HOST_PORT_CTRLSTATUS_OVERCURRENT_CHANGED (1 << 5) |
Bit 5.
Set by hardware when the overcurrent bit changes. The software can write 1 to acknowledge and clear. The setting of this bit by hardware generates the interrupt that can be enabled by setting port_intr in the core_interrupt_mask register
| #define DWC_HOST_PORT_CTRLSTATUS_RESUME (1 << 6) |
Bit 6.
Set by software to set resume signalling
| #define DWC_HOST_PORT_CTRLSTATUS_SUSPENDED (1 << 7) |
Bit 7.
Set by software to suspend the port
| #define DWC_HOST_PORT_CTRLSTATUS_RESET (1 << 8) |
Bit 8.
Software can set this to start a reset on this port. Software must clear this after waiting 60 milliseconds for the reset to complete
| #define DWC_HOST_PORT_CTRLSTATUS_RESERVED (1 << 9) |
Bit 9.
| #define DWC_HOST_PORT_CTRLSTATUS_LINE_STATUS (3 << 10) |
Bits 10-11.
Current logic of data lines (10: logic of D+; 11: logic of D-). Changed by hardware only
| #define DWC_HOST_PORT_CTRLSTATUS_POWERED (1 << 12) |
Bit 12.
1: port is powered. 0: port is not powered. Software can change this bit to power on (1) or power off (0) the port
| #define DWC_HOST_PORT_CTRLSTATUS_TEST_CONTROL (0x0F << 13) |
Bits 13-16.
| #define DWC_HOST_PORT_CTRLSTATUS_SPEED (3 << 17) |
Bits 17-18.
Speed of attached device (if any). This should only be considered meaningful if the connected bit is set. 00: high speed; 01: full speed; 10: low speed Changed by hardware only
| #define DWC_HOST_PORT_CTRLSTATUS_RESERVED2 (0x1FFF << 19) |
Bits 19-32.
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_MAX_PACKET_SIZE (0x7FF << 0) |
Bits 0-10.
TDWCHostChannel: 0x0000 : Channel Characteristics Register Contains various fields that must be set to prepare this channel for a transfer to or from a particular endpoint on a particular USB device This register only needs to be programmed one time when doing a transfer, regardless of how many packets it consists of, unless the channel is re-programmed for a different transfer or the transfer is moved to a different channel Maximum packet size the endpoint is capable of sending or receiving. Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_NUMBER (0x0F << 11) |
Bits 11-14.
Endpoint number (low 4 bits of bEndpointAddress). Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_DIRECTION (1 << 15) |
Bit 15.
Endpoint direction (high bit of bEndpointAddress). Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_RESERVED (1 << 16) |
Bit 16.
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_LOWSPEED (1 << 17) |
Bit 17.
1 when the device being communicated with is attached at low speed; 0 otherwise. Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_ENDPOINT_TYPE (3 << 18) |
Bits 18-19.
Endpoint type (low 2 bits of bmAttributes). Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_PACKETS_PER_FRAME (3 << 20) |
Bits 20-21.
Maximum number of transactions that can be executed per microframe as part of this transfer. Normally 1, but should be set to 1 + (bits 11 and 12 of wMaxPacketSize) for high-speed interrupt and isochronous endpoints. Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_DEVICE_ADDRESS (0x7F << 22) |
Bits 22-28.
USB device address of the device on which the endpoint is located. Must be programmed by software before starting the transfer
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_ODD_FRAME (1 << 29) |
Bit 29.
Just before enabling the channel (for all transactions), software needs to set this to the opposite of the low bit of the host_frame_number register. Otherwise the hardware will issue frame overrun errors on some transactions. TODO: what exactly does this do?
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_CHANNEL_DISABLE (1 << 30) |
Bit 30.
Software can set this to 1 to halt the channel. Not needed during normal operation as the channel halts automatically when a transaction completes or an error occurs
| #define DWC_HOST_CHANNEL_CHARACTERISTICS_CHANNEL_ENABLE (1 << 31) |
Bit 31.
Software can set this to 1 to enable the channel, thereby actually starting the transaction on the USB. This must only be done after the characteristics, split_control, and transfer registers, and possibly other registers (depending on the transfer) have been programmed
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_PORT_ADDRESS (0x7F << 0) |
Bits 0-6.
TDWCHostChannel: 0x0004 : Channel Split Control Register This register is used to set up Split Transactions for communicating with low or full-speed devices attached to a high-speed hub. When doing so, set split_enable to 1 and the other fields as documented. Otherwise, software must clear this register before starting the transfer Like the Channel Characteristics register, this register only needs to be programmed one time if the channel is enabled multiple times to send all the packets of a single transfer 0-based index of the port on the high-speed hub on which the low or full-speed device is attached.
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_HUB_ADDRESS (0x7F << 7) |
Bits 7-13.
USB device address of the high-speed hub that acts as the Transaction Translator for this low or full-speed device. This is not necessarily the hub the device is physically connected to, since that could be a full-speed or low-speed hub. Instead, software must walk up the USB device tree (towards the root hub) until a high-speed hub is found and use its device address here
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_TRANSACTION_POSITION (3 << 14) |
Bits 14-15.
TODO: what exactly does this do?
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_COMPLETE_SPLIT (1 << 16) |
Bit 16.
0: Do a Start Split transaction 1: Do a Complete Split transaction. When split transactions are enabled, this must be programmed by software before enabling the channel. Note that you must begin with a Start Split transaction and alternate this bit for each transaction until the transfer is complete
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_RESERVED (0x3FFF << 17) |
Bits 17-30.
| #define DWC_HOST_CHANNEL_SPLIT_CONTROL_SPLIT_ENABLE (1 << 31) |
Bit 31.
Set to 1 to enable Split Transactions
| #define DWC_HOST_CHANNEL_INTERRUPTS_TRANSFER_COMPLETED (1 << 0) |
Bit 0.
TDWCHostChannel: 0x0008 : Channel Interrupts Register Bitmask of status conditions that have occurred on this channel These bits can be used with or without "real" interrupts. To have the CPU get a real interrupt when one of these bits gets set, set the appropriate bit in the interrupt_mask, and also ensure that interrupts from the channel are enabled in the host_channels_interrupt_mask register, channel interrupts overall are enabled in the core_interrupt_mask register, and interrupts from the DWC hardware overall are enabled in the ahb_configuration register and by any system-specific interrupt controller The requested USB transfer has successfully completed Exceptions and caveats:
| #define DWC_HOST_CHANNEL_INTERRUPTS_CHANNEL_HALTED (1 << 1) |
Bit 1.
The channel has halted. After this bit has been set, the channel sits idle and nothing else will happen until software takes action. Channels may halt for several reasons. From our experience these cover all possible situations in which software needs to take action, so this is the only channel interrupt that actually needs to be enabled. At least in DMA mode, the controller to some extent will act autonomously to complete transfers and only issue this interrupt when software needs to take action. Situations in which a channel will halt include but probably are not limited to:
| #define DWC_HOST_CHANNEL_INTERRUPTS_AHB_ERROR (1 << 2) |
Bit 2.
An error occurred on the ARM Advanced High-Performance Bus (AHB)
| #define DWC_HOST_CHANNEL_INTERRUPTS_STALL_RESPONSE_RECEIVED (1 << 3) |
Bit 3.
The device issued a STALL handshake packet (endpoint is halted or control pipe request is not supported)
| #define DWC_HOST_CHANNEL_INTERRUPTS_NAK_RESPONSE_RECEIVED (1 << 4) |
Bit 4.
The device issued a NAK handshake packet (receiving device cannot accept data or transmitting device cannot send data) The channel will halt with this bit set when performing an IN transfer from an interrupt endpoint that has no data to send As this requires software intervention to restart the channel, this means that polling of interrupt endpoints (e.g. on hubs and HID devices) must be done in software, even if the actual transactions themselves are interrupt-driven
| #define DWC_HOST_CHANNEL_INTERRUPTS_ACK_RESPONSE_RECEIVED (1 << 5) |
Bit 5.
The device issued an ACK handshake packet (receiving device acknowledged error-free packet)
| #define DWC_HOST_CHANNEL_INTERRUPTS_NYET_RESPONSE_RECEIVED (1 << 6) |
Bit 6.
The device issued a NYET handshake packet
| #define DWC_HOST_CHANNEL_INTERRUPTS_TRANSACTION_ERROR (1 << 7) |
Bit 7.
From our experience this seems to usually indicate that software programmed the channel incorrectly
| #define DWC_HOST_CHANNEL_INTERRUPTS_BABBLE_ERROR (1 << 8) |
Bit 8.
Unexpected bus activity occurred
| #define DWC_HOST_CHANNEL_INTERRUPTS_FRAME_OVERRUN (1 << 9) |
Bit 9.
TODO
| #define DWC_HOST_CHANNEL_INTERRUPTS_DATA_TOGGLE_ERROR (1 << 10) |
Bit 10.
When issuing a series of DATA transactions to an endpoint, the correct DATA0 or DATA1 packet ID was not specified in the packet_id member of the transfer register
| #define DWC_HOST_CHANNEL_INTERRUPTS_BUFFER_NOT_AVAILABLE (1 << 11) |
Bit 11.
| #define DWC_HOST_CHANNEL_INTERRUPTS_EXCESS_TRANSACTION_ERROR (1 << 12) |
Bit 12.
| #define DWC_HOST_CHANNEL_INTERRUPTS_FRAME_LIST_ROLLOVER (1 << 13) |
Bit 13.
| #define DWC_HOST_CHANNEL_INTERRUPTS_RESERVED (0x3FFFF << 14) |
Bits 14-31.
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_TRANSFER_COMPLETED DWC_HOST_CHANNEL_INTERRUPTS_TRANSFER_COMPLETED |
TDWCHostChannel: 0x000c : Channel Interrupts Mask Register This has the same format as the Channel Interrupts Register, but software uses this to enable (1) or disable (0) the corresponding interrupt. Defaults to all 0's after a reset
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_CHANNEL_HALTED DWC_HOST_CHANNEL_INTERRUPTS_CHANNEL_HALTED |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_AHB_ERROR DWC_HOST_CHANNEL_INTERRUPTS_AHB_ERROR |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_STALL_RESPONSE_RECEIVED DWC_HOST_CHANNEL_INTERRUPTS_STALL_RESPONSE_RECEIVED |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_NAK_RESPONSE_RECEIVED DWC_HOST_CHANNEL_INTERRUPTS_NAK_RESPONSE_RECEIVED |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_ACK_RESPONSE_RECEIVED DWC_HOST_CHANNEL_INTERRUPTS_ACK_RESPONSE_RECEIVED |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_NYET_RESPONSE_RECEIVED DWC_HOST_CHANNEL_INTERRUPTS_NYET_RESPONSE_RECEIVED |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_TRANSACTION_ERROR DWC_HOST_CHANNEL_INTERRUPTS_TRANSACTION_ERROR |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_BABBLE_ERROR DWC_HOST_CHANNEL_INTERRUPTS_BABBLE_ERROR |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_FRAME_OVERRUN DWC_HOST_CHANNEL_INTERRUPTS_FRAME_OVERRUN |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_DATA_TOGGLE_ERROR DWC_HOST_CHANNEL_INTERRUPTS_DATA_TOGGLE_ERROR |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_BUFFER_NOT_AVAILABLE DWC_HOST_CHANNEL_INTERRUPTS_BUFFER_NOT_AVAILABLE |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_EXCESS_TRANSACTION_ERROR DWC_HOST_CHANNEL_INTERRUPTS_EXCESS_TRANSACTION_ERROR |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_FRAME_LIST_ROLLOVER DWC_HOST_CHANNEL_INTERRUPTS_FRAME_LIST_ROLLOVER |
| #define DWC_HOST_CHANNEL_INTERRUPT_MASK_RESERVED DWC_HOST_CHANNEL_INTERRUPTS_RESERVED |
| #define DWC_HOST_CHANNEL_TRANSFER_SIZE (0x7FFFF << 0) |
Bits 0-18.
TDWCHostChannel: 0x0010 : Channel Transfer Register Used to store additional information about the transfer. This must be programmed before beginning the transfer Size of the data to send or receive, in bytes. Software must program this before beginning the transfer. This can be greater than the maximum packet length. For IN transfers, the hardware decrements this field for each packet received by the number of bytes received. For split transactions, the decrement happens after the Complete Split rather than the Start Split. Software can subtract this field from the original transfer size in order to determine the number of bytes received at any given point, including when the transfer has encountered an error or has completed with either the full size or a short size. For OUT transfers, the hardware does not update this field as expected. It will not be decremented when data is transmitted, at least not in every case; hence, software cannot rely on its value to indicate how many bytes of data have been transmitted so far. Instead, software must inspect the packet_count field and assume that all data was transmitted if packet_count is 0, or that the amount of data transmitted is equal to the endpoint's maximum packet size times [the original packet count minus packet_count] if packet_count is nonzero
| #define DWC_HOST_CHANNEL_TRANSFER_PACKET_COUNT (0x3FF << 19) |
Bits 19-28.
Number of packets left to transmit or maximum number of packets left to receive. Software must program this before beginning the transfer. The packet count is calculated as the size divided by the maximum packet size, rounded up to the nearest whole packet. As a special case, if the transfer size is 0 bytes, the packet count must be set to 1. The hardware will decrement this register when a packet is successfully sent or received. In the case of split transactions, this happens after the Complete Split rather than after the Start Split. If the final received packet of an IN transfer is short, it is still counted
| #define DWC_HOST_CHANNEL_TRANSFER_PACKET_ID (0x03 << 29) |
Bits 29-30.
High 2 bits of the Packet ID used in the USB protocol. When performing the SETUP phase of a control transfer, specify 0x3 here to generate the needed SETUP token. When performing the DATA phase of a control transfer, initially specify 0x2 here to begin the DATA packets with the needed DATA1 Packet ID. When performing the STATUS phase of a control transfer, specify 0x2 here to generate the needed DATA1 Packet ID. When starting a bulk, isochronous, or interrupt transfer, specify 0x0 here to generate the needed DATA0 Packet ID. In the case of a transfer consisting of multiple DATA packets, the hardware will update this field with the Packet ID to use for the next packet. This field therefore only needs to be re-programmed if the transfer is moved to a different channel or the channel is re-used before the transfer is complete. When doing so, software must save this field so that it can be re-programmed correctly
| #define DWC_HOST_CHANNEL_TRANSFER_DO_PING (1 << 31) |
Bit 31.
Do PING protocol when 1 (See Section 8.5.1 of Universal Serial Bus Specification 2.0)
| typedef struct _DWC_HOST_CHANNEL DWC_HOST_CHANNEL |
DWCOTG specific types TDWCRegisters: 0x0500 : Array of host channels. Each host channel can be used to execute an independent USB transfer or transaction simultaneously. A USB transfer may consist of multiple transactions, or packets. To avoid having to re-program the channel, it may be useful to use one channel for all transactions of a transfer before allowing other transfers to be scheduled on it.
| typedef struct _DWC_REGISTERS DWC_REGISTERS |
Layout of the registers of the DesignWare Hi-Speed USB 2.0 On-The-Go Controller. There is no official documentation for these; however, the register locations (and to some extent the meanings) can be found in other code, such as the Linux driver for this hardware that Synopsys contributed.
We do not explicitly define every bit in the registers because the majority are not used by our driver and would complicate this file. For example, we do not attempt to document any features that are specific to suspend, hibernation, the OTG protocol, or to the core acting in device mode rather than host mode.
The bits and fields we do use in our driver we have tried to completely document based on our understanding of what they do. We cannot guarantee that all the information is correct, as we do not have access to any official documentation
| typedef struct _DWC_ROOTHUB_CONFIGURATION DWC_ROOTHUB_CONFIGURATION |
DWC Root Hub Configuration
| typedef struct _DWC_USB_HOST DWC_USB_HOST |
DWC USB Host
Create and register a new DWCOTG host which can be accessed using the USB API.
DWCOTG Functions
| Address | The address of the DWCOTG registers |
| IRQ | The interrupt number for the DWCOTG host |
| PowerID | The power ID value to power on the host using PowerOn (or POWER_ID_UNKNOWN if not applicable) |
Stop, deregister and destroy a DWCOTG USB host created by this driver.
| Host | The USB host to destroy |
| struct _DWC_ROOTHUB_CONFIGURATION PACKED |
1.16.1