Unit DMA

`DMA_FLAG_NONE = $00000000;`
`DMA_FLAG_SHARED = $00000001;`	Host requires data buffers in shared memory
`DMA_FLAG_NOCACHE = $00000002;`	Host requires data buffers in non cached memory
`DMA_FLAG_COHERENT = $00000004;`	Data buffers are cache coherent if allocated according to host configuration
`DMA_FLAG_STRIDE = $00000008;`	Host supports 2D stride on source and/or dest address
`DMA_FLAG_DREQ = $00000010;`	Host supports data request gating (DREQ) on source and/or dest address
`DMA_FLAG_NOINCREMENT = $00000020;`	Host supports no increment on source and/or dest address
`DMA_FLAG_NOREAD = $00000040;`	Host supports no read from source address (write to dest address only) (Zero fill the destination)
`DMA_FLAG_NOWRITE = $00000080;`	Host supports no write to dest address (read from source address only) (Cache fill from the source)
`DMA_FLAG_WIDE = $00000100;`	Host supports wide read and/or write
`DMA_FLAG_BULK = $00000200;`	Host supports bulk transfer

`DMA_REQUEST_FLAG_NONE = $00000000;`
`DMA_REQUEST_FLAG_RELEASE = $00000001;`	If set then release the request automatically after completion
`DMA_REQUEST_FLAG_CYCLIC = $00000002;`	This is a cyclic request which loops around from tail to head

`DMA_LOG_LEVEL_DEBUG = LOG_LEVEL_DEBUG;`	DMA debugging messages
`DMA_LOG_LEVEL_INFO = LOG_LEVEL_INFO;`	DMA informational messages, such as a device being attached or detached
`DMA_LOG_LEVEL_ERROR = LOG_LEVEL_ERROR;`	DMA error messages
`DMA_LOG_LEVEL_NONE = LOG_LEVEL_NONE;`	No DMA messages

Size	Size in bytes to allocate for new DMA (Including the DMA entry")
Return	Pointer to new DMA entry or nil if DMA could not be created

DMA	The DMA host that the request will be sent to
Size	The size of the data buffer to allocate
Return	The newly allocated buffer or nil on failure

Contents

DMA	The DMA host that the request will be sent to
Buffer	The data buffer to validate
Size	The size of the data buffer
Return	ERROR_SUCCESS on success or another error code on failure (ERROR_NOT_COMPATIBLE if not compatible with host)
Note	Does not check for cache coherency requirements (Shared, Non Cached) only alignment and size. Buffers used as the source of a DMA request do not neccessarily need to meet alignment and size requirements, however buffers used as a destintation must meet these requirements or the caller must take appropriate actions to prevent undesiraable side effects from cache invalidation.

Data	The buffer to be released
Return	ERROR_SUCCESS on success or another error code on failure

DMA	The DMA host this request will be sent to
Data	A linked list of DMA data blocks for the transfer (Optional)
Callback	The callback function to be called on completion of the request
DriverData	Driver private data for the callback (Optional)
Direction	The direction of the DMA request (eg DMA_DIR_MEM_TO_MEM)
Peripheral	The peripheral ID for data request gating (eg DMA_DREQ_ID_NONE)
Flags	Additional flags for this request (eg DMA_REQUEST_FLAG_CYCLIC)
Return	The newly allocated request or nil on failure

Request	The request to be released
Return	ERROR_SUCCESS on success or another error code on failure

Request	The request to be submitted
Return	ERROR_SUCCESS if completed or another error code on failure
Note	The request will be completed asynchronously by the DMA host and the completion callback will be called when the request has either succeeded or failed

Request	The request to be cancelled
Return	ERROR_SUCCESS if completed or another error code on failure

Request	The DMA request which has completed
Note	DMA host drivers may call this on a worker thread

DMA	The DMA host to execute the request on
Data	A linked list of DMA data blocks for the transfer
Direction	The direction of the DMA request (eg DMA_DIR_MEM_TO_MEM)
Peripheral	The peripheral ID for data request gating (eg DMA_DREQ_ID_NONE)
Flags	Additional flags for this transfer request (eg DMA_REQUEST_FLAG_CYCLIC)
Timeout	Milliseconds to wait for request to complete (INFINITE to wait forever)
Note	An internal callback will be specified and the function will wait for the transfer to complete

Dest	The address to start the memory fill
Size	The size of memory to fill in bytes
Value	The value to fill the memory with

Source	The source address to start the memory copy
Dest	The destination address to start the memory copy
Size	The size of memory to copy in bytes

`DMA_STATE_DISABLED = 0;`
`DMA_STATE_ENABLED = 1;`

Address	The address of the periperhal register to read from
Dest	The destination address to start writing to
Size	The size of the read in bytes
Peripheral	The peripheral ID for data request gating (eg DMA_DREQ_ID_UART_RX)

Source	The source address to start reading from
Address	The address of the peripheral register to write to
Size	The size of the write in bytes
Peripheral	The peripheral ID for data request gating (eg DMA_DREQ_ID_UART_TX)