Unit BootRPi2
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Description
Raspberry Pi 2
SoC: Broadcom BCM2836
CPU: Cortex A7 (ARMv7) (4 @ 900MHz) Cache: L1 32KB (Per Core) / L2 512KB (Shared by all Cores)
FPU: VFPV3
GPU: Broadcom VideoCore IV (VC4)
RAM: 1GB
USB: Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller (DWCOTG)
LAN: SMSC LAN9514 (SMSC95XX)
SD/MMC: Arasan (BCM2709)
WiFi: (None)
Bluetooth: (None)
Other: GPIO / SPI / I2C / I2S / PL011 (UART) / PWM / SMI / Watchdog (PM) / Random (RNG) / Timer ???
Boot RPi2
The boot loader on the Raspberry Pi 2 will load this code at address 0x00008000 onwards and set the following registers before jumping to this code.
R0 - Zero
R1 - Machine Type (Raspberry Pi 2 or BCM2709 = 0x0C42)
R2 - Address of the ARM Tags structure (Normally 0x0100)
On entry to this code the processor will be in the following state:
World - Non Secure (Firmware causes a switch to Non Secure before jumping to Startup code)
Mode - Supervisor (ARM_MODE_SVC) Note: Firmware later than 2/10/2015 will boot in Hypervisor mode (ARM_MODE_HYP)
MMU - Disabled
FPU - Disabled
L1 Data Cache - Enabled (Firmware enabled prior to Non Secure switch)
L1 Instruction Cache - Enabled (Firmware enabled prior to Non Secure switch)
Branch Predication - Disabled
Unaligned Data Access - Enabled (Always enabled on ARMv7)
SMP Coherence - Enabled (Firmware enabled prior to Non Secure switch)
If the processor is in Hypervisor mode (Firmware behaviour after 2/10/2015) then Ultibo switches it to Supervisor mode during initial boot.
If the configuration option RPI2_SECURE_BOOT is set to 1 then Ultibo switches the processor back to Secure world during initial boot (see note below).
Ultibo then switches the processor to System mode for all operations and remains in either the Secure or Non Secure World as per the option above.
The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.
Returning to Secure World:
The Raspberry Pi 2 firmware always switches to Non Secure world in order to:
a) Reset CNTVOFF (Virtual Offset register) to zero
b) Switch to Hypervisor mode (Firmware later than 2/10/2015)
It is not normally possible (by design) to return from the Non Secure world to the Secure world except by invoking the Secure Monitor which then handles any requests in the Secure world.
However due to the fact that this switch is performed by the boot loader code (loaded between 0x00000000 and 0x000000FF by the firmware) and that the code appears to set the secure, non secure and monitor vector base addresses to 0x00000000 and because all memory is writable from non secure at boot (the MMU is disabled) then the option exists to return to the Secure world as follows:
- Install a new Secure Monitor Call vector at the appropriate point in the vector table - Clean the data cache by Modified Virtual Address at address 0x00000000 - Perform a data synchronisation barrier - Invalidate the entire instruction cache - Perform a data synchronisation barrier - Perform an instruction synchronisation barrier - Perform a Secure Monitor Call (SMC) - From within the newly installed Secure Monitor Call read the Secure Configuration Register (SCR) mask off the Non Secure (NS) bit, rewrite the SCR and then return to Supervisor mode
Secondary cores also switch back to the Secure world using the same technique however they do not need to install the new SMC vector and instead use the one installed by the primary core.
Future changes to the firmware will hopefully not invalidate this technique, however there is also the option to use the config.txt parameter kernel_old=1 which would load Ultibo at 0x00000000 and allow us to setup the boot state independant of the firmware. This would require changes to both Ultibo (this boot module) and to the FPC compiler to change the linker start location.
Constants
To be documented
Type definitions
To be documented
Public variables
To be documented
Function declarations
To be documented
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