Unit BCM2835
From Ultibo.org
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Description
Some of the information in this file is documented in the Broadcom BCM2835-ARM-Peripherals document, some can only be found in the Linux source.
Constants
BCM2835 specific constants
BCM2835_* BCM2835_CPU_COUNT = 1;
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BCM2835 ARM physical to VC IO mapping constants
BCM2835_VCIO_* | See: BCM2835-ARM-Peripherals.pdf | |
BCM2835_VCIO_ALIAS = $7E000000;
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BCM2835 ARM physical to VC bus mapping constants
BCM2835_VCBUS_* | See: BCM2835-ARM-Peripherals.pdf | |
BCM2835_VCBUS_0_ALIAS = $00000000;
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0 Alias - L1 and L2 cached |
BCM2835_VCBUS_4_ALIAS = $40000000;
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4 Alias - L2 cache coherent (non allocating) Suitable for RPi Model A/B/A+/B+ if disable_l2cache=0 in config.txt (Default) |
BCM2835_VCBUS_8_ALIAS = $80000000;
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8 Alias - L2 cached (only) |
BCM2835_VCBUS_C_ALIAS = $C0000000;
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C Alias - Direct uncached Suitable for RPi Model A/B/A+/B+ only if disable_l2cache=1 in config.txt |
BCM2835 peripherals constants
BCM2835_PERIPHERALS_* | See: BCM2835-ARM-Peripherals.pdf | |
BCM2835_PERIPHERALS_BASE = $20000000;
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Mapped to VC address 7E000000 |
BCM2835_PERIPHERALS_SIZE = $00FFFFFF;
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BCM2835 interrupt controller 0 constants
BCM2835_IC0_* BCM2835_IC0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $2000;
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BCM2835 system timer constants
BCM2835_SYSTEM_TIMER_* | See Section 12 | |
BCM2835_SYSTEM_TIMER_REGS_BASE = BCM2835_PERIPHERALS_BASE + $3000;
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BCM2835 message based parallel host interface constants
BCM2835_MPHI_* BCM2835_MPHI_REGS_BASE = BCM2835_PERIPHERALS_BASE + $6000;
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BCM2835 DMA controller constants
BCM2835_DMA* | See Section 4 | |
| Channels 0 to 14 | |
BCM2835_DMA0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7000;
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BCM2835_DMA1_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7100;
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BCM2835_DMA2_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7200;
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BCM2835_DMA3_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7300;
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BCM2835_DMA4_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7400;
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BCM2835_DMA5_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7500;
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BCM2835_DMA6_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7600;
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BCM2835_DMA7_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7700;
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BCM2835_DMA8_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7800;
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BCM2835_DMA9_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7900;
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BCM2835_DMA10_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7A00;
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BCM2835_DMA11_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7B00;
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BCM2835_DMA12_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7C00;
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BCM2835_DMA13_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7D00;
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BCM2835_DMA14_REGS_BASE = BCM2835_PERIPHERALS_BASE + $7E00;
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BCM2835_DMA_INT_STATUS_BASE = BCM2835_PERIPHERALS_BASE + $7FE0;
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BCM2835_DMA_ENABLE_BASE = BCM2835_PERIPHERALS_BASE + $7FF0;
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BCM2835 ARM interrupt controller constants
BCM2835_INTERRUPT_* | See Section 7 | |
BCM2835_INTERRUPT_REGS_BASE = BCM2835_PERIPHERALS_BASE + $B200;
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Note: Broadcom states 0xB000 but the offsets begin at 0x200 so 0xB200 will be correct |
BCM2835 ARM timer constants
BCM2835_TIMER_* | See Section 14 | |
BCM2835_TIMER_REGS_BASE = BCM2835_PERIPHERALS_BASE + $B400;
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Note: Broadcom states 0xB000 but the offsets begin at 0x400 so 0xB400 will be correct |
BCM2835 ARM mailbox 0 constants
BCM2835_MAILBOX0_* BCM2835_MAILBOX0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $B880;
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BCM2835 ARM mailbox 1 constants
BCM2835_MAILBOX1_* BCM2835_MAILBOX1_REGS_BASE
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Currently unknown |
BCM2835 power management, reset controller and watchdog constants
BCM2835_PM_* BCM2835_PM_REGS_BASE = BCM2835_PERIPHERALS_BASE + $100000;
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BCM2835 clock management constants
BCM2835_CM_* BCM2835_CM_REGS_BASE = BCM2835_PERIPHERALS_BASE + $101000;
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BCM2835 PCM clock constants
BCM2835_PCM_CLOCK_* BCM2835_PCM_CLOCK_BASE = BCM2835_PERIPHERALS_BASE + $101098;
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BCM2835 random number generator constants
BCM2835_RNG_* BCM2835_RNG_REGS_BASE = BCM2835_PERIPHERALS_BASE + $104000;
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BCM2835 GPIO constants
BCM2835_GPIO_* | See Section 6 | |
BCM2835_GPIO_REGS_BASE = BCM2835_PERIPHERALS_BASE + $200000;
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BCM2835 UART0 (PL011) constants
BCM2835_PL011_* | See Section 13 | |
BCM2835_PL011_REGS_BASE = BCM2835_PERIPHERALS_BASE + $201000;
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BCM2835 MMCI0 constants
BCM2835_MMCI0_* BCM2835_MMCI0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $202000;
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BCM2835 PCM / I2S audio constants
BCM2835_PCM_* | See Section 8 | |
BCM2835_PCM_REGS_BASE = BCM2835_PERIPHERALS_BASE + $203000;
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BCM2835 SPI0 constants
BCM2835_SPI0_* | See Section 10 | |
BCM2835_SPI0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $204000;
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BCM2835 BSC0 (I2C) constants
BCM2835_BSC0_* | See Section 3 | |
BCM2835_BSC0_REGS_BASE = BCM2835_PERIPHERALS_BASE + $205000;
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BCM2835 PWM constants
BCM2835_PWM_* | See Section 9 | |
BCM2835_PWM_REGS_BASE = BCM2835_PERIPHERALS_BASE + $20C000;
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BCM2835 I2C/SPI slave constants
BCM2835_I2CSPI_* | See Section 11 | |
BCM2835_I2CSPI_REGS_BASE = BCM2835_PERIPHERALS_BASE + $214000;
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BCM2835 AUX (UART1, SPI1 and SPI2) constants
BCM2835_AUX_* | See Section 2 | |
BCM2835_AUX_REGS_BASE = BCM2835_PERIPHERALS_BASE + $215000;
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BCM2835 SD host controller constants
BCM2835_SDHCI_* | See Section 5 | |
BCM2835_SDHCI_REGS_BASE = BCM2835_PERIPHERALS_BASE + $300000;
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BCM2835 SMI constants
BCM2835_SMI_* BCM2835_SMI_REGS_BASE = BCM2835_PERIPHERALS_BASE + $600000;
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BCM2835 BSC1 (I2C) constants
BCM2835_BSC1_* | See Section 3 | |
BCM2835_BSC1_REGS_BASE = BCM2835_PERIPHERALS_BASE + $804000;
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BCM2835 BSC2 (I2C) constants
BCM2835_BSC2_* | See Section 3 | |
| Note: BSC2 master is used dedicated with the HDMI interface and should not be used | |
BCM2835_BSC2_REGS_BASE = BCM2835_PERIPHERALS_BASE + $805000;
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BCM2835 USB constants
BCM2835_USB_* | See Section 15 | |
BCM2835_USB_REGS_BASE = BCM2835_PERIPHERALS_BASE + $980000;
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BCM2835 V3D constants
BCM2835_V3D_* BCM2835_V3D_REGS_BASE = BCM2835_PERIPHERALS_BASE + $C00000;
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BCM2835 DMA controller constants
BCM2835_DMA15_* | Channel 15 (See Section 4) | |
BCM2835_DMA15_REGS_BASE = BCM2835_PERIPHERALS_BASE + $E05000;
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BCM2835 IRQ peripheral constants
BCM2835_IRQ_* | IRQs 0-63 are those shared between the GPU and CPU, IRQs 64+ are CPU-specific | |
| IRQs 0 to 31 appear in the IRQ_pending_1 register | |
| System Timer | |
BCM2835_IRQ_SYSTEM_TIMER_0 = 0;
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Already used by the VideoCore GPU (Do not use) |
BCM2835_IRQ_SYSTEM_TIMER_1 = 1;
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BCM2835_IRQ_SYSTEM_TIMER_2 = 2;
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Already used by the VideoCore GPU (Do not use) |
BCM2835_IRQ_SYSTEM_TIMER_3 = 3;
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| Codec | |
BCM2835_IRQ_CODEC0 = 4;
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BCM2835_IRQ_CODEC1 = 5;
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BCM2835_IRQ_CODEC2 = 6;
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| JPEG | |
BCM2835_IRQ_JPEG = 7;
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Also available as IRQ 74 in the IRQ_basic_pending register |
| ISP | |
BCM2835_IRQ_ISP = 8;
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| USB (Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller) | |
BCM2835_IRQ_USB = 9;
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Also available as IRQ 75 in the IRQ_basic_pending register |
| 3D | |
BCM2835_IRQ_3D = 10;
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Also available as IRQ 76 in the IRQ_basic_pending register |
| Transposer | |
BCM2835_IRQ_TRANSPOSER = 11;
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| Multicore Sync | |
BCM2835_IRQ_MULTICORESYNC0 = 12;
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BCM2835_IRQ_MULTICORESYNC1 = 13;
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BCM2835_IRQ_MULTICORESYNC2 = 14;
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BCM2835_IRQ_MULTICORESYNC3 = 15;
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| DMA | |
BCM2835_IRQ_DMA0 = 16;
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BCM2835_IRQ_DMA1 = 17;
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BCM2835_IRQ_DMA2 = 18;
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Also available as IRQ 77 in the IRQ_basic_pending register |
BCM2835_IRQ_DMA3 = 19;
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Also available as IRQ 78 in the IRQ_basic_pending register |
BCM2835_IRQ_DMA4 = 20;
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BCM2835_IRQ_DMA5 = 21;
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BCM2835_IRQ_DMA6 = 22;
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BCM2835_IRQ_DMA7 = 23;
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BCM2835_IRQ_DMA8 = 24;
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BCM2835_IRQ_DMA9 = 25;
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BCM2835_IRQ_DMA10 = 26;
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BCM2835_IRQ_DMA11_14 = 27;
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BCM2835_IRQ_DMA11 This IRQ is actually shared between DMA channels 11, 12, 13 and 14 |
BCM2835_IRQ_DMA_ALL = 28;
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BCM2835_IRQ_DMA12 This IRQ is triggered by any DMA channel (all channels interrupt to allow DMA FIQ) |
| AUX (UART1, SPI1 and SPI2) | |
BCM2835_IRQ_AUX = 29;
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| ARM | |
BCM2835_IRQ_ARM = 30;
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| GPUDMA | |
BCM2835_IRQ_GPUDMA = 31;
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| IRQs 32 to 63 appear in the IRQ_pending_2 register | |
| Hostport | |
BCM2835_IRQ_HOSTPORT = 32;
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| Videoscaler | |
BCM2835_IRQ_VIDEOSCALER = 33;
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| CCP2TX | |
BCM2835_IRQ_CCP2TX = 34;
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| SDC | |
BCM2835_IRQ_SDC = 35;
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| DSI0 | |
BCM2835_IRQ_DSI0 = 36;
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| AVE | |
BCM2835_IRQ_AVE = 37;
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| CAM | |
BCM2835_IRQ_CAM0 = 38;
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BCM2835_IRQ_CAM1 = 39;
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| HDMI | |
BCM2835_IRQ_HDMI0 = 40;
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BCM2835_IRQ_HDMI1 = 41;
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| Pixelvalve | |
BCM2835_IRQ_PIXELVALVE1 = 42;
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| I2C / SPI Slave | |
BCM2835_IRQ_I2CSPI = 43;
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| DSI1 | |
BCM2835_IRQ_DSI1 = 44;
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| PWA | |
BCM2835_IRQ_PWA0 = 45;
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BCM2835_IRQ_PWA1 = 46;
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| CPR | |
BCM2835_IRQ_CPR = 47;
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| SMI | |
BCM2835_IRQ_SMI = 48;
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| GPIO | |
BCM2835_IRQ_GPIO_0 = 49;
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Bank0 |
BCM2835_IRQ_GPIO_1 = 50;
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Bank1 |
BCM2835_IRQ_GPIO_2 = 51;
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Bank2 (Non existent in BCM2835) |
BCM2835_IRQ_GPIO_ALL = 52;
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BCM2835_IRQ_GPIO_3 Any Bank (all banks interrupt to allow GPIO FIQ) |
| I2C | |
BCM2835_IRQ_I2C = 53;
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Also available as IRQ 79 in the IRQ_basic_pending register |
| SPI | |
BCM2835_IRQ_SPI = 54;
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Also available as IRQ 80 in the IRQ_basic_pending register |
| I2S PCM sound | |
BCM2835_IRQ_I2SPCM = 55;
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Also available as IRQ 81 in the IRQ_basic_pending register |
| SDIO | |
BCM2835_IRQ_SDIO = 56;
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Also available as IRQ 82 in the IRQ_basic_pending register |
| PL011 UART | |
BCM2835_IRQ_PL011 = 57;
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Also available as IRQ 83 in the IRQ_basic_pending register |
| Slimbus | |
BCM2835_IRQ_SLIMBUS = 58;
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| VEC | |
BCM2835_IRQ_VEC = 59;
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| CPG | |
BCM2835_IRQ_CPG = 60;
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| RNG | |
BCM2835_IRQ_RNG = 61;
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| SD card host controller (EMMC) | |
BCM2835_IRQ_SDHCI = 62;
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Also available as IRQ 84 in the IRQ_basic_pending register |
| AVSPMON | |
BCM2835_IRQ_AVSPMON = 63;
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| IRQs 64 to 84 appear in the IRQ_basic_pending register | |
| ARM Timer | |
BCM2835_IRQ_ARM_TIMER = 64;
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ARM IRQ 0 |
| ARM Mailbox | |
BCM2835_IRQ_ARM_MAILBOX = 65;
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ARM IRQ 1 |
| ARM Doorbell | |
BCM2835_IRQ_ARM_DOORBELL0 = 66;
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ARM IRQ 2 |
BCM2835_IRQ_ARM_DOORBELL1 = 67;
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ARM IRQ 3 |
| ARM GPU Halted | |
BCM2835_IRQ_ARM_GPU0HALTED = 68;
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ARM IRQ 4 |
BCM2835_IRQ_ARM_GPU1HALTED = 69;
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ARM IRQ 5 |
| ARM Illegal Access | |
BCM2835_IRQ_ARM_ILLEGALTYPE0 = 70;
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ARM IRQ 6 |
BCM2835_IRQ_ARM_ILLEGALTYPE1 = 71;
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ARM IRQ 7 |
| ARM Pending | |
BCM2835_IRQ_ARM_PENDING0 = 72;
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ARM IRQ 8 |
BCM2835_IRQ_ARM_PENDING1 = 73;
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ARM IRQ 9 |
| ARM JPEG | |
BCM2835_IRQ_ARM_JPEG = 74;
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ARM IRQ 10 |
| ARM USB | |
BCM2835_IRQ_ARM_USB = 75;
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ARM IRQ 11 |
| ARM 3D | |
BCM2835_IRQ_ARM_3D = 76;
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ARM IRQ 12 |
| ARM DMA | |
BCM2835_IRQ_ARM_DMA2 = 77;
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ARM IRQ 13 |
BCM2835_IRQ_ARM_DMA3 = 78;
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ARM IRQ 14 |
| ARM I2C | |
BCM2835_IRQ_ARM_I2C = 79;
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ARM IRQ 15 |
| ARM SPI | |
BCM2835_IRQ_ARM_SPI = 80;
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ARM IRQ 16 |
| ARM I2SPCM | |
BCM2835_IRQ_ARM_I2SPCM = 81;
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ARM IRQ 17 |
| ARM SDIO | |
BCM2835_IRQ_ARM_SDIO = 82;
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ARM IRQ 18 |
| ARM PL011 UART | |
BCM2835_IRQ_ARM_PL011 = 83;
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ARM IRQ 19 |
| ARM SDHCI | |
BCM2835_IRQ_ARM_SDHCI = 84;
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ARM IRQ 20 |
| IRQs 85 to 95 (ARM IRQs 21 to 31) are not assigned | |
| Number of IRQs shared between the GPU and ARM (These correspond to the IRQs that show up in the IRQ_pending_1 and IRQ_pending_2 registers) | |
BCM2835_GPU_IRQ_COUNT = 64;
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| Number of ARM specific IRQs (These correspond to IRQs that show up in the first 8 bits of IRQ_basic_pending) | |
BCM2835_ARM_IRQ_COUNT = 32;
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Previously 8 |
| Total number of IRQs available | |
BCM2835_IRQ_COUNT = BCM2835_GPU_IRQ_COUNT + BCM2835_ARM_IRQ_COUNT;
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72 |
| Total number of FIQs available | |
BCM2835_FIQ_COUNT = 1;
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BCM2835 system timer frequency constants
BCM2835_SYSTEM_TIMER_* BCM2835_SYSTEM_TIMER_FREQUENCY = 1000000;
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Default clock frequency of the BCM2835 System Timer (1MHz) |
| System Timer Control/Status register bits (See Section 12) | |
BCM2835_SYSTEM_TIMER_CS_0 = (1 shl 0);
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Already used by the VideoCore GPU (Do not use) |
BCM2835_SYSTEM_TIMER_CS_1 = (1 shl 1);
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BCM2835_SYSTEM_TIMER_CS_2 = (1 shl 2);
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Already used by the VideoCore GPU (Do not use) |
BCM2835_SYSTEM_TIMER_CS_3 = (1 shl 3);
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BCM2835 DMA control and status constants
BCM2835_DMA_CS_* | See Section 4 | |
BCM2835_DMA_CS_ACTIVE = (1 shl 0);
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Activate the DMA (This bit enables the DMA. The DMA will start if this bit is set and the CB_ADDR is non zero. The DMA transfer can be paused and resumed by clearing, then setting it again) |
BCM2835_DMA_CS_END = (1 shl 1);
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DMA End Flag (Set when the transfer described by the current control block is complete. Write 1 to clear) |
BCM2835_DMA_CS_INT = (1 shl 2);
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Interrupt Status (This is set when the transfer for the CB ends and INTEN is set to 1. Write 1 to clear) |
BCM2835_DMA_CS_DREQ = (1 shl 3);
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DREQ State (Indicates the state of the selected DREQ (Data Request) signal, ie. the DREQ selected by the PERMAP field of the transfer info) |
BCM2835_DMA_CS_PAUSED = (1 shl 4);
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DMA Paused State (Indicates if the DMA is currently paused and not transferring data) |
BCM2835_DMA_CS_DREQ_PAUSED = (1 shl 5);
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DMA Paused by DREQ State (Indicates if the DMA is currently paused and not transferring data due to the DREQ being inactive) |
BCM2835_DMA_CS_WAITING_FOR_OUTSTANDING_WRITES = (1 shl 6);
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DMA is Waiting for the Last Write to be Received (Indicates if the DMA is currently waiting for any outstanding writes to be received, and is not transferring data) |
| Bit 7 Reserved - Write as 0, read as don't care | |
BCM2835_DMA_CS_ERROR = (1 shl 8);
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DMA Error (Indicates if the DMA has detected an error) |
| Bits 9:15 Reserved - Write as 0, read as don't care | |
BCM2835_DMA_CS_PRIORITY = ($F shl 16);
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AXI Priority Level (Sets the priority of normal AXI bus transactions. Zero is the lowest priority) |
BCM2835_DMA_CS_PANIC_PRIORITY = ($F shl 20);
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AXI Panic Priority Level (Sets the priority of panicking AXI bus transactions) |
| Bits 24:27 Reserved - Write as 0, read as don't care | |
BCM2835_DMA_CS_WAIT_FOR_OUTSTANDING_WRITES = (1 shl 28);
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Wait for outstanding writes (When set to 1, the DMA will keep a tally of the AXI writes going out and the write responses coming in) |
BCM2835_DMA_CS_DISDEBUG = (1 shl 29);
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Disable debug pause signal (When set to 1, the DMA will not stop when the debug pause signal is asserted) |
BCM2835_DMA_CS_ABORT = (1 shl 30);
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Abort DMA (Writing a 1 to this bit will abort the current DMA CB. The DMA will load the next CB and attempt to continue. The bit cannot be read, and will self clear) |
BCM2835_DMA_CS_RESET = (1 shl 31);
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DMA Channel Reset (Writing a 1 to this bit will reset the DMA. The bit cannot be read, and will self clear) |
BCM2835_DMA_CS_PRIORITY_DEFAULT = 0;
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BCM2835 DMA transfer information constants
BCM2835_DMA_TI_* | See Section 4 | |
BCM2835_DMA_TI_INTEN = (1 shl 0);
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Interrupt Enable (1 = Generate an interrupt when the transfer described by the current Control Block completes) |
BCM2835_DMA_TI_2DMODE = (1 shl 1);
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2D Mode (1 = 2D mode interpret the TXFR_LEN register as YLENGTH number of transfers each of XLENGTH, and add the strides to the address after each transfer) |
| Bit 2 Reserved - Write as 0, read as don't care | |
BCM2835_DMA_TI_WAIT_RESP = (1 shl 3);
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Wait for a Write Response (When set this makes the DMA wait until it receives the AXI write response for each write. This ensures that multiple writes cannot get stacked in the AXI bus pipeline) |
BCM2835_DMA_TI_DEST_INC = (1 shl 4);
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Destination Address Increment (1 = Destination address increments after each write The address will increment by 4, if DEST_WIDTH=0 else by 32) |
BCM2835_DMA_TI_DEST_WIDTH = (1 shl 5);
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Destination Transfer Width (1 = Use 128-bit destination write width. 0 = Use 32-bit destination write width) |
BCM2835_DMA_TI_DEST_DREQ = (1 shl 6);
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Control Destination Writes with DREQ (1 = The DREQ selected by PERMAP will gate the destination writes) |
BCM2835_DMA_TI_DEST_IGNORE = (1 shl 7);
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Ignore Writes (1 = Do not perform destination writes. 0 = Write data to destination) |
BCM2835_DMA_TI_SRC_INC = (1 shl 8);
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Source Address Increment (1 = Source address increments after each read. The address will increment by 4, if S_WIDTH=0 else by 32) |
BCM2835_DMA_TI_SRC_WIDTH = (1 shl 9);
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Source Transfer Width (1 = Use 128-bit source read width. 0 = Use 32-bit source read width) |
BCM2835_DMA_TI_SRC_DREQ = (1 shl 10);
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Control Source Reads with DREQ (1 = The DREQ selected by PERMAP will gate the source reads) |
BCM2835_DMA_TI_SRC_IGNORE = (1 shl 11);
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Ignore Reads (1 = Do not perform source reads. In addition, destination writes will zero all the write strobes. This is used for fast cache fill operations) |
BCM2835_DMA_TI_BURST_LENGTH = ($F shl 12);
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Burst Transfer Length (Indicates the burst length of the DMA transfers) |
BCM2835_DMA_TI_PERMAP = ($1F shl 16);
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Peripheral Mapping (Indicates the peripheral number (1-31) whose ready signal shall be used to control the rate of the transfers) |
BCM2835_DMA_TI_WAITS = ($3E shl 21);
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Add Wait Cycles (This slows down the DMA throughput by setting the number of dummy cycles burnt after each DMA read or write operation is completed) |
BCM2835_DMA_TI_NO_WIDE_BURSTS = (1 shl 26);
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Don't Do wide writes as a 2 beat burst (This prevents the DMA from issuing wide writes as 2 beat AXI bursts. This is an inefficient access mode, so the default is to use the bursts) |
| Bits 27:31 Reserved - Write as 0, read as don't care | |
| Note: BCM2835_DMA_TI_2DMODE, BCM2835_DMA_TI_DEST_IGNORE, BCM2835_DMA_TI_SRC_IGNORE and BCM2835_DMA_TI_NO_WIDE_BURSTS not available on DMA Lite channels | |
BCM2835_DMA_TI_PERMAP_SHIFT = 16;
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BCM2835_DMA_TI_BURST_LENGTH_SHIFT = 12;
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BCM2835_DMA_TI_BURST_LENGTH_DEFAULT = 0;
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BCM2835 DMA transfer length constants
BCM2835_DMA_TXFR_LEN_* | See Section 4 | |
BCM2835_DMA_TXFR_LEN_XLENGTH = ($FFFF shl 0);
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Transfer Length in bytes |
BCM2835_DMA_TXFR_LEN_YLENGTH = ($3FFF shl 16);
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When in 2D mode, This is the Y transfer length, indicating how many xlength transfers are performed. When in normal linear mode this becomes the top bits of the XLENGTH |
| Note: BCM2835_DMA_TXFR_LEN_YLENGTH not available on DMA Lite channels | |
BCM2835 DMA 2D stride constants
BCM2835_DMA_STRIDE_* | See Section 4 | |
BCM2835_DMA_STRIDE_S_STRIDE = ($FFFF shl 0);
|
Destination Stride (2D Mode) (Signed (2 s complement) byte increment to apply to the destination address at the end of each row in 2D mode) |
BCM2835_DMA_STRIDE_D_STRIDE = ($FFFF shl 16);
|
Source Stride (2D Mode) (Signed (2 s complement) byte increment to apply to the source address at the end of each row in 2D mode) |
| Note: BCM2835_DMA_STRIDE_S_STRIDE and BCM2835_DMA_STRIDE_D_STRIDE not available on DMA Lite channels | |
BCM2835 DMA debug constants
BCM2835_DMA_DEBUG_* | See Section 4 | |
BCM2835_DMA_DEBUG_READ_LAST_NOT_SET_ERROR = (1 shl 0);
|
Read Last Not Set Error |
BCM2835_DMA_DEBUG_FIFO_ERROR = (1 shl 1);
|
Fifo Error |
BCM2835_DMA_DEBUG_READ_ERROR = (1 shl 2);
|
Slave Read Response Error |
| Bit 3 Reserved - Write as 0, read as don't care | |
BCM2835_DMA_DEBUG_OUTSTANDING_WRITES = ($F shl 4);
|
DMA Outstanding Writes Counter |
BCM2835_DMA_DEBUG_DMA_ID = ($FF shl 8);
|
DMA ID |
BCM2835_DMA_DEBUG_DMA_STATE = ($1FF shl 16);
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DMA State Machine State |
BCM2835_DMA_DEBUG_VERSION = (7 shl 25);
|
DMA Version |
BCM2835_DMA_DEBUG_LITE = (1 shl 28);
|
DMA Lite |
| Bits 29:31 Reserved - Write as 0, read as don't care | |
BCM2835 DMA engine interrupt status constants
BCM2835_DMA_INT_STATUS_* | See Section 4 | |
BCM2835_DMA_INT_STATUS_0 = (1 shl 0);
|
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BCM2835_DMA_INT_STATUS_1 = (1 shl 1);
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BCM2835_DMA_INT_STATUS_2 = (1 shl 2);
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BCM2835_DMA_INT_STATUS_3 = (1 shl 3);
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BCM2835_DMA_INT_STATUS_4 = (1 shl 4);
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BCM2835_DMA_INT_STATUS_5 = (1 shl 5);
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BCM2835_DMA_INT_STATUS_6 = (1 shl 6);
|
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BCM2835_DMA_INT_STATUS_7 = (1 shl 7);
|
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BCM2835_DMA_INT_STATUS_8 = (1 shl 8);
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BCM2835_DMA_INT_STATUS_9 = (1 shl 9);
|
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BCM2835_DMA_INT_STATUS_10 = (1 shl 10);
|
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BCM2835_DMA_INT_STATUS_11 = (1 shl 11);
|
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BCM2835_DMA_INT_STATUS_12 = (1 shl 12);
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BCM2835_DMA_INT_STATUS_13 = (1 shl 13);
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BCM2835_DMA_INT_STATUS_14 = (1 shl 14);
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BCM2835_DMA_INT_STATUS_15 = (1 shl 15);
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BCM2835 DMA engine enable constants
BCM2835_DMA_ENABLE_* | See Section 4 | |
BCM2835_DMA_ENABLE_0 = (1 shl 0);
|
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BCM2835_DMA_ENABLE_1 = (1 shl 1);
|
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BCM2835_DMA_ENABLE_2 = (1 shl 2);
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BCM2835_DMA_ENABLE_3 = (1 shl 3);
|
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BCM2835_DMA_ENABLE_4 = (1 shl 4);
|
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BCM2835_DMA_ENABLE_5 = (1 shl 5);
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BCM2835_DMA_ENABLE_6 = (1 shl 6);
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BCM2835_DMA_ENABLE_7 = (1 shl 7);
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BCM2835_DMA_ENABLE_8 = (1 shl 8);
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BCM2835_DMA_ENABLE_9 = (1 shl 9);
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BCM2835_DMA_ENABLE_10 = (1 shl 10);
|
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BCM2835_DMA_ENABLE_11 = (1 shl 11);
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BCM2835_DMA_ENABLE_12 = (1 shl 12);
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BCM2835_DMA_ENABLE_13 = (1 shl 13);
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BCM2835_DMA_ENABLE_14 = (1 shl 14);
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BCM2835 DMA engine DREQ peripheral constants
BCM2835_DMA_DREQ_* | See Section 4 | |
BCM2835_DMA_DREQ_NONE = 0;
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BCM2835_DMA_DREQ_DSI0 = 1;
|
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BCM2835_DMA_DREQ_PCMTX = 2;
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BCM2835_DMA_DREQ_PCMRX = 3;
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BCM2835_DMA_DREQ_SMI = 4;
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BCM2835_DMA_DREQ_PWM = 5;
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BCM2835_DMA_DREQ_SPITX = 6;
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BCM2835_DMA_DREQ_SPIRX = 7;
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BCM2835_DMA_DREQ_BSCSPITX = 8;
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BCM2835_DMA_DREQ_BSCSPIRX = 9;
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BCM2835_DMA_DREQ_RESERVED1 = 10;
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BCM2835_DMA_DREQ_EMMC = 11;
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BCM2835_DMA_DREQ_UARTTX = 12;
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BCM2835_DMA_DREQ_SDHOST = 13;
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BCM2835_DMA_DREQ_UARTRX = 14;
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BCM2835_DMA_DREQ_DSI1 = 15;
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BCM2835_DMA_DREQ_SLIMBUS_MCTX = 16;
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BCM2835_DMA_DREQ_HDMI = 17;
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BCM2835_DMA_DREQ_SLIMBUS_MCRX = 18;
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BCM2835_DMA_DREQ_SLIMBUS_DC0 = 19;
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BCM2835_DMA_DREQ_SLIMBUS_DC1 = 20;
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BCM2835_DMA_DREQ_SLIMBUS_DC2 = 21;
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BCM2835_DMA_DREQ_SLIMBUS_DC3 = 22;
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BCM2835_DMA_DREQ_SLIMBUS_DC4 = 23;
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BCM2835_DMA_DREQ_SCALER_FIFO0 = 24;
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BCM2835_DMA_DREQ_SCALER_FIFO1 = 25;
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|
BCM2835_DMA_DREQ_SCALER_FIFO2 = 26;
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BCM2835_DMA_DREQ_SLIMBUS_DC5 = 27;
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BCM2835_DMA_DREQ_SLIMBUS_DC6 = 28;
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|
BCM2835_DMA_DREQ_SLIMBUS_DC7 = 29;
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|
BCM2835_DMA_DREQ_SLIMBUS_DC8 = 30;
|
|
BCM2835_DMA_DREQ_SLIMBUS_DC9 = 31;
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BCM2835 BSC (I2C0/1/2) control constants
BCM2835_BSC_C_* | See Section 3.2 | |
BCM2835_BSC_C_I2CEN = (1 shl 15);
|
I2C Enable (0 = BSC controller is disabled / 1 = BSC controller is enabled) |
BCM2835_BSC_C_INTR = (1 shl 10);
|
INTR Interrupt on RX (0 = Don t generate interrupts on RXR condition / 1 = Generate interrupt while RXR = 1) |
BCM2835_BSC_C_INTT = (1 shl 9);
|
INTT Interrupt on TX (0 = Don t generate interrupts on TXW condition / 1 = Generate interrupt while TXW = 1) |
BCM2835_BSC_C_INTD = (1 shl 8);
|
INTD Interrupt on DONE (0 = Don t generate interrupts on DONE condition / 1 = Generate interrupt while DONE = 1) |
BCM2835_BSC_C_ST = (1 shl 7);
|
ST Start Transfer (0 = No action / 1 = Start a new transfer. One shot operation. Read back as 0) |
BCM2835_BSC_C_CLEAR = (1 shl 5);
|
CLEAR FIFO Clear (00 = No action / x1 = Clear FIFO. One shot operation / 1x = Clear FIFO. One shot operation) |
BCM2835_BSC_C_READ = (1 shl 0);
|
READ Read Transfer (0 = Write Packet Transfer / 1 = Read Packet Transfer) |
BCM2835 BSC (I2C0/1/2) status constants
BCM2835_BSC_S_* | See Section 3.2 | |
BCM2835_BSC_S_CLKT = (1 shl 9);
|
CLKT Clock Stretch Timeout (0 = No errors detected. 1 = Slave has held the SCL signal low (clock stretching) for longer and that specified in the I2CCLKT register Cleared by writing 1 to the field) |
BCM2835_BSC_S_ERR = (1 shl 8);
|
ERR ACK Error (0 = No errors detected. 1 = Slave has not acknowledged its address. Cleared by writing 1 to the field) |
BCM2835_BSC_S_RXF = (1 shl 7);
|
RXF - FIFO Full (0 = FIFO is not full. 1 = FIFO is full. If a read is underway, no further serial data will be received until data is read from FIFO) |
BCM2835_BSC_S_TXE = (1 shl 6);
|
TXE - FIFO Empty (0 = FIFO is not empty. 1 = FIFO is empty. If a write is underway, no further serial data can be transmitted until data is written to the FIFO) |
BCM2835_BSC_S_RXD = (1 shl 5);
|
RXD - FIFO contains Data (0 = FIFO is empty. 1 = FIFO contains at least 1 byte. Cleared by reading sufficient data from FIFO) |
BCM2835_BSC_S_TXD = (1 shl 4);
|
TXD - FIFO can accept Data (0 = FIFO is full. The FIFO cannot accept more data. 1 = FIFO has space for at least 1 byte) |
BCM2835_BSC_S_RXR = (1 shl 3);
|
RXR - FIFO needs Reading (full) (0 = FIFO is less than full and a read is underway. 1 = FIFO is or more full and a read is underway. Cleared by reading sufficient data from the FIFO) |
BCM2835_BSC_S_TXW = (1 shl 2);
|
TXW - FIFO needs Writing (full) (0 = FIFO is at least full and a write is underway (or sufficient data to send). 1 = FIFO is less then full and a write is underway. Cleared by writing sufficient data to the FIFO) |
BCM2835_BSC_S_DONE = (1 shl 1);
|
DONE Transfer Done (0 = Transfer not completed. 1 = Transfer complete. Cleared by writing 1 to the field) |
BCM2835_BSC_S_TA = (1 shl 0);
|
TA Transfer Active (0 = Transfer not active. 1 = Transfer active) |
BCM2835 BSC (I2C0/1/2) data length constants
BCM2835_BSC_DLEN_* | See Section 3.2 | |
BCM2835_BSC_DLEN_MASK = $FFFF;
|
Data Length. (Writing to DLEN specifies the number of bytes to be transmitted/received. Reading from DLEN when TA = 1 or DONE = 1, returns the number of bytes still to be transmitted or received) |
BCM2835 BSC (I2C0/1/2) slave address constants
BCM2835_BSC_A_* | See Section 3.2 | |
BCM2835_BSC_A_MASK = $7F;
|
Slave Address |
BCM2835 BSC (I2C0/1/2) data FIFO constants
BCM2835_BSC_FIFO_* | See Section 3.2 | |
BCM2835_BSC_FIFO_MASK = $FF;
|
Writes to the register write transmit data to the FIFO. Reads from register reads received data from the FIFO |
BCM2835_BSC_FIFO_SIZE = 16;
|
|
BCM2835 BSC (I2C0/1/2) clock divider constants
BCM2835_BSC_CDIV_* | See Section 3.2 | |
BCM2835_BSC_CDIV_MASK = $FFFF;
|
Clock Divider (SCL = core clock / CDIV) (CDIV is always rounded down to an even number) |
BCM2835 BSC (I2C0/1/2) data delay constants
BCM2835_BSC_DEL_* | See Section 3.2 | |
BCM2835_BSC_DEL_FEDL_MASK = ($FFFF shl 16);
|
FEDL Falling Edge Delay (Number of core clock cycles to wait after the falling edge of SCL before outputting next bit of data) |
BCM2835_BSC_DEL_REDL_MASK = ($FFFF shl 0);
|
REDL Rising Edge Delay (Number of core clock cycles to wait after the rising edge of SCL before reading the next bit of data) |
BCM2835 BSC (I2C0/1/2) clock stretch timeout constants
BCM2835_BSC_CLKT_TOUT_* | See Section 3.2 | |
BCM2835_BSC_CLKT_TOUT_MASK = $FFFF;
|
TOUT Clock Stretch Timeout Value (Number of SCL clock cycles to wait after the rising edge of SCL before deciding that the slave is not responding) |
BCM2835 SPI0 constants
BCM2835_SPI0_* | See Section 10.5 | |
BCM2835_SPI0_CS_LEN_LONG = (1 shl 25);
|
Enable Long data word in Lossi mode if DMA_LEN is set (0 = writing to the FIFO will write a single byte / 1 = writing to the FIFO will write a 32 bit word) |
BCM2835_SPI0_CS_DMA_LEN = (1 shl 24);
|
Enable DMA mode in Lossi mode |
BCM2835_SPI0_CS_CSPOL2 = (1 shl 23);
|
Chip Select 2 Polarity (0 = Chip select is active low / 1 = Chip select is active high) |
BCM2835_SPI0_CS_CSPOL1 = (1 shl 22);
|
Chip Select 1 Polarity (0 = Chip select is active low / 1 = Chip select is active high) |
BCM2835_SPI0_CS_CSPOL0 = (1 shl 21);
|
Chip Select 0 Polarity (0 = Chip select is active low / 1 = Chip select is active high) |
BCM2835_SPI0_CS_RXF = (1 shl 20);
|
RXF - RX FIFO Full (0 = RXFIFO is not full / 1 = RX FIFO is full. No further serial data will be sent/received until data is read from FIFO) |
BCM2835_SPI0_CS_RXR = (1 shl 19);
|
RXR RX FIFO needs Reading (full) (0 = RX FIFO is less than full (or not active TA = 0) / 1 = RX FIFO is or more full. Cleared by reading sufficient data from the RX FIFO or setting TA to 0) |
BCM2835_SPI0_CS_TXD = (1 shl 18);
|
TXD TX FIFO can accept Data (0 = TX FIFO is full and so cannot accept more data / 1 = TX FIFO has space for at least 1 byte) |
BCM2835_SPI0_CS_RXD = (1 shl 17);
|
RXD RX FIFO contains Data (0 = RX FIFO is empty / 1 = RX FIFO contains at least 1 byte) |
BCM2835_SPI0_CS_DONE = (1 shl 16);
|
DONE Transfer Done (0 = Transfer is in progress (or not active TA = 0) / 1 = Transfer is complete. Cleared by writing more data to the TX FIFO or setting TA to 0) |
BCM2835_SPI0_CS_TE_EN = (1 shl 15);
|
Unused |
BCM2835_SPI0_CS_LMONO = (1 shl 14);
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Unused |
BCM2835_SPI0_CS_LEN = (1 shl 13);
|
LEN LoSSI enable (0 = The serial interface will behave as an SPI master / 1 = The serial interface will behave as a LoSSI master) |
BCM2835_SPI0_CS_REN = (1 shl 12);
|
REN Read Enable. If this bit is set, the SPI peripheral will be able to send data to this device (0 = We intend to write to the SPI peripheral / 1 = We intend to read from the SPI peripheral) |
BCM2835_SPI0_CS_ADCS = (1 shl 11);
|
ADCS Automatically Deassert Chip Select (0 = Don t automatically deassert chip select at the end of a DMA transfer chip select is manually controlled by software. / 1 = Automatically deassert chip select at the end of a DMA transfer as determined by SPIDLEN) |
BCM2835_SPI0_CS_INTR = (1 shl 10);
|
INTR Interrupt on RXR (0 = Don t generate interrupts on RX FIFO condition / 1 = Generate interrupt while RXR = 1) |
BCM2835_SPI0_CS_INTD = (1 shl 9);
|
INTD Interrupt on Done (0 = Don t generate interrupt on transfer complete / 1 = Generate interrupt when DONE = 1) |
BCM2835_SPI0_CS_DMAEN = (1 shl 8);
|
DMAEN DMA Enable (0 = No DMA requests will be issued / 1 = Enable DMA operation. Peripheral generates data requests. These will be taken in four-byte words until the SPIDLEN has been reached |
BCM2835_SPI0_CS_TA = (1 shl 7);
|
Transfer Active (0 = Transfer not active / 1 = Transfer active) |
BCM2835_SPI0_CS_CSPOL = (1 shl 6);
|
Chip Select Polarity (0 = Chip select lines are active low / 1 = Chip select lines are active high |
BCM2835_SPI0_CS_CLEAR_RX = (1 shl 5);
|
CLEAR FIFO Clear (00 = No action / x1 = Clear TX FIFO. One shot operation / 1x = Clear RX FIFO. One shot operation) |
BCM2835_SPI0_CS_CLEAR_TX = (1 shl 4);
|
As above |
BCM2835_SPI0_CS_CPOL = (1 shl 3);
|
Clock Polarity (0 = Rest state of clock = low / 1 = Rest state of clock = high) |
BCM2835_SPI0_CS_CPHA = (1 shl 2);
|
Clock Phase (0 = First SCLK transition at middle of data bit / 1 = First SCLK transition at beginning of data bit) |
BCM2835_SPI0_CS_CS_0 = (0 shl 0);
|
Chip Select (00 = Chip select 0 / 01 = Chip select 1 / 10 = Chip select 2 / 11 = Reserved |
BCM2835_SPI0_CS_CS_1 = (1 shl 0);
|
As above |
BCM2835_SPI0_CS_CS_2 = (2 shl 0);
|
As above |
BCM2835_SPI0_CS_CS_MASK = (3 shl 0);
|
|
BCM2835_SPI0_FIFO_DMA_DATA = $FFFFFFFF;
|
DMA Mode (DMAEN set) If TA is clear, the first 32-bit write to this register will control SPIDLEN and SPICS. Subsequent reads and writes will be taken as four-byte data words to be read/written to the FIFOs |
BCM2835_SPI0_FIFO_IRQ_DATA = $000000FF;
|
Poll/Interrupt Mode (DMAEN clear, TA set) Writes to the register write bytes to TX FIFO. Reads from register read bytes from the RX FIFO |
BCM2835_SPI0_CLK_CDIV = $0000FFFF;
|
Clock Divider (SCLK = Core Clock / CDIV) If CDIV is set to 0, the divisor is 65536. The divisor must be a multiple of 2. Odd numbers rounded down. The maximum SPI clock rate is of the APB clock |
BCM2835_SPI0_DLEN_LEN = $0000FFFF;
|
Data Length. The number of bytes to transfer. This field is only valid for DMA mode (DMAEN set) and controls how many bytes to transmit (and therefore receive) |
BCM2835_SPI0_LTOH_TOH = $0000000F;
|
This sets the Output Hold delay in APB clocks (A value of 0 causes a 1 clock delay) |
BCM2835_SPI0_DC_RPANIC = ($FF shl 24);
|
DMA Read Panic Threshold (Generate the Panic signal to the RX DMA engine whenever the RX FIFO level is greater than this amount) |
BCM2835_SPI0_DC_RDREQ = ($FF shl 16);
|
DMA Read Request Threshold (Generate A DREQ to the RX DMA engine whenever the RX FIFO level is greater than this amount) (RX DREQ is also generated if thetransfer has finished but the RXFIFO isn't empty) |
BCM2835_SPI0_DC_TPANIC = ($FF shl 8);
|
DMA Write Panic Threshold (Generate the Panic signal to the TX DMA engine whenever the TX FIFO level is less than or equal to this amount) |
BCM2835_SPI0_DC_TDREQ = ($FF shl 0);
|
DMA Write Request Threshold (Generate a DREQ signal to the TX DMA engine whenever the TX FIFO level is less than or equal to this amount) |
BCM2835 PWM control constants
BCM2835_PWM_CTL_* | See Section 9.6 | |
BCM2835_PWM_CTL_MSEN2 = (1 shl 15);
|
Channel 2 M/S Enable (0: PWM algorithm is used / 1: M/S transmission is used) |
| Bit 14 Reserved - Write as 0, read as don't care | |
BCM2835_PWM_CTL_USEF2 = (1 shl 13);
|
Channel 2 Use Fifo (0: Data register is transmitted / 1: Fifo is used for transmission) |
BCM2835_PWM_CTL_POLA2 = (1 shl 12);
|
Channel 2 Polarity (0 : 0=low 1=high / 1: 1=low 0=high) |
BCM2835_PWM_CTL_SBIT2 = (1 shl 11);
|
Channel 2 Silence Bit (Defines the state of the output when no transmission takes place) |
BCM2835_PWM_CTL_RPTL2 = (1 shl 10);
|
Channel 2 Repeat Last Data (0: Transmission interrupts when FIFO is empty / 1: Last data in FIFO is transmitted repetedly until FIFO is not empty) |
BCM2835_PWM_CTL_MODE2 = (1 shl 9);
|
Channel 2 Mode (0: PWM mode / 1: Serialiser mode) |
BCM2835_PWM_CTL_PWEN2 = (1 shl 8);
|
Channel 2 Enable (0: Channel is disabled / 1: Channel is enabled) |
BCM2835_PWM_CTL_MSEN1 = (1 shl 7);
|
Channel 1 M/S Enable (0: PWM algorithm is used / 1: M/S transmission is used) |
BCM2835_PWM_CTL_CLRF1 = (1 shl 6);
|
Clear Fifo (1: Clears FIFO / 0: Has no effect) (This is a single shot operation. This bit always reads 0) |
BCM2835_PWM_CTL_USEF1 = (1 shl 5);
|
Channel 1 Use Fifo (0: Data register is transmitted / 1: Fifo is used for transmission) |
BCM2835_PWM_CTL_POLA1 = (1 shl 4);
|
Channel 1 Polarity (0 : 0=low 1=high / 1: 1=low 0=high) |
BCM2835_PWM_CTL_SBIT1 = (1 shl 3);
|
Channel 1 Silence Bit (Defines the state of the output when no transmission takes place) |
BCM2835_PWM_CTL_RPTL1 = (1 shl 2);
|
Channel 1 Repeat Last Data (0: Transmission interrupts when FIFO is empty / 1: Last data in FIFO is transmitted repetedly until FIFO is not empty) |
BCM2835_PWM_CTL_MODE1 = (1 shl 1);
|
Channel 1 Mode (0: PWM mode / 1: Serialiser mode) |
BCM2835_PWM_CTL_PWEN1 = (1 shl 0);
|
Channel 1 Enable (0: Channel is disabled / 1: Channel is enabled) |
BCM2835 PWM status constants
BCM2835_PWM_STA_* | See Section 9.6 | |
BCM2835_PWM_STA_STA4 = (1 shl 12);
|
Channel 4 State |
BCM2835_PWM_STA_STA3 = (1 shl 11);
|
Channel 3 State |
BCM2835_PWM_STA_STA2 = (1 shl 10);
|
Channel 2 State |
BCM2835_PWM_STA_STA1 = (1 shl 9);
|
Channel 1 State |
BCM2835_PWM_STA_BERR = (1 shl 8);
|
Bus Error Flag |
BCM2835_PWM_STA_GAPO4 = (1 shl 7);
|
Channel 4 Gap Occurred Flag |
BCM2835_PWM_STA_GAPO3 = (1 shl 6);
|
Channel 3 Gap Occurred Flag |
BCM2835_PWM_STA_GAPO2 = (1 shl 5);
|
Channel 2 Gap Occurred Flag |
BCM2835_PWM_STA_GAPO1 = (1 shl 4);
|
Channel 1 Gap Occurred Flag |
BCM2835_PWM_STA_RERR1 = (1 shl 3);
|
Fifo Read Error Flag |
BCM2835_PWM_STA_WERR1 = (1 shl 2);
|
Fifo Write Error Flag |
BCM2835_PWM_STA_EMPT1 = (1 shl 1);
|
Fifo Empty Flag |
BCM2835_PWM_STA_FULL1 = (1 shl 0);
|
Fifo Full Flag |
BCM2835 PWM DMA configuration constants
CM2835_PWM_DMAC_* | See Section 9.6 | |
BCM2835_PWM_DMAC_ENAB = (1 shl 31);
|
DMA Enable (0: DMA disabled / 1: DMA enabled) |
BCM2835_PWM_DMAC_PANIC = ($FF shl 8);
|
DMA Threshold for PANIC signal (Default: 0x7) |
BCM2835_PWM_DMAC_DREQ = ($FF shl 0);
|
DMA Threshold for DREQ signal (Default: 0x7) |
BCM2835 PWM constants
BCM2835_PWM_* BCM2835_PWM_CTL = $00000000;
|
PWM Control |
BCM2835_PWM_STA = $00000004;
|
PWM Status |
BCM2835_PWM_DMAC = $00000008;
|
PWM DMA Configuration |
BCM2835_PWM_RNG1 = $00000010;
|
PWM Channel 1 Range |
BCM2835_PWM_DAT1 = $00000014;
|
PWM Channel 1 Data |
BCM2835_PWM_FIF1 = $00000018;
|
PWM FIFO Input |
BCM2835_PWM_RNG2 = $00000020;
|
PWM Channel 2 Range |
BCM2835_PWM_DAT2 = $00000024;
|
PWM Channel 2 Data |
BCM2835 PL011 UART data constants
BCM2835_PL011_DR_* | See Section 13.4 | |
BCM2835_PL011_DR_OE = (1 shl 11);
|
Overrun error |
BCM2835_PL011_DR_BE = (1 shl 10);
|
Break error |
BCM2835_PL011_DR_PE = (1 shl 9);
|
Parity error |
BCM2835_PL011_DR_FE = (1 shl 8);
|
Framing error |
BCM2835_PL011_DR_DATA = ($FF shl 0);
|
Receive / Transmit data |
BCM2835_PL011_DR_ERROR = BCM2835_PL011_DR_OE or BCM2835_PL011_DR_BE or BCM2835_PL011_DR_PE or BCM2835_PL011_DR_FE;
|
|
BCM2835 PL011 UART receive status / error clear constants
BCM2835_PL011_RSRECR_* | See Section 13.4 | |
BCM2835_PL011_RSRECR_OE = (1 shl 3);
|
Overrun error |
BCM2835_PL011_RSRECR_BE = (1 shl 2);
|
Break error |
BCM2835_PL011_RSRECR_PE = (1 shl 1);
|
Parity error |
BCM2835_PL011_RSRECR_FE = (1 shl 0);
|
Framing error |
BCM2835 PL011 UART flag constants
BCM2835_PL011_FR_* | See Section13.4 | |
BCM2835_PL011_FR_RI = (1 shl 8);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_FR_TXFE = (1 shl 7);
|
Transmit FIFO empty |
BCM2835_PL011_FR_RXFF = (1 shl 6);
|
Receive FIFO full |
BCM2835_PL011_FR_TXFF = (1 shl 5);
|
Transmit FIFO full |
BCM2835_PL011_FR_RXFE = (1 shl 4);
|
Receive FIFO empty |
BCM2835_PL011_FR_BUSY = (1 shl 3);
|
UART busy |
BCM2835_PL011_FR_DCD = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_FR_DSR = (1 shl 1);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_FR_CTS = (1 shl 0);
|
Clear to send (This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW) |
BCM2835 PL011 UART IrDA constants
| See Section 13.4 | |
| This register is disabled, writing to it has no effect and reading returns 0 |
BCM2835 PL011 UART integer baud rate divisor constants
BCM2835_PL011_IBRD_* | See Section 13.4 | |
BCM2835_PL011_IBRD_MASK = ($FFFF shl 0);
|
|
BCM2835 PL011 UART fractional baud rate divisor constants
BCM2835_PL011_FBRD_* | See Section 13.4 | |
BCM2835_PL011_FBRD_MASK = ($3F shl 0);
|
|
BCM2835 PL011 UART line control constants
BCM2835_PL011_LCRH_* | See Section 13.4 | |
BCM2835_PL011_LCRH_SPS = (1 shl 7);
|
Stick parity select |
BCM2835_PL011_LCRH_WLEN = (3 shl 5);
|
Word length |
BCM2835_PL011_LCRH_WLEN8 = (3 shl 5);
|
8 bits |
BCM2835_PL011_LCRH_WLEN7 = (2 shl 5);
|
7 bits |
BCM2835_PL011_LCRH_WLEN6 = (1 shl 5);
|
6 bits |
BCM2835_PL011_LCRH_WLEN5 = (0 shl 5);
|
5 bits |
BCM2835_PL011_LCRH_FEN = (1 shl 4);
|
Enable FIFOs |
BCM2835_PL011_LCRH_STP2 = (1 shl 3);
|
Two stop bits select |
BCM2835_PL011_LCRH_EPS = (1 shl 2);
|
Even parity select (0 = odd parity / 1 = even parity) |
BCM2835_PL011_LCRH_PEN = (1 shl 1);
|
Parity enable |
BCM2835_PL011_LCRH_BRK = (1 shl 0);
|
Send break |
BCM2835 PL011 UART control constants
BCM2835_PL011_CR_* | See Section 13.4 | |
BCM2835_PL011_CR_CTSEN = (1 shl 15);
|
CTS hardware flow control enable (If this bit is set to 1 data is only transmitted when the nUARTCTS signal is asserted) |
BCM2835_PL011_CR_RTSEN = (1 shl 14);
|
RTS hardware flow control enable (If this bit is set to 1 data is only requested when there is space in the receive FIFO for it to be received) |
BCM2835_PL011_CR_OUT2 = (1 shl 13);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_CR_OUT1 = (1 shl 12);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_CR_RTS = (1 shl 11);
|
Request to send (This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW) |
BCM2835_PL011_CR_DTR = (1 shl 10);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_CR_RXE = (1 shl 9);
|
Receive enable |
BCM2835_PL011_CR_TXE = (1 shl 8);
|
Transmit enable |
BCM2835_PL011_CR_LBE = (1 shl 7);
|
Loopback enable |
| Bits 6:3 Reserved - Write as 0, read as don't care | |
BCM2835_PL011_CR_SIRLP = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_CR_SIREN = (1 shl 1);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_CR_UARTEN = (1 shl 0);
|
UART enable |
BCM2835 PL011 UART interrupt FIFO level select constants
BCM2835_PL011_IFLS_* | See Section 13.4 | |
BCM2835_PL011_IFLS_RXIFPSEL = (7 shl 9);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_IFLS_TXIFPSEL = (7 shl 6);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_IFLS_RXIFLSEL = (7 shl 3);
|
Receive interrupt FIFO level select |
BCM2835_PL011_IFLS_RXIFLSEL1_8 = (0 shl 3);
|
b000 = Receive FIFO becomes 1/8 full |
BCM2835_PL011_IFLS_RXIFLSEL1_4 = (1 shl 3);
|
b001 = Receive FIFO becomes 1/4 full |
BCM2835_PL011_IFLS_RXIFLSEL1_2 = (2 shl 3);
|
b010 = Receive FIFO becomes 1/2 full |
BCM2835_PL011_IFLS_RXIFLSEL3_4 = (3 shl 3);
|
b011 = Receive FIFO becomes 3/4 full |
BCM2835_PL011_IFLS_RXIFLSEL7_8 = (4 shl 3);
|
b100 = Receive FIFO becomes 7/8 full |
BCM2835_PL011_IFLS_TXIFLSEL = (7 shl 0);
|
Transmit interrupt FIFO level select |
BCM2835_PL011_IFLS_TXIFLSEL1_8 = (0 shl 0);
|
b000 = Transmit FIFO becomes 1/8 full |
BCM2835_PL011_IFLS_TXIFLSEL1_4 = (1 shl 0);
|
b001 = Transmit FIFO becomes 1/4 full |
BCM2835_PL011_IFLS_TXIFLSEL1_2 = (2 shl 0);
|
b010 = Transmit FIFO becomes 1/2 full |
BCM2835_PL011_IFLS_TXIFLSEL3_4 = (3 shl 0);
|
b011 = Transmit FIFO becomes 3/4 full |
BCM2835_PL011_IFLS_TXIFLSEL7_8 = (4 shl 0);
|
b100 = Transmit FIFO becomes 7/8 full |
BCM2835 PL011 UART interrupt mask set/clear constants
BCM2835_PL011_IMSC_* | See Section 13.4 | |
BCM2835_PL011_IMSC_OEIM = (1 shl 10);
|
Overrun error interrupt mask |
BCM2835_PL011_IMSC_BEIM = (1 shl 9);
|
Break error interrupt mask |
BCM2835_PL011_IMSC_PEIM = (1 shl 8);
|
Parity error interrupt mask |
BCM2835_PL011_IMSC_FEIM = (1 shl 7);
|
Framing error interrupt mask |
BCM2835_PL011_IMSC_RTIM = (1 shl 6);
|
Receive timeout interrupt mask |
BCM2835_PL011_IMSC_TXIM = (1 shl 5);
|
Transmit interrupt mask |
BCM2835_PL011_IMSC_RXIM = (1 shl 4);
|
Receive interrupt mask |
BCM2835_PL011_IMSC_DSRMIM = (1 shl 3);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_IMSC_DCDMIM = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_IMSC_CTSMIM = (1 shl 1);
|
nUARTCTS modem interrupt mask |
BCM2835_PL011_IMSC_RIMIM = (1 shl 0);
|
Unsupported, write zero, read as don't care |
BCM2835 PL011 UART raw interrupt status constants
BCM2835_PL011_RIS_* | See Section 13.4 | |
BCM2835_PL011_RIS_OERIS = (1 shl 10);
|
Overrun error interrupt status |
BCM2835_PL011_RIS_BERIS = (1 shl 9);
|
Break error interrupt status |
BCM2835_PL011_RIS_PERIS = (1 shl 8);
|
Parity error interrupt status |
BCM2835_PL011_RIS_FERIS = (1 shl 7);
|
Framing error interrupt status |
BCM2835_PL011_RIS_RTRIS = (1 shl 6);
|
Receive timeout interrupt status |
BCM2835_PL011_RIS_TXRIS = (1 shl 5);
|
Transmit interrupt status |
BCM2835_PL011_RIS_RXRIS = (1 shl 4);
|
Receive interrupt status |
BCM2835_PL011_RIS_DSRMRIS = (1 shl 3);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_RIS_DCDMRIS = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_RIS_CTSMRIS = (1 shl 1);
|
nUARTCTS modem interrupt status |
BCM2835_PL011_RIS_RIMRIS = (1 shl 0);
|
Unsupported, write zero, read as don't care |
BCM2835 PL011 UART masked interrupt status constants
BCM2835_PL011_MIS_* | See Section 13.4 | |
BCM2835_PL011_MIS_OEMIS = (1 shl 10);
|
Overrun error masked interrupt status |
BCM2835_PL011_MIS_BEMIS = (1 shl 9);
|
Break error masked interrupt status |
BCM2835_PL011_MIS_PEMIS = (1 shl 8);
|
Parity error masked interrupt status |
BCM2835_PL011_MIS_FEMIS = (1 shl 7);
|
Framing error masked interrupt status |
BCM2835_PL011_MIS_RTMIS = (1 shl 6);
|
Receive timeout masked interrupt status |
BCM2835_PL011_MIS_TXMIS = (1 shl 5);
|
Transmit masked interrupt status |
BCM2835_PL011_MIS_RXMIS = (1 shl 4);
|
Receive masked interrupt status |
BCM2835_PL011_MIS_DSRMMIS = (1 shl 3);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_MIS_DCDMMIS = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_MIS_CTSMMIS = (1 shl 1);
|
nUARTCTS modem masked interrupt status |
BCM2835_PL011_MIS_RIMMIS = (1 shl 0);
|
Unsupported, write zero, read as don't care |
BCM2835 PL011 UART interrupt clear constants
BCM2835_PL011_ICR_* | See Section 13.4 | |
BCM2835_PL011_ICR_OEIC = (1 shl 10);
|
Overrun error interrupt clear |
BCM2835_PL011_ICR_BEIC = (1 shl 9);
|
Break error interrupt clear |
BCM2835_PL011_ICR_PEIC = (1 shl 8);
|
Parity error interrupt clear |
BCM2835_PL011_ICR_FEIC = (1 shl 7);
|
Framing error interrupt clear |
BCM2835_PL011_ICR_RTIC = (1 shl 6);
|
Receive timeout interrupt clear |
BCM2835_PL011_ICR_TXIC = (1 shl 5);
|
Transmit interrupt clear |
BCM2835_PL011_ICR_RXIC = (1 shl 4);
|
Receive interrupt clear |
BCM2835_PL011_ICR_DSRMIC = (1 shl 3);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_ICR_DCDMIC = (1 shl 2);
|
Unsupported, write zero, read as don't care |
BCM2835_PL011_ICR_CTSMIC = (1 shl 1);
|
nUARTCTS modem interrupt clear |
BCM2835_PL011_ICR_RIMIC = (1 shl 0);
|
Unsupported, write zero, read as don't care |
BCM2835 PL011 UART DMA control constants
| See Section 13.4 | |
| This register is disabled, writing to it has no effect and reading returns 0 |
BCM2835 ARM interrupt controller constants
BCM2835_ARM_INTERRUPT_* | See Section 7.5 | |
BCM2835_ARM_INTERRUPT_FIQ_ENABLE = (1 shl 7);
|
FIQ enable (Set this bit to 1 to enable FIQ generation. If set to 0 bits 6:0 are don't care) |
BCM2835_ARM_INTERRUPT_FIQ_SOURCE = ($7F shl 0);
|
Select FIQ Source (0..127) |
BCM2835 ARM timer constants
BCM2835_ARM_TIMER_* | See Section 14.2 | |
BCM2835_ARM_TIMER_CONTROL_COUNTER_PRESCALE = ($FF shl 16);
|
Free running counter pre-scaler (Freq is sys_clk/(prescale+1)) |
BCM2835_ARM_TIMER_CONTROL_COUNTER_ENABLED = (1 shl 9);
|
0 : Free running counter Disabled / 1 : Free running counter Enabled |
BCM2835_ARM_TIMER_CONTROL_DEBUG_HALT = (1 shl 8);
|
0 : Timers keeps running if ARM is in debug halted mode / 1 : Timers halted if ARM is in debug halted mode |
BCM2835_ARM_TIMER_CONTROL_TIMER_ENABLED = (1 shl 7);
|
0 : Timer disabled / 1 : Timer enabled |
BCM2835_ARM_TIMER_CONTROL_INT_ENABLED = (1 shl 5);
|
0 : Timer interrupt disabled / 1 : Timer interrupt enabled |
BCM2835_ARM_TIMER_CONTROL_PRESCALE = (3 shl 2);
|
Pre-scale bits: 00 : pre-scale is clock / 1 (No pre-scale) / 01 : pre-scale is clock / 16 / 10 : pre-scale is clock / 256 / 11 : pre-scale is clock / 1 |
BCM2835_ARM_TIMER_CONTROL_32BIT = (1 shl 1);
|
0 : 16-bit counters / 1 : 32-bit counter |
BCM2835_ARM_TIMER_CONTROL_ONESHOT = (1 shl 0);
|
0 = wrapping mode (default) / 1 = one-shot mode (Not supported by BCM2835) |
BCM2835_ARM_TIMER_RAW_IRQ_PENDING = (1 shl 0);
|
0 : The interrupt pending bits is clear / 1 : The interrupt pending bit is set |
BCM2835_ARM_TIMER_MASKED_IRQ_PENDING = (1 shl 0);
|
0 : Interrupt line not asserted / 1 :Interrupt line is asserted, (the interrupt pending and the interrupt enable bit are set) |
BCM2835_ARM_TIMER_PREDIVIDER_MASK = ($3FF shl 0);
|
Pre-divider value (timer_clock = apb_clock/(pre_divider+1)) |
BCM2835 power management, reset controller and watchdog constants
BCM2835_PM_* BCM2835_PM_PASSWORD = $5A000000;
|
|
BCM2835_PM_RSTC_WRCFG_CLR = $FFFFFFCF;
|
|
BCM2835_PM_RSTC_WRCFG_SET = $00000030;
|
|
BCM2835_PM_RSTC_WRCFG_FULL_RESET = $00000020;
|
|
BCM2835_PM_RSTC_RESET = $00000102;
|
|
BCM2835_PM_RSTS_HADPOR_SET = $00001000;
|
|
BCM2835_PM_RSTS_HADSRH_SET = $00000400;
|
|
BCM2835_PM_RSTS_HADSRF_SET = $00000200;
|
|
BCM2835_PM_RSTS_HADSRQ_SET = $00000100;
|
|
BCM2835_PM_RSTS_HADWRH_SET = $00000040;
|
|
BCM2835_PM_RSTS_HADWRF_SET = $00000020;
|
|
BCM2835_PM_RSTS_HADWRQ_SET = $00000010;
|
|
BCM2835_PM_RSTS_HADDRH_SET = $00000004;
|
|
BCM2835_PM_RSTS_HADDRF_SET = $00000002;
|
|
BCM2835_PM_RSTS_HADDRQ_SET = $00000001;
|
|
BCM2835_PM_RSTS_RASPBERRYPI_HALT = $00000555;
|
Special value to tell the Raspberry Pi firmware not to reboot |
BCM2835_PM_WDOG_RESET = $00000000;
|
|
BCM2835_PM_WDOG_TIME_MASK = $000FFFFF;
|
|
BCM2835_PM_WDOG_TICKS_PER_SECOND = (1 shl 16);
|
|
BCM2835_PM_WDOG_TICKS_PER_MILLISECOND = (BCM2835_PM_WDOG_TICKS_PER_SECOND div 1000);
|
|
BCM2835 random number generator constants
BCM2835_RANDOM_* BCM2835_RANDOM_DISABLE = $00000000;
|
Disable Random Number Generator |
BCM2835_RANDOM_ENABLE = $00000001;
|
Enable Random Number Generator |
BCM2835_RANDOM_DOUBLE_SPEED = $00000002;
|
Double Speed Mode (Less Random) |
BCM2835 clock management constants
BCM2835_CM_* | See Section 6 | |
BCM2835_CM_PASSWORD = $5A000000;
|
|
BCM2835 clock manager control constants
BCM2835_CM_CTL_* | See Section 6.3 | |
BCM2835_CM_CTL_MASH_0 = (0 shl 9);
|
MASH control - 0 = integer division |
BCM2835_CM_CTL_MASH_1 = (1 shl 9);
|
MASH control - 1 = 1-stage MASH (equivalent to non-MASH dividers) |
BCM2835_CM_CTL_MASH_2 = (2 shl 9);
|
MASH control - 2 = 2-stage MASH |
BCM2835_CM_CTL_MASH_3 = (3 shl 9);
|
MASH control - 3 = 3-stage MASH (To avoid lock-ups and glitches do not change this control while BUSY=1 and do not change this control at the same time as asserting ENAB) |
BCM2835_CM_CTL_FLIP = (1 shl 8);
|
MASH control - Invert the clock generator output (To avoid output glitches do not switch this control while BUSY=1) |
BCM2835_CM_CTL_BUSY = (1 shl 7);
|
Clock generator is running (To avoid glitches and lock-ups, clock sources and setups must not be changed while this flag is set) |
BCM2835_CM_CTL_GATE = (1 shl 6);
|
Unused |
BCM2835_CM_CTL_KILL = (1 shl 5);
|
Kill the clock generator (0 = no action / 1 = stop and reset the clock generator) (This is intended for test/debug only) |
BCM2835_CM_CTL_ENAB = (1 shl 4);
|
Enable the clock generator |
BCM2835_CM_CTL_SRC_GND = (0 shl 0);
|
Clock source - 0 Hz GND |
BCM2835_CM_CTL_SRC_OSC = (1 shl 0);
|
Clock source - 19.2 MHz Oscillator |
BCM2835_CM_CTL_SRC_TESTDEBUG0 = (2 shl 0);
|
Clock source - 0 Hz Testdebug0 |
BCM2835_CM_CTL_SRC_TESTDEBUG1 = (3 shl 0);
|
Clock source - 0 Hz Testdebug1 |
BCM2835_CM_CTL_SRC_PLLA = (4 shl 0);
|
Clock source - 0 Hz PLLA per |
BCM2835_CM_CTL_SRC_PLLC = (5 shl 0);
|
Clock source - 1000 MHz PLLC per (changes with overclock settings) |
BCM2835_CM_CTL_SRC_PLLD = (6 shl 0);
|
Clock source - 500 MHz PLLD per |
BCM2835_CM_CTL_SRC_HDMI = (7 shl 0);
|
Clock source - 216 MHz HDMI auxiliary |
BCM2835 clock manager divisor constants
BCM2835_CM_DIV_* | See Section 6.3 | |
BCM2835_CM_DIV_INT_MASK = $00FFF000;
|
Integer part of divisor (This value has a minimum limit determined by the MASH setting) (To avoid lock-ups and glitches do not change this control while BUSY=1) |
BCM2835_CM_DIV_FRAC_MASK = $00000FFF;
|
Fractional part of divisor (To avoid lock-ups and glitches do not change this control while BUSY=1) |
BCM2835 clock manager constants
BCM2835_CM_* BCM2835_CM_GNRICCTL = $00000000;
|
Generic Clock Control} |
BCM2835_CM_GNRICDIV = $00000004;
|
Generic Clock Divisor |
BCM2835_CM_VPUCTL = $00000008;
|
VPU Clock Control |
BCM2835_CM_VPUDIV = $0000000C;
|
VPU Clock Divisor |
BCM2835_CM_SYSCTL = $00000010;
|
System Clock Control |
BCM2835_CM_SYSDIV = $00000014;
|
System Clock Divisor |
BCM2835_CM_PERIACTL = $00000018;
|
PERIA Clock Control |
BCM2835_CM_PERIADIV = $0000001C;
|
PERIA Clock Divisor |
BCM2835_CM_PERIICTL = $00000020;
|
PERII Clock Control |
BCM2835_CM_PERIIDIV = $00000024;
|
PERII Clock Divisor |
BCM2835_CM_H264CTL = $00000028;
|
H264 Clock Control |
BCM2835_CM_H264DIV = $0000002C;
|
H264 Clock Divisor |
BCM2835_CM_ISPCTL = $00000030;
|
ISP Clock Control |
BCM2835_CM_ISPDIV = $00000034;
|
ISP Clock Divisor |
BCM2835_CM_V3DCTL = $00000038;
|
V3D Clock Control |
BCM2835_CM_V3DDIV = $0000003C;
|
V3D Clock Divisor |
BCM2835_CM_CAM0CTL = $00000040;
|
Camera 0 Clock Control |
BCM2835_CM_CAM0DIV = $00000044;
|
Camera 0 Clock Divisor |
BCM2835_CM_CAM1CTL = $00000048;
|
Camera 1 Clock Control |
BCM2835_CM_CAM1DIV = $0000004C;
|
Camera 1 Clock Divisor |
BCM2835_CM_CCP2CTL = $00000050;
|
CCP2 Clock Control |
BCM2835_CM_CCP2DIV = $00000054;
|
CCP2 Clock Divisor |
BCM2835_CM_DSI0ECTL = $00000058;
|
DSI0E Clock Control |
BCM2835_CM_DSI0EDIV = $0000005C;
|
DSI0E Clock Divisor |
BCM2835_CM_DSI0PCTL = $00000060;
|
DSI0P Clock Control |
BCM2835_CM_DSI0PDIV = $00000064;
|
DSI0P Clock Divisor |
BCM2835_CM_DPICTL = $00000068;
|
DPI Clock Control |
BCM2835_CM_DPIDIV = $0000006C;
|
DPI Clock Control |
BCM2835_CM_GP0CTL = $00000070;
|
General Purpose 0 Clock Control |
BCM2835_CM_GP0DIV = $00000074;
|
General Purpose 0 Clock Divisor |
BCM2835_CM_GP1CTL = $00000078;
|
General Purpose 1 Clock Control |
BCM2835_CM_GP1DIV = $0000007C;
|
General Purpose 1 Clock Divisor |
BCM2835_CM_GP2CTL = $00000080;
|
General Purpose 2 Clock Control |
BCM2835_CM_GP2DIV = $00000084;
|
General Purpose 2 Clock Divisor |
BCM2835_CM_HSMCTL = $00000088;
|
HSM Clock Control |
BCM2835_CM_HSMDIV = $0000008C;
|
HSM Clock Divisor |
BCM2835_CM_OTPCTL = $00000090;
|
OTP Clock Control |
BCM2835_CM_OTPDIV = $00000094;
|
OTP Clock Divisor |
BCM2835_CM_PCMCTL = $00000098;
|
PCM / I2S Clock Control |
BCM2835_CM_PCMDIV = $0000009C;
|
PCM / I2S Clock Divisor |
BCM2835_CM_PWMCTL = $000000A0;
|
PWM Clock Control |
BCM2835_CM_PWMDIV = $000000A4;
|
PWM Clock Divisor |
BCM2835_CM_SLIMCTL = $000000A8;
|
SLIM Clock Control |
BCM2835_CM_SLIMDIV = $000000AC;
|
SLIM Clock Divisor |
BCM2835_CM_SMICTL = $000000B0;
|
SMI Clock Control |
BCM2835_CM_SMIDIV = $000000B4;
|
SMI Clock Divisor |
BCM2835_CM_TCNTCTL = $000000C0;
|
TCNT Clock Control |
BCM2835_CM_TCNTDIV = $000000C4;
|
TCNT Clock Divisor |
BCM2835_CM_TECCTL = $000000C8;
|
TEC Clock Control |
BCM2835_CM_TECDIV = $000000CC;
|
TEC Clock Divisor |
BCM2835_CM_TD0CTL = $000000D0;
|
TD0 Clock Control |
BCM2835_CM_TD0DIV = $000000D4;
|
TD0 Clock Divisor |
BCM2835_CM_TD1CTL = $000000D8;
|
TD1 Clock Control |
BCM2835_CM_TD1DIV = $000000DC;
|
TD1 Clock Divisor |
BCM2835_CM_TSENSCTL = $000000E0;
|
TSENS Clock Control |
BCM2835_CM_TSENSDIV = $000000E4;
|
TSENS Clock Divisor |
BCM2835_CM_TIMERCTL = $000000E8;
|
Timer Clock Control |
BCM2835_CM_TIMERDIV = $000000EC;
|
Timer Clock Divisor |
BCM2835_CM_UARTCTL = $000000F0;
|
UART Clock Control |
BCM2835_CM_UARTDIV = $000000F4;
|
UART Clock Divisor |
BCM2835_CM_VECCTL = $000000F8;
|
VEC Clock Control |
BCM2835_CM_VECDIV = $000000FC;
|
VEC Clock Divisor |
BCM2835_CM_OSCCOUNT = $00000100;
|
Oscillator Count |
BCM2835_CM_PLLA = $00000104;
|
PLLA |
BCM2835_CM_PLLC = $00000108;
|
PLLC |
BCM2835_CM_PLLD = $0000010C;
|
PLLD |
BCM2835_CM_PLLH = $00000110;
|
PLLH |
BCM2835_CM_LOCK = $00000114;
|
Lock |
BCM2835_CM_EVENT = $00000118;
|
Event |
BCM2835_CM_INTEN = $00000118;
|
INTEN |
BCM2835_CM_DSI0HSCK = $00000120;
|
DSI0HSCK |
BCM2835_CM_CKSM = $00000124;
|
CKSM |
BCM2835_CM_OSCFREQI = $00000128;
|
Oscillator Frequency Integer |
BCM2835_CM_OSCFREQF = $0000012C;
|
Oscillator Frequency Fraction |
BCM2835_CM_PLLTCTL = $00000130;
|
PLLT Control |
BCM2835_CM_PLLTCNT0 = $00000134;
|
PLLT0 Count |
BCM2835_CM_PLLTCNT1 = $00000138;
|
PLLT1 Count |
BCM2835_CM_PLLTCNT2 = $0000013C;
|
PLLT2 Count |
BCM2835_CM_PLLTCNT3 = $00000140;
|
PLLT3 Count |
BCM2835_CM_TDCLKEN = $00000144;
|
TD Clock Enable |
BCM2835_CM_BURSTCTL = $00000148;
|
Burst Control |
BCM2835_CM_BURSTCNT = $0000014C;
|
Burst Count |
BCM2835_CM_DSI1ECTL = $00000158;
|
DSI1E Clock Control |
BCM2835_CM_DSI1EDIV = $0000015C;
|
DSI1E Clock Divisor |
BCM2835_CM_DSI1PCTL = $00000160;
|
DSI1P Clock Control |
BCM2835_CM_DSI1PDIV = $00000164;
|
DSI1P Clock Divisor |
BCM2835_CM_DFTCTL = $00000168;
|
DFT Clock Control |
BCM2835_CM_DFTDIV = $0000016C;
|
DFT Clock Divisor |
BCM2835_CM_PLLB = $00000170;
|
PLLB |
BCM2835_CM_PULSECTL = $00000190;
|
Pulse Clock Control |
BCM2835_CM_PULSEDIV = $00000194;
|
Pulse Clock Divisor |
BCM2835_CM_SDCCTL = $000001A8;
|
SDC Clock Control |
BCM2835_CM_SDCDIV = $000001AC;
|
SDC Clock Divisor |
BCM2835_CM_ARMCTL = $000001B0;
|
ARM Clock Control |
BCM2835_CM_ARMDIV = $000001B4;
|
ARM Clock Divisor |
BCM2835_CM_AVEOCTL = $000001B8;
|
AVEO Clock Control |
BCM2835_CM_AVEODIV = $000001BC;
|
AVEO Clock Divisor |
BCM2835_CM_EMMCCTL = $000001C0;
|
EMMC Clock Control |
BCM2835_CM_EMMCDIV = $000001C4;
|
EMMC Clock Divisor |
BCM2835 mailbox constants
BCM2835_MAILBOX_* BCM2835_MAILBOX_0 = 0;
|
|
BCM2835_MAILBOX_1 = 1;
|
BCM2835 mailbox 0 channel constants
BCM2835_MAILBOX0_CHANNEL_* | See https://github.com/raspberrypi/firmware/wiki/Mailboxes | |
BCM2835_MAILBOX0_CHANNEL_POWER_MGMT = 0;
|
|
BCM2835_MAILBOX0_CHANNEL_FRAMEBUFFER = 1;
|
|
BCM2835_MAILBOX0_CHANNEL_UART = 2;
|
|
BCM2835_MAILBOX0_CHANNEL_VCHIQ = 3;
|
|
BCM2835_MAILBOX0_CHANNEL_LEDS = 4;
|
|
BCM2835_MAILBOX0_CHANNEL_BUTTONS = 5;
|
|
BCM2835_MAILBOX0_CHANNEL_TOUCHSCREEN = 6;
|
|
BCM2835_MAILBOX0_CHANNEL_UNKNOWN = 7;
|
|
BCM2835_MAILBOX0_CHANNEL_PROPERTYTAGS_ARMVC = 8;
|
|
BCM2835_MAILBOX0_CHANNEL_PROPERTYTAGS_VCARM = 9;
|
|
BCM2835 mailbox 1 channel constants
BCM2835_MAILBOX_* | See https://github.com/raspberrypi/firmware/wiki/Mailboxes | |
| Currently unknown | |
| The BCM2835 mailboxes pass 28-bit messages (The low 4 bits of the 32-bit value are used to specify the channel) | |
BCM2835_MAILBOX_CHANNEL_MASK = $0000000F;
|
|
BCM2835_MAILBOX_DATA_MASK = $FFFFFFF0;
|
|
BCM2835 mailbox status flag constants
BCM2835_MAILBOX_STATUS_* BCM2835_MAILBOX_STATUS_FULL = $80000000;
|
|
BCM2835_MAILBOX_STATUS_EMPTY = $40000000;
|
BCM2835 mailbox property tag constants
BCM2835_MBOX_TAG_GET_* | See https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface or \include\soc\bcm2835\raspberrypi-firmware.h | |
| VideoCore | |
BCM2835_MBOX_TAG_GET_FIRMWARE_REV = $00000001;
|
|
| Hardware | |
BCM2835_MBOX_TAG_GET_BOARD_MODEL = $00010001;
|
|
BCM2835_MBOX_TAG_GET_BOARD_REV = $00010002;
|
|
BCM2835_MBOX_TAG_GET_MAC_ADDRESS = $00010003;
|
|
BCM2835_MBOX_TAG_GET_BOARD_SERIAL = $00010004;
|
|
BCM2835_MBOX_TAG_GET_ARM_MEMORY = $00010005;
|
|
BCM2835_MBOX_TAG_GET_VC_MEMORY = $00010006;
|
|
BCM2835_MBOX_TAG_GET_CLOCKS = $00010007;
|
|
| Shared Resource Management | |
BCM2835_MBOX_TAG_GET_POWER_STATE = $00020001;
|
Response indicates current state |
BCM2835_MBOX_TAG_GET_TIMING = $00020002;
|
Response indicates wait time required after turning a device on before power is stable |
BCM2835_MBOX_TAG_SET_POWER_STATE = $00028001;
|
Response indicates new state, with/without waiting for the power to become stable |
BCM2835_MBOX_TAG_GET_CLOCK_STATE = $00030001;
|
|
BCM2835_MBOX_TAG_SET_CLOCK_STATE = $00038001;
|
|
BCM2835_MBOX_TAG_GET_CLOCK_RATE = $00030002;
|
|
BCM2835_MBOX_TAG_SET_CLOCK_RATE = $00038002;
|
|
BCM2835_MBOX_TAG_GET_CLOCK_MAX_RATE = $00030004;
|
Return the maximum supported clock rate for the given clock. Clocks should not be set higher than this. |
BCM2835_MBOX_TAG_GET_CLOCK_MIN_RATE = $00030007;
|
Return the minimum supported clock rate for the given clock. This may be used when idle. |
BCM2835_MBOX_TAG_GET_TURBO = $00030009;
|
Get the turbo state for index id. Id should be 0. Level will be zero for non-turbo and one for turbo. |
BCM2835_MBOX_TAG_SET_TURBO = $00038009;
|
Set the turbo state for index id. Id should be zero. Level will be zero for non-turbo and one for turbo. This will cause GPU clocks to be set to maximum when enabled and minimum when disabled. |
BCM2835_MBOX_TAG_GET_STC = $0003000b;
|
|
| Voltage | |
BCM2835_MBOX_TAG_GET_VOLTAGE = $00030003;
|
The voltage value may be clamped to the supported range. A value of 0x80000000 means the id was not valid. |
BCM2835_MBOX_TAG_SET_VOLTAGE = $00038003;
|
The voltage value may be clamped to the supported range. A value of 0x80000000 means the id was not valid. |
BCM2835_MBOX_TAG_GET_MAX_VOLTAGE = $00030005;
|
Return the maximum supported voltage rate for the given id. Voltages should not be set higher than this. |
BCM2835_MBOX_TAG_GET_MIN_VOLTAGE = $00030008;
|
Return the minimum supported voltage rate for the given id. This may be used when idle. |
BCM2835_MBOX_TAG_GET_TEMP = $00030006;
|
Return the temperature of the SoC in thousandths of a degree C. Id should be zero. |
BCM2835_MBOX_TAG_GET_MAX_TEMP = $0003000a;
|
Return the maximum safe temperature of the SoC in thousandths of a degree C. Id should be zero. Overclock may be disabled above this temperature. |
BCM2835_MBOX_TAG_ALLOCATE_MEMORY = $0003000c;
|
Allocates contiguous memory on the GPU. Size and alignment are in bytes. |
BCM2835_MBOX_TAG_LOCK_MEMORY = $0003000d;
|
Lock buffer in place, and return a bus address. Must be done before memory can be accessed. |
BCM2835_MBOX_TAG_UNLOCK_MEMORY = $0003000e;
|
Unlock buffer. It retains contents, but may move. Needs to be locked before next use. status=0 is success. |
BCM2835_MBOX_TAG_RELEASE_MEMORY = $0003000f;
|
Free the memory buffer. status=0 is success |
BCM2835_MBOX_TAG_EXECUTE_CODE = $00030010;
|
Calls the function at given (bus) address and with arguments given. E.g. r0 = fn(r0, r1, r2, r3, r4, r5); It blocks until call completes |
BCM2835_MBOX_TAG_EXECUTE_QPU = $00030011; {}
|
|
BCM2835_MBOX_TAG_ENABLE_QPU = $00030012; {}
|
|
BCM2835_MBOX_TAG_GET_DISPMANX_HANDLE = $00030014;
|
Gets the mem_handle associated with a created dispmanx resource. This can be locked and the memory directly written from the arm to avoid having to copy the image data to GPU. |
BCM2835_MBOX_TAG_GET_EDID_BLOCK = $00030020;
|
This reads the specified EDID block from attached HDMI/DVI device. There will always be at least one block of 128 bytes, but there may be additional blocks. You should keep requesting blocks (starting from 0) until the status returned is non-zero. |
BCM2835_MBOX_TAG_GET_CUSTOMER_OTP = $00030021;
|
|
BCM2835_MBOX_TAG_SET_CUSTOMER_OTP = $00038021;
|
|
BCM2835_MBOX_TAG_GET_DOMAIN_STATE = $00030030;
|
|
BCM2835_MBOX_TAG_SET_DOMAIN_STATE = $00038030;
|
|
| Frame Buffer | |
BCM2835_MBOX_TAG_ALLOCATE_BUFFER = $00040001;
|
If the requested alignment is unsupported then the current base and size (which may be 0 if not allocated) is returned and no change occurs |
BCM2835_MBOX_TAG_RELEASE_BUFFER = $00048001;
|
Releases and disables the frame buffer |
BCM2835_MBOX_TAG_SET_BLANK_SCREEN = $00040002;
|
|
BCM2835_MBOX_TAG_TST_BLANK_SCREEN = $00044002;
|
|
BCM2835_MBOX_TAG_GET_PHYSICAL_W_H = $00040003;
|
Note that the "physical (display)" size is the size of the allocated buffer in memory, not the resolution of the video signal sent to the display device. |
BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H = $00044003;
|
|
BCM2835_MBOX_TAG_SET_PHYSICAL_W_H = $00048003;
|
|
BCM2835_MBOX_TAG_GET_VIRTUAL_W_H = $00040004;
|
Note that the "virtual (buffer)" size is the portion of buffer that is sent to the display device, not the resolution the buffer itself. This may be smaller than the allocated buffer size in order to implement panning. |
BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H = $00044004;
|
|
BCM2835_MBOX_TAG_SET_VIRTUAL_W_H = $00048004;
|
|
BCM2835_MBOX_TAG_GET_DEPTH = $00040005;
|
|
BCM2835_MBOX_TAG_TEST_DEPTH = $00044005;
|
|
BCM2835_MBOX_TAG_SET_DEPTH = $00048005;
|
|
BCM2835_MBOX_TAG_GET_PIXEL_ORDER = $00040006;
|
|
BCM2835_MBOX_TAG_TEST_PIXEL_ORDER = $00044006;
|
|
BCM2835_MBOX_TAG_SET_PIXEL_ORDER = $00048006;
|
|
BCM2835_MBOX_TAG_GET_ALPHA_MODE = $00040007;
|
|
BCM2835_MBOX_TAG_TEST_ALPHA_MODE = $00044007;
|
|
BCM2835_MBOX_TAG_SET_ALPHA_MODE = $00048007;
|
|
BCM2835_MBOX_TAG_GET_PITCH = $00040008;
|
|
BCM2835_MBOX_TAG_TST_PITCH = $00044008;
|
|
BCM2835_MBOX_TAG_SET_PITCH = $00048008;
|
|
BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET = $00040009;
|
Offset of physical display window within virtual buffer |
BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET = $00044009;
|
|
BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET = $00048009;
|
|
BCM2835_MBOX_TAG_GET_OVERSCAN = $0004000a;
|
|
BCM2835_MBOX_TAG_TEST_OVERSCAN = $0004400a;
|
|
BCM2835_MBOX_TAG_SET_OVERSCAN = $0004800a;
|
|
BCM2835_MBOX_TAG_GET_PALETTE = $0004000b;
|
|
BCM2835_MBOX_TAG_TEST_PALETTE = $0004400b;
|
|
BCM2835_MBOX_TAG_SET_PALETTE = $0004800b;
|
|
BCM2835_MBOX_TAG_GET_TOUCHBUF = $0004000f;
|
|
BCM2835_MBOX_TAG_GET_GPIOVIRTBUF = $00040010;
|
|
BCM2835_MBOX_TAG_GET_LAYER = $0004000c;
|
|
BCM2835_MBOX_TAG_TST_LAYER = $0004400c;
|
|
BCM2835_MBOX_TAG_SET_LAYER = $0004800c;
|
|
BCM2835_MBOX_TAG_GET_TRANSFORM = $0004000d;
|
|
BCM2835_MBOX_TAG_TST_TRANSFORM = $0004400d;
|
|
BCM2835_MBOX_TAG_SET_TRANSFORM = $0004800d;
|
|
BCM2835_MBOX_TAG_TST_VSYNC = $0004400e;
|
|
BCM2835_MBOX_TAG_SET_VSYNC = $0004800e;
|
|
BCM2835_MBOX_TAG_SET_BACKLIGHT = $0004800f;
|
|
BCM2835_MBOX_TAG_SET_CURSOR_INFO = $00008010;
|
00008011 These were reversed in the documentation, see Linux \include\soc\bcm2835\raspberrypi-firmware.h |
BCM2835_MBOX_TAG_SET_CURSOR_STATE = $00008011;
|
00008010 |
| VCHIQ | |
BCM2835_MBOX_TAG_VCHIQ_INIT = $00048010;
|
|
| Config | |
BCM2835_MBOX_TAG_GET_COMMAND_LINE = $00050001;
|
|
| Shared Resource Management | |
BCM2835_MBOX_TAG_GET_DMA_CHANNELS = $00060001;
|
Caller assumes that the VC has enabled all the usable DMA channels |
| End | |
BCM2835_MBOX_TAG_END = $00000000;
|
|
BCM2835 mailbox board revision value constants
BCM2835_BOARD_REV_* | See: http://elinux.org/RPi_HardwareHistory | |
BCM2835_BOARD_REV_B_I2C0_2 = $00000002;
|
|
BCM2835_BOARD_REV_B_I2C0_3 = $00000003;
|
|
BCM2835_BOARD_REV_B_I2C1_4 = $00000004;
|
|
BCM2835_BOARD_REV_B_I2C1_5 = $00000005;
|
|
BCM2835_BOARD_REV_B_I2C1_6 = $00000006;
|
|
BCM2835_BOARD_REV_A_7 = $00000007;
|
|
BCM2835_BOARD_REV_A_8 = $00000008;
|
|
BCM2835_BOARD_REV_A_9 = $00000009;
|
|
BCM2835_BOARD_REV_B_REV2_d = $0000000D;
|
|
BCM2835_BOARD_REV_B_REV2_e = $0000000E;
|
|
BCM2835_BOARD_REV_B_REV2_f = $0000000F;
|
|
BCM2835_BOARD_REV_B_PLUS = $00000010;
|
|
BCM2835_BOARD_REV_CM = $00000011;
|
|
BCM2835_BOARD_REV_A_PLUS = $00000012;
|
|
BCM2835_BOARD_REV_B_PLUS_2 = $00000013;
|
|
BCM2835_BOARD_REV_CM_2 = $00000014;
|
|
BCM2835_BOARD_REV_A_PLUS_2 = $00000015;
|
|
BCM2835_BOARD_REV_ZERO = $00900092;
|
|
BCM2835_BOARD_REV_MASK = $00FFFFFF;
|
Mask off the warranty bit |
BCM2835 mailbox board revision constants
BCM2835_BOARD_REVISION_* | See: https://github.com/AndrewFromMelbourne/raspberry_pi_revision | |
BCM2835_BOARD_REVISION_PCB_MASK = ($F shl 0);
|
PCB Revision Number |
BCM2835_BOARD_REVISION_MODEL_MASK = ($FF shl 4);
|
Model Number |
BCM2835_BOARD_REVISION_MODEL_A = (0 shl 4);
|
Model A |
BCM2835_BOARD_REVISION_MODEL_B = (1 shl 4);
|
Model B |
BCM2835_BOARD_REVISION_MODEL_APLUS = (2 shl 4);
|
Model A+ |
BCM2835_BOARD_REVISION_MODEL_BPLUS = (3 shl 4);
|
Model B+ |
BCM2835_BOARD_REVISION_MODEL_2B = (4 shl 4);
|
Model 2B (Cannot occur on BCM2835) |
BCM2835_BOARD_REVISION_MODEL_ALPHA = (5 shl 4);
|
Unknown |
BCM2835_BOARD_REVISION_MODEL_COMPUTE = (6 shl 4);
|
Compute Module |
BCM2835_BOARD_REVISION_MODEL_UNKNOWN = (7 shl 4);
|
Unknown |
BCM2835_BOARD_REVISION_MODEL_3B = (8 shl 4);
|
Model 3B (Cannot occur on BCM2835) |
BCM2835_BOARD_REVISION_MODEL_ZERO = (9 shl 4);
|
Model Zero |
BCM2835_BOARD_REVISION_PROCESSOR_MASK = ($F shl 12);
|
Processor Type |
BCM2835_BOARD_REVISION_PROCESSOR_BCM2835 = (0 shl 12);
|
BCM2835 |
BCM2835_BOARD_REVISION_PROCESSOR_BCM2836 = (1 shl 12);
|
BCM2836 (Cannot occur on BCM2835) |
BCM2835_BOARD_REVISION_PROCESSOR_BCM2837 = (2 shl 12);
|
BCM2837 (Cannot occur on BCM2835) |
BCM2835_BOARD_REVISION_MANUFACTURER_MASK = ($F shl 16);
|
Manufacturer |
BCM2835_BOARD_REVISION_MANUFACTURER_SONY = (0 shl 16);
|
Sony |
BCM2835_BOARD_REVISION_MANUFACTURER_EGOMAN = (1 shl 16);
|
Egoman |
BCM2835_BOARD_REVISION_MANUFACTURER_EMBEST = (2 shl 16);
|
Embest |
BCM2835_BOARD_REVISION_MANUFACTURER_UNKNOWN = (3 shl 16);
|
Unknown |
BCM2835_BOARD_REVISION_MANUFACTURER_EMBEST2 = (4 shl 16);
|
Embest |
BCM2835_BOARD_REVISION_MEMORY_MASK = ($7 shl 20);
|
Memory Size |
BCM2835_BOARD_REVISION_MEMORY_256M = (0 shl 20);
|
256M |
BCM2835_BOARD_REVISION_MEMORY_512M = (1 shl 20);
|
512M |
BCM2835_BOARD_REVISION_MEMORY_1024M = (2 shl 20);
|
1024M |
BCM2835_BOARD_REVISION_ENCODED_FLAG = (1 shl 23);
|
Endcoded Flag, if set then revision uses this encoding |
BCM2835_BOARD_REVISION_MASK = $00FFFFFF;
|
Mask off the warranty bits |
BCM2835 mailbox power state device constants
BCM2835_MBOX_POWER_DEVID_* BCM2835_MBOX_POWER_DEVID_SDHCI = 0;
|
|
BCM2835_MBOX_POWER_DEVID_UART0 = 1;
|
|
BCM2835_MBOX_POWER_DEVID_UART1 = 2;
|
|
BCM2835_MBOX_POWER_DEVID_USB_HCD = 3;
|
|
BCM2835_MBOX_POWER_DEVID_I2C0 = 4;
|
|
BCM2835_MBOX_POWER_DEVID_I2C1 = 5;
|
|
BCM2835_MBOX_POWER_DEVID_I2C2 = 6;
|
|
BCM2835_MBOX_POWER_DEVID_SPI = 7;
|
|
BCM2835_MBOX_POWER_DEVID_CCP2TX = 8;
|
|
BCM2835_MBOX_POWER_DEVID_UNKNOWN = $FFFFFFFF;
|
|
BCM2835 mailbox power state request constants
BCM2835_MBOX_SET_POWER_STATE_REQ_* BCM2835_MBOX_SET_POWER_STATE_REQ_OFF = (0 shl 0);
|
|
BCM2835_MBOX_SET_POWER_STATE_REQ_ON = (1 shl 0);
|
|
BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT = (1 shl 1);
|
BCM2835 mailbox power state reponse constants
BCM2835_MBOX_POWER_STATE_RESP_* BCM2835_MBOX_POWER_STATE_RESP_OFF = (0 shl 0);
|
|
BCM2835_MBOX_POWER_STATE_RESP_ON = (1 shl 0);
|
|
BCM2835_MBOX_POWER_STATE_RESP_NODEV = (1 shl 1);
|
Device doesn't exist |
BCM2835 mailbox clock state/rate id constants
BCM2835_MBOX_CLOCK_ID_* BCM2835_MBOX_CLOCK_ID_RESERVED = 0;
|
|
BCM2835_MBOX_CLOCK_ID_EMMC = 1;
|
|
BCM2835_MBOX_CLOCK_ID_UART = 2;
|
|
BCM2835_MBOX_CLOCK_ID_ARM = 3;
|
|
BCM2835_MBOX_CLOCK_ID_CORE = 4;
|
|
BCM2835_MBOX_CLOCK_ID_V3D = 5;
|
|
BCM2835_MBOX_CLOCK_ID_H264 = 6;
|
|
BCM2835_MBOX_CLOCK_ID_ISP = 7;
|
|
BCM2835_MBOX_CLOCK_ID_SDRAM = 8;
|
|
BCM2835_MBOX_CLOCK_ID_PIXEL = 9;
|
|
BCM2835_MBOX_CLOCK_ID_PWM = 10;
|
|
BCM2835_MBOX_CLOCK_ID_UNKNOWN = $FFFFFFFF;
|
|
BCM2835 mailbox clock state request constants
BCM2835_MBOX_SET_CLOCK_STATE_REQ_* BCM2835_MBOX_SET_CLOCK_STATE_REQ_OFF = (0 shl 0);
|
|
BCM2835_MBOX_SET_CLOCK_STATE_REQ_ON = (1 shl 0);
|
|
BCM2835_MBOX_SET_CLOCK_STATE_REQ_NOCLOCK = (1 shl 1);
|
Clock doesn't exist |
BCM2835 mailbox clock state response constants
BCM2835_MBOX_CLOCK_STATE_RESP_* BCM2835_MBOX_CLOCK_STATE_RESP_OFF = (0 shl 0);
|
|
BCM2835_MBOX_CLOCK_STATE_RESP_ON = (1 shl 0);
|
|
BCM2835_MBOX_CLOCK_STATE_RESP_NOCLOCK = (1 shl 1);
|
Clock doesn't exist |
BCM2835 mailbox clock rate turbo constants
BCM2835_MBOX_CLOCK_RATE_REQ_* BCM2835_MBOX_CLOCK_RATE_REQ_SKIP_TURBO = (1 shl 0);
|
BCM2835 mailbox voltage id constants
BCM2835_MBOX_VOLTAGE_ID_* BCM2835_MBOX_VOLTAGE_ID_RESERVED = $00000000;
|
|
BCM2835_MBOX_VOLTAGE_ID_CORE = $00000001;
|
|
BCM2835_MBOX_VOLTAGE_ID_SDRAM_C = $00000002;
|
|
BCM2835_MBOX_VOLTAGE_ID_SDRAM_P = $00000003;
|
|
BCM2835_MBOX_VOLTAGE_ID_SDRAM_I = $00000004;
|
BCM2835 mailbox voltage constants
BCM2835_MBOX_VOLTAGE_* BCM2835_MBOX_VOLTAGE_INVALID = $80000000;
|
A value of 0x80000000 means the id was not valid |
BCM2835 mailbox temperature id constants
BCM2835_MBOX_TEMP_ID_* BCM2835_MBOX_TEMP_ID_SOC = 0;
|
BCM2835 mailbox memory flag constants
BCM2835_MBOX_MEM_FLAG_* BCM2835_MBOX_MEM_FLAG_DISCARDABLE = (1 shl 0);
|
Can be resized to 0 at any time. Use for cached data. |
BCM2835_MBOX_MEM_FLAG_NORMAL = (0 shl 2);
|
Normal allocating alias. Don't use from ARM. |
BCM2835_MBOX_MEM_FLAG_DIRECT = (1 shl 2);
|
0xC alias uncached |
BCM2835_MBOX_MEM_FLAG_COHERENT = (2 shl 2);
|
0x8 alias. Non-allocating in L2 but coherent. |
BCM2835_MBOX_MEM_FLAG_L1_NONALLOCATING = (BCM2835_MBOX_MEM_FLAG_DIRECT or BCM2835_MBOX_MEM_FLAG_COHERENT);
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Allocating in L2 |
BCM2835_MBOX_MEM_FLAG_ZERO = (1 shl 4);
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Initialise buffer to all zeros |
BCM2835_MBOX_MEM_FLAG_NO_INIT = (1 shl 5);
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Don't initialise (default is initialise to all ones) |
BCM2835_MBOX_MEM_FLAG_HINT_PERMALOCK = (1 shl 6);
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Likely to be locked for long periods of time |
BCM2835 mailbox blank screen constants
BCM2835_MBOX_BLANK_SCREEN_* BCM2835_MBOX_BLANK_SCREEN_REQ_ON = (1 shl 0);
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BCM2835 mailbox pixel order constants
BCM2835_MBOX_PIXEL_ORDER_* BCM2835_MBOX_PIXEL_ORDER_BGR = 0;
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BCM2835_MBOX_PIXEL_ORDER_RGB = 1;
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BCM2835 mailbox alpha mode constants
BCM2835_MBOX_ALPHA_MODE_* BCM2835_MBOX_ALPHA_MODE_0_OPAQUE = 0;
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BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT = 1;
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BCM2835_MBOX_ALPHA_MODE_IGNORED = 2;
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BCM2835 mailbox palette constants
BCM2835_MBOX_PALETTE_* BCM2835_MBOX_PALETTE_INVALID = $00000001;
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BCM2835 mailbox cursor state constants
BCM2835_MBOX_CURSOR_* BCM2835_MBOX_CURSOR_INVISIBLE = 0;
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BCM2835_MBOX_CURSOR_VISIBLE = 1;
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BCM2835 mailbox cursor state flag constants
BCM2835_MBOX_CURSOR_STATE_* BCM2835_MBOX_CURSOR_STATE_DISPLAY_COORDS = (0 shl 0);
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BCM2835_MBOX_CURSOR_STATE_FRAMEBUFFER_COORDS = (1 shl 0);
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BCM2835 mailbox cursor constants
BCM2835_MBOX_CURSOR_* BCM2835_MBOX_CURSOR_INVALID = $00000001;
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BCM2835 mailbox request constants
BCM2835_MBOX_* BCM2835_MBOX_REQUEST_CODE = $00000000;
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BCM2835_MBOX_RESPONSE_CODE_SUCCESS = $80000000;
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BCM2835_MBOX_RESPONSE_CODE_ERROR = $80000001;
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BCM2835 mailbox tag request constants
BCM2835_MBOX_TAG_* BCM2835_MBOX_TAG_REQUEST_CODE = $00000000;
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BCM2835_MBOX_TAG_RESPONSE_CODE = $80000000;
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BCM2835 GPIO constants
BCM2835_GPIO_* BCM2835_GPIO_PIN_COUNT = 54;
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BCM2835_GPIO_BANK_COUNT = 2;
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BCM2835 function select register constants
BCM2835_GP* BCM2835_GPFSEL0 = $00000000;
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GPIO Function Select 0 |
BCM2835_GPFSEL1 = $00000004;
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GPIO Function Select 1 |
BCM2835_GPFSEL2 = $00000008;
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GPIO Function Select 2 |
BCM2835_GPFSEL3 = $0000000C;
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GPIO Function Select 3 |
BCM2835_GPFSEL4 = $00000010;
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GPIO Function Select 4 |
BCM2835_GPFSEL5 = $00000014;
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GPIO Function Select 5 |
| Pin Output Set Registers | |
BCM2835_GPSET0 = $0000001C;
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GPIO Pin Output Set 0 |
BCM2835_GPSET1 = $00000020;
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GPIO Pin Output Set 1 |
| Pin Output Clear Registers | |
BCM2835_GPCLR0 = $00000028;
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GPIO Pin Output Clear 0 |
BCM2835_GPCLR1 = $0000002C;
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GPIO Pin Output Clear 1 |
| Pin Level Registers | |
BCM2835_GPLEV0 = $00000034;
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GPIO Pin Level 0 |
BCM2835_GPLEV1 = $00000038;
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GPIO Pin Level 1 |
| Pin Event Detect Status Registers | |
BCM2835_GPEDS0 = $00000040;
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GPIO Pin Event Detect Status 0 |
BCM2835_GPEDS1 = $00000044;
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GPIO Pin Event Detect Status 1 |
| Pin Rising Edge Detect Enable Registers | |
BCM2835_GPREN0 = $0000004c;
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GPIO Pin Rising Edge Detect Enable 0 |
BCM2835_GPREN1 = $00000050;
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GPIO Pin Rising Edge Detect Enable 1 |
| Pin Falling Edge Detect Enable Registers | |
BCM2835_GPFEN0 = $00000058;
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GPIO Pin Falling Edge Detect Enable 0 |
BCM2835_GPFEN1 = $0000005c;
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GPIO Pin Falling Edge Detect Enable 1 |
| Pin High Detect Enable Registers | |
BCM2835_GPHEN0 = $00000064;
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GPIO Pin High Detect Enable 0 |
BCM2835_GPHEN1 = $00000068;
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GPIO Pin High Detect Enable 1 |
| Pin Low Detect Enable Registers | |
BCM2835_GPLEN0 = $00000070;
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GPIO Pin Low Detect Enable 0 |
BCM2835_GPLEN1 = $00000074;
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GPIO Pin Low Detect Enable 1 |
| Pin Async. Rising Edge Detect Registers | |
BCM2835_GPAREN0 = $0000007c;
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GPIO Pin Async. Rising Edge Detect 0 |
BCM2835_GPAREN1 = $00000080;
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GPIO Pin Async. Rising Edge Detect 1 |
| Pin Async. Falling Edge Detect Registers | |
BCM2835_GPAFEN0 = $00000088;
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GPIO Pin Async. Falling Edge Detect 0 |
BCM2835_GPAFEN1 = $0000008c;
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GPIO Pin Async. Falling Edge Detect 1 |
| Pin Pull-up/down Enable Registers | |
BCM2835_GPPUD = $00000094;
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GPIO Pin Pull-up/down Enable |
| Pin Pull-up/down Enable Clock Registers | |
BCM2835_GPPUDCLK0 = $00000098;
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GPIO Pin Pull-up/down Enable Clock 0 |
BCM2835_GPPUDCLK1 = $0000009C;
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GPIO Pin Pull-up/down Enable Clock 1 |
| Function Select Mask | |
BCM2835_GPFSEL_MASK = 7;
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| Function Select Values | |
BCM2835_GPFSEL_IN = 0;
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BCM2835_GPFSEL_OUT = 1;
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BCM2835_GPFSEL_ALT0 = 4;
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BCM2835_GPFSEL_ALT1 = 5;
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BCM2835_GPFSEL_ALT2 = 6;
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BCM2835_GPFSEL_ALT3 = 7;
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BCM2835_GPFSEL_ALT4 = 3;
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BCM2835_GPFSEL_ALT5 = 2;
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| Pin Output Set Mask | |
BCM2835_GPSET_MASK = 1;
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| Pin Output Clear Mask | |
BCM2835_GPCLR_MASK = 1;
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| Pin Level Mask | |
BCM2835_GPLEV_MASK = 1;
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| Pin Event Detect Status Mask | |
BCM2835_GPEDS_MASK = 1;
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| Pin Rising Edge Detect Enable Mask | |
BCM2835_GPREN_MASK = 1;
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| Pin Falling Edge Detect Enable Mask | |
BCM2835_GPFEN_MASK = 1;
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| Pin High Detect Enable Mask | |
BCM2835_GPHEN_MASK = 1;
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| Pin Low Detect Enable Mask | |
BCM2835_GPLEN_MASK = 1;
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| Pin Async. Rising Edge Detect Mask | |
BCM2835_GPAREN_MASK = 1;
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| Pin Async. Falling Edge Detect Mask | |
BCM2835_GPAFEN_MASK = 1;
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| Pull-up/down Enable Mask | |
BCM2835_GPPUD_MASK = 3;
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| Pull-up/down Enable Values | |
BCM2835_GPPUD_NONE = 0;
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BCM2835_GPPUD_DOWN = 1;
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|
BCM2835_GPPUD_UP = 2;
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| Pin Pull-up/down Enable Clock Mask | |
BCM2835_GPPUDCLK_MASK = 1;
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|
Type definitions
To be documented
Public variables
None defined
Function declarations
None defined
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