Difference between revisions of "Unit PlatformQEMUVPB"

Revision as of 00:46, 21 April 2017

@@ Line 640: / Line 640: @@
 ! '''Note'''
 | On the VersatilePB this comes from the 24MHz counter which will overflow every 178 seconds and increment the rollover value. This is only accurate if either ClockGetCount or ClockGetTotal is called at least once per 178 seconds on order to increment the rollover.
+|-
+|}
+</div></div>
+<br />
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;">
+<pre style="border: 0; padding-bottom:0px;">procedure QEMUVPBClockGetTimer(Data:Pointer);</pre>
+<div style="font-size: 14px; padding-left: 12px;">'''Description:''' Timer procedure to ensure ClockGetTotal is called at least once per rollover interval</div>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+! '''Note'''
+| Not intended to be called directly by applications
 |-
 |}

`QEMUVPB_PAGE_TABLE_BASE = $00004000;`	Place the first level Page Table after the interrupt vectors at 0x00001000 and before the code start at 0x00010000
`QEMUVPB_PAGE_TABLE_SIZE = SIZE_16K;`	ARMv7 first level Page Table is exactly 16KB in size (4096 32 bit (4 byte) entries)

`QEMUVPB_VECTOR_TABLE_BASE = $00001000;`	Place the Interrupt Vector Table at 0x00001000 before the code start at 0x00010000
`QEMUVPB_VECTOR_TABLE_SIZE = SIZE_64;`	The Interrupt Vector Table is exactly 64 bytes (16 32 bit (4 byte) entries)
`QEMUVPB_VECTOR_TABLE_COUNT = 8;`	The Interrupt Vector Table contains 8 entries on an ARMv7 device

`QEMUVPB_KERNEL_NAME = 'kernel.bin';`
`QEMUVPB_KERNEL_NAME = 'kernel64.bin';`
`QEMUVPB_KERNEL_CONFIG = ;`	Not available as a file
`QEMUVPB_KERNEL_COMMAND = ;`	Not available as a file

Note: Layout of the PL110 registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)
`TIMING0:LongWord;`	Horizontal Axis Panel Control Register
`TIMING1:LongWord;`	Vertical Axis Panel Control Register
`TIMING2:LongWord;`	Clock and Signal Polarity Control Register
`TIMING3:LongWord;`	Line End Control Register
`UPBASE:LongWord;`	Upper Panel Frame Base Address Registers
`LPBASE:LongWord;`	Lower Panel Frame Base Address Registers
`CONTROL:LongWord;`	Control Register Note: Reversed in VersatilePB implementation, 0x0000001c in PL110 TRM
`IMSC:LongWord;`	Interrupt Mask Set/Clear Register Note: Reversed in VersatilePB implementation, 0x00000018 in PL110 TRM
`RIS:LongWord;`	Raw Interrupt Status Register
`MIS:LongWord;`	Masked Interrupt Status Register
`ICR:LongWord;`	Interrupt Clear Register
`UPCURR:LongWord;`	Upper Panel Current Address Value Registers
`LPCURR:LongWord;`	Lower Panel Current Address Value Registers

`QEMUVPB_CPU_COUNT = VERSATILEPB_CPU_COUNT;`
`QEMUVPB_CPU_BOOT = CPU_ID_0;`
`QEMUVPB_CPU_MASK = CPU_AFFINITY_0;`

Framebuffer Properties
`Framebuffer:TFramebufferDevice;`
PL110 Properties
`Mode:LongWord;`	PL110 framebuffer mode (eg PL110_MODE_TFT)
`Depth:LongWord;`	Framebuffer color depth (eg FRAMEBUFFER_DEPTH_16)
`Width:LongWord;`	Framebuffer width in pixels
`Height:LongWord;`	Framebuffer height in pixels
`Rotation:LongWord;`	Framebuffer rotation (eg FRAMEBUFFER_ROTATION_180)
Driver Properties
`Control:LongWord;`	Preset Control register value
`Timing0:LongWord;`	Preset Timing0 register value
`Timing1:LongWord;`	Preset Timing1 register value
`Timing2:LongWord;`	Preset Timing2 register value
`Timing3:LongWord;`	Preset Timing2 register value
`Registers:PPL110CLCDRegisters;`	PL110 registers

CPUID	CPU to route IRQ to
Number	IRQ number to register
Handler	Interrupt handler function to register
HandlerEx	Extended Interrupt handler function to register
Note	Only one of Handler or HandlerEx can be specified

CPUID	CPU to route FIQ to
Number	FIQ number to register
Handler	Interrupt handler function to register
HandlerEx	Extended Interrupt handler function to register
Note	Only one of Handler or HandlerEx can be specified

CPUID	The CPU Id to register the System Call against (Ignored on QEMUVPB)
Number	The System Call number to be registered
Handler	The handler function to be registered
HandlerEx	The extended handler function to be registered
Note	Only one of Handler or HandlerEx can be specified

CPUID	The CPU Id to deregister the System Call from (Ignored on QEMUVPB)
Number	The System Call number to be deregistered
Handler	The handler function to be deregistered
HandlerEx	The extended handler function to be deregistered
Note	Only one of Handler or HandlerEx can be specified

Cycles	Number of cycles after which the timer interrupt is to be triggered
Note	This refers to native clock cycles as specified by CLOCK_FREQUENCY

Cycles	Number of cycles after which the scheduler interrupt is to be triggered
Note	This refers to native clock cycles as specified by VERSATILEPB_TIMER_FREQUENCY