|
|
| Line 572: |
Line 572: |
| | ---- | | ---- |
| | | | |
| − | ''To be documented'' | + | |
| | + | '''PL011 UART registers''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PPL011UARTRegisters = ^TPL011UARTRegisters;</code> |
| | + | |
| | + | <code>TPL011UARTRegisters = record</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | |colspan="2"|Note: Layout of the PL011 registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html) |
| | + | |- |
| | + | | <code>DR:LongWord;</code> |
| | + | | Data Register |
| | + | |- |
| | + | | <code>RSRECR:LongWord;</code> |
| | + | | Receive Status Register / Error Clear Register |
| | + | |- |
| | + | | <code>Reserved01:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved02:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved03:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved04:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>FR:LongWord;</code> |
| | + | | Flag register |
| | + | |- |
| | + | | <code>Reserved05:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>ILPR:LongWord;</code> |
| | + | | IrDA Low-Power Counter Register |
| | + | |- |
| | + | | <code>IBRD:LongWord;</code> |
| | + | | Integer Baud rate divisor |
| | + | |- |
| | + | | <code>FBRD:LongWord;</code> |
| | + | | Fractional Baud rate divisor |
| | + | |- |
| | + | | <code>LCRH:LongWord;</code> |
| | + | | Line Control register |
| | + | |- |
| | + | | <code>CR:LongWord;</code> |
| | + | | Control register |
| | + | |- |
| | + | | <code>IFLS:LongWord;</code> |
| | + | | Interrupt FIFO Level Select Register |
| | + | |- |
| | + | | <code>IMSC:LongWord;</code> |
| | + | | Interrupt Mask Set Clear Register |
| | + | |- |
| | + | | <code>RIS:LongWord;</code> |
| | + | | Raw Interrupt Status Register |
| | + | |- |
| | + | | <code>MIS:LongWord;</code> |
| | + | | Masked Interrupt Status Register |
| | + | |- |
| | + | | <code>ICR:LongWord;</code> |
| | + | | Interrupt Clear Register |
| | + | |- |
| | + | | <code>DMACR:LongWord;</code> |
| | + | | DMA Control Register |
| | + | |- |
| | + | | <code>Reserved11:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved12:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved13:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved14:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved15:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved16:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved17:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved18:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved19:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved1A:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved1B:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved1C:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>Reserved1D:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>ITCR:LongWord;</code> |
| | + | | Test Control Register |
| | + | |- |
| | + | | <code>ITIP:LongWord;</code> |
| | + | | Integration Test Input Register |
| | + | |- |
| | + | | <code>ITOP:LongWord;</code> |
| | + | | Integration Test Output Register |
| | + | |- |
| | + | | <code>TDR:LongWord;</code> |
| | + | | Test Data Register |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | |
| | + | '''PL011 UART properties''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PPL011UART = ^TPL011UART;</code> |
| | + | |
| | + | <code>TPL011UART = record</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | |colspan="2"|''UART Properties'' |
| | + | |- |
| | + | | <code>UART:TUARTDevice;</code> |
| | + | | |
| | + | |- |
| | + | |colspan="2"|''PL011 Properties'' |
| | + | | |
| | + | |- |
| | + | | <code>IRQ:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>ClockRate:LongWord;</code> |
| | + | | Device clock rate |
| | + | |- |
| | + | | <code>Registers:PPL011UARTRegisters;</code> |
| | + | | Device registers |
| | + | |- |
| | + | |colspan="2"|''Statistics Properties'' |
| | + | |- |
| | + | | <code>InterruptCount:LongWord;</code> |
| | + | | Number of interrupt requests received by the device |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | <br /> |
| | | | |
| | === Public variables === | | === Public variables === |
Revision as of 23:44, 23 January 2017
Return to Unit Reference
Description
ARM PrimeCell PL011 UART Driver unit
To be documented
Constants
[Expand]
PL011 specific constants PL011_*
PL011_UART_DESCRIPTION = 'ARM PrimeCell PL011 UART';
|
Description of PL011 device
|
|
|
PL011_UART_MIN_BAUD = 300;
|
Default minimum of 300 baud
|
PL011_UART_MAX_BAUD = 1500000;
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Default maximum based on 24MHz clock
|
|
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PL011_UART_MIN_DATABITS = SERIAL_DATA_5BIT;
|
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PL011_UART_MAX_DATABITS = SERIAL_DATA_8BIT;
|
|
|
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PL011_UART_MIN_STOPBITS = SERIAL_STOP_1BIT;
|
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PL011_UART_MAX_STOPBITS = SERIAL_STOP_2BIT;
|
|
|
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PL011_UART_MAX_PARITY = SERIAL_PARITY_EVEN;
|
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|
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PL011_UART_MAX_FLOW = SERIAL_FLOW_RTS_CTS;
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|
|
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PL011_UART_CLOCK_RATE = 24000000;
|
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[Expand]
PL011 UART data constants PL011_UART_DR_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
|
PL011_UART_DR_OE = (1 shl 11);
|
Overrun error
|
PL011_UART_DR_BE = (1 shl 10);
|
Break error
|
PL011_UART_DR_PE = (1 shl 9);
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Parity error
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PL011_UART_DR_FE = (1 shl 8);
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Framing error
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PL011_UART_DR_DATA = ($FF shl 0);
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Receive / Transmit data
|
PL011_UART_DR_ERROR = PL011_UART_DR_OE or PL011_UART_DR_BE or PL011_UART_DR_PE or PL011_UART_DR_FE;
|
[Expand]
PL011 UART receive status/error clear constants PL011_UART_RSRECR_*
[Expand]
PL011 UART flag constants PL011_UART_FR_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
|
PL011_UART_FR_RI = (1 shl 8);
|
Unsupported, write zero, read as don't care
|
PL011_UART_FR_TXFE = (1 shl 7);
|
Transmit FIFO empty
|
PL011_UART_FR_RXFF = (1 shl 6);
|
Receive FIFO full
|
PL011_UART_FR_TXFF = (1 shl 5);
|
Transmit FIFO full
|
PL011_UART_FR_RXFE = (1 shl 4);
|
Receive FIFO empty
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PL011_UART_FR_BUSY = (1 shl 3);
|
UART busy
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PL011_UART_FR_DCD = (1 shl 2);
|
Unsupported, write zero, read as don't care
|
PL011_UART_FR_DSR = (1 shl 1);
|
Unsupported, write zero, read as don't care
|
PL011_UART_FR_CTS = (1 shl 0);
|
Clear to send (This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW)
|
[Expand]
PL011 UART integer baud rate divisor constants PL011_UART_IBRD_*
[Expand]
PL011 UART fractional baud rate divisor constants PL011_UART_FBRD_*
[Expand]
PL011 UART line control constants PL011_UART_LCRH_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
|
PL011_UART_LCRH_SPS = (1 shl 7);
|
Stick parity select
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PL011_UART_LCRH_WLEN = (3 shl 5);
|
Word length
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PL011_UART_LCRH_WLEN8 = (3 shl 5);
|
8 bits
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PL011_UART_LCRH_WLEN7 = (2 shl 5);
|
7 bits
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PL011_UART_LCRH_WLEN6 = (1 shl 5);
|
6 bits
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PL011_UART_LCRH_WLEN5 = (0 shl 5);
|
5 bits
|
PL011_UART_LCRH_FEN = (1 shl 4);
|
Enable FIFOs
|
PL011_UART_LCRH_STP2 = (1 shl 3);
|
Two stop bits select
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PL011_UART_LCRH_EPS = (1 shl 2);
|
Even parity select (0 = odd parity / 1 = even parity)
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PL011_UART_LCRH_PEN = (1 shl 1);
|
Parity enable
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PL011_UART_LCRH_BRK = (1 shl 0);
|
Send break
|
[Expand]
PL011 UART control constants PL011_UART_CR_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
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PL011_UART_CR_CTSEN = (1 shl 15);
|
CTS hardware flow control enable (If this bit is set to 1 data is only transmitted when the nUARTCTS signal is asserted)
|
PL011_UART_CR_RTSEN = (1 shl 14);
|
RTS hardware flow control enable (If this bit is set to 1 data is only requested when there is space in the receive FIFO for it to be received)
|
PL011_UART_CR_OUT2 = (1 shl 13);
|
Unsupported, write zero, read as don't care.
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PL011_UART_CR_OUT1 = (1 shl 12);
|
Unsupported, write zero, read as don't care.
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PL011_UART_CR_RTS = (1 shl 11);
|
Request to send (This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW).
|
PL011_UART_CR_DTR = (1 shl 10);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_CR_RXE = (1 shl 9);
|
Receive enable
|
PL011_UART_CR_TXE = (1 shl 8);
|
Transmit enable
|
PL011_UART_CR_LBE = (1 shl 7);
|
Loopback enable
|
| Bits 6:3 Reserved - Write as 0, read as don't care
|
PL011_UART_CR_SIRLP = (1 shl 2);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_CR_SIREN = (1 shl 1);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_CR_UARTEN = (1 shl 0);
|
UART enable
|
[Expand]
PL011 UART interrupt FIFO level select constants PL011_UART_IFLS_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
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PL011_UART_IFLS_RXIFPSEL = (7 shl 9);
|
Unsupported, write zero, read as don't care
|
PL011_UART_IFLS_TXIFPSEL = (7 shl 6);
|
Unsupported, write zero, read as don't care
|
PL011_UART_IFLS_RXIFLSEL = (7 shl 3);
|
Receive interrupt FIFO level select
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PL011_UART_IFLS_RXIFLSEL1_8 = (0 shl 3);
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b000 = Receive FIFO becomes 1/8 full
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PL011_UART_IFLS_RXIFLSEL1_4 = (1 shl 3);
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b001 = Receive FIFO becomes 1/4 full
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PL011_UART_IFLS_RXIFLSEL1_2 = (2 shl 3);
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b010 = Receive FIFO becomes 1/2 full
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PL011_UART_IFLS_RXIFLSEL3_4 = (3 shl 3);
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b011 = Receive FIFO becomes 3/4 full
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PL011_UART_IFLS_RXIFLSEL7_8 = (4 shl 3);
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b100 = Receive FIFO becomes 7/8 full
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PL011_UART_IFLS_TXIFLSEL = (7 shl 0);
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Transmit interrupt FIFO level select
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PL011_UART_IFLS_TXIFLSEL1_8 = (0 shl 0);
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b000 = Transmit FIFO becomes 1/8 full
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PL011_UART_IFLS_TXIFLSEL1_4 = (1 shl 0);
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b001 = Transmit FIFO becomes 1/4 full
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PL011_UART_IFLS_TXIFLSEL1_2 = (2 shl 0);
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b010 = Transmit FIFO becomes 1/2 full
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PL011_UART_IFLS_TXIFLSEL3_4 = (3 shl 0);
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b011 = Transmit FIFO becomes 3/4 full
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PL011_UART_IFLS_TXIFLSEL7_8 = (4 shl 0);
|
b100 = Transmit FIFO becomes 7/8 full
|
[Expand]
PL011 UART interrupt mask set/clear constants PL011_UART_IMSC_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
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PL011_UART_IMSC_OEIM = (1 shl 10);
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Overrun error interrupt mask
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PL011_UART_IMSC_BEIM = (1 shl 9);
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Break error interrupt mask
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PL011_UART_IMSC_PEIM = (1 shl 8);
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Parity error interrupt mask
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PL011_UART_IMSC_FEIM = (1 shl 7);
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Framing error interrupt mask
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PL011_UART_IMSC_RTIM = (1 shl 6);
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Receive timeout interrupt mask
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PL011_UART_IMSC_TXIM = (1 shl 5);
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Transmit interrupt mask
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PL011_UART_IMSC_RXIM = (1 shl 4);
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Receive interrupt mask
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PL011_UART_IMSC_DSRMIM = (1 shl 3);
|
Unsupported, write zero, read as don't care.
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PL011_UART_IMSC_DCDMIM = (1 shl 2);
|
Unsupported, write zero, read as don't care.
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PL011_UART_IMSC_CTSMIM = (1 shl 1);
|
nUARTCTS modem interrupt mask
|
PL011_UART_IMSC_RIMIM = (1 shl 0);
|
Unsupported, write zero, read as don't care.
|
[Expand]
PL011 UART raw interrupt status constants PL011_UART_RIS_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
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PL011_UART_RIS_OERIS = (1 shl 10);
|
Overrun error interrupt status
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PL011_UART_RIS_BERIS = (1 shl 9);
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Break error interrupt status
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PL011_UART_RIS_PERIS = (1 shl 8);
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Parity error interrupt status
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PL011_UART_RIS_FERIS = (1 shl 7);
|
Framing error interrupt status
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PL011_UART_RIS_RTRIS = (1 shl 6);
|
Receive timeout interrupt status
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PL011_UART_RIS_TXRIS = (1 shl 5);
|
Transmit interrupt status
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PL011_UART_RIS_RXRIS = (1 shl 4);
|
Receive interrupt status
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PL011_UART_RIS_DSRMRIS = (1 shl 3);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_RIS_DCDMRIS = (1 shl 2);
|
Unsupported, write zero, read as don't care.
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PL011_UART_RIS_CTSMRIS = (1 shl 1);
|
nUARTCTS modem interrupt status
|
PL011_UART_RIS_RIMRIS = (1 shl 0);
|
Unsupported, write zero, read as don't care.
|
[Expand]
PL011 UART masked interrupt status constants PL011_UART_MIS_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
|
PL011_UART_MIS_OEMIS = (1 shl 10);
|
Overrun error masked interrupt status
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PL011_UART_MIS_BEMIS = (1 shl 9);
|
Break error masked interrupt status
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PL011_UART_MIS_PEMIS = (1 shl 8);
|
Parity error masked interrupt status
|
PL011_UART_MIS_FEMIS = (1 shl 7);
|
Framing error masked interrupt status
|
PL011_UART_MIS_RTMIS = (1 shl 6);
|
Receive timeout masked interrupt status
|
PL011_UART_MIS_TXMIS = (1 shl 5);
|
Transmit masked interrupt status
|
PL011_UART_MIS_RXMIS = (1 shl 4);
|
Receive masked interrupt status
|
PL011_UART_MIS_DSRMMIS = (1 shl 3);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_MIS_DCDMMIS = (1 shl 2);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_MIS_CTSMMIS = (1 shl 1);
|
nUARTCTS modem masked interrupt status
|
PL011_UART_MIS_RIMMIS = (1 shl 0);
|
Unsupported, write zero, read as don't care.
|
[Expand]
PL011 UART interrupt clear constants PL011_UART_ICR_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
|
|
|
PL011_UART_ICR_OEIC = (1 shl 10);
|
Overrun error interrupt clear
|
PL011_UART_ICR_BEIC = (1 shl 9);
|
Break error interrupt clear
|
PL011_UART_ICR_PEIC = (1 shl 8);
|
Parity error interrupt clear
|
PL011_UART_ICR_FEIC = (1 shl 7);
|
Framing error interrupt clear
|
PL011_UART_ICR_RTIC = (1 shl 6);
|
Receive timeout interrupt clear
|
PL011_UART_ICR_TXIC = (1 shl 5);
|
Transmit interrupt clear
|
PL011_UART_ICR_RXIC = (1 shl 4);
|
Receive interrupt clear
|
PL011_UART_ICR_DSRMIC = (1 shl 3);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_ICR_DCDMIC = (1 shl 2);
|
Unsupported, write zero, read as don't care.
|
PL011_UART_ICR_CTSMIC = (1 shl 1);
|
nUARTCTS modem interrupt clear
|
PL011_UART_ICR_RIMIC = (1 shl 0);
|
Unsupported, write zero, read as don't care.
|
[Expand]
PL011 UART DMA Control constants
[Expand]
PL011 UART test control constants
[Expand]
PL011 UART integration test input constants
[Expand]
PL011 UART integration test output constants
[Expand]
PL011 UART test data constants
Type definitions
PL011 UART registers
[Expand]
PPL011UARTRegisters = ^TPL011UARTRegisters;
TPL011UARTRegisters = record
| Note: Layout of the PL011 registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html)
|
DR:LongWord;
|
Data Register
|
RSRECR:LongWord;
|
Receive Status Register / Error Clear Register
|
Reserved01:LongWord;
|
|
Reserved02:LongWord;
|
|
Reserved03:LongWord;
|
|
Reserved04:LongWord;
|
|
FR:LongWord;
|
Flag register
|
Reserved05:LongWord;
|
|
ILPR:LongWord;
|
IrDA Low-Power Counter Register
|
IBRD:LongWord;
|
Integer Baud rate divisor
|
FBRD:LongWord;
|
Fractional Baud rate divisor
|
LCRH:LongWord;
|
Line Control register
|
CR:LongWord;
|
Control register
|
IFLS:LongWord;
|
Interrupt FIFO Level Select Register
|
IMSC:LongWord;
|
Interrupt Mask Set Clear Register
|
RIS:LongWord;
|
Raw Interrupt Status Register
|
MIS:LongWord;
|
Masked Interrupt Status Register
|
ICR:LongWord;
|
Interrupt Clear Register
|
DMACR:LongWord;
|
DMA Control Register
|
Reserved11:LongWord;
|
|
Reserved12:LongWord;
|
|
Reserved13:LongWord;
|
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Reserved14:LongWord;
|
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Reserved15:LongWord;
|
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Reserved16:LongWord;
|
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Reserved17:LongWord;
|
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Reserved18:LongWord;
|
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Reserved19:LongWord;
|
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Reserved1A:LongWord;
|
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Reserved1B:LongWord;
|
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Reserved1C:LongWord;
|
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Reserved1D:LongWord;
|
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ITCR:LongWord;
|
Test Control Register
|
ITIP:LongWord;
|
Integration Test Input Register
|
ITOP:LongWord;
|
Integration Test Output Register
|
TDR:LongWord;
|
Test Data Register
|
PL011 UART properties
[Expand]
PPL011UART = ^TPL011UART;
TPL011UART = record
| UART Properties
|
UART:TUARTDevice;
|
|
| PL011 Properties
|
|
IRQ:LongWord;
|
|
ClockRate:LongWord;
|
Device clock rate
|
Registers:PPL011UARTRegisters;
|
Device registers
|
| Statistics Properties
|
InterruptCount:LongWord;
|
Number of interrupt requests received by the device
|
Public variables
None defined
Function declarations
PL011 functions
[Expand]
function PL011UARTCreate(Address:LongWord; const Name:String; IRQ,ClockRate:LongWord):PUARTDevice;
Description: Create and register a new PL011 UART device which can be accessed using the UART API
| Address
|
The address of the PL011 registers
|
| Name
|
The text description of this device which will show in the device list (Optional)
|
| IRQ
|
The interrupt number for the PL011
|
| ClockRate
|
The clock source frequency for the PL011
|
| Return
|
Pointer to the new UART device or nil if the UART device could not be created
|
[Expand]
function PL011UARTDestroy(UART:PUARTDevice):LongWord;
Description: Close, deregister and destroy a PL011 UART device created by this driver
| UART
|
The UART device to destroy
|
| Return
|
ERROR_SUCCESS if completed or another error code on failure
|
PL011 UART functions
[Expand]
function PL011UARTOpen(UART:PUARTDevice; BaudRate,DataBits,StopBits,Parity,FlowControl:LongWord):LongWord;
Description: Implementation of UARTDeviceOpen API for PL011 UART
| Note
|
Not intended to be called directly by applications, use UARTDeviceOpen instead
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[Expand]
function PL011UARTClose(UART:PUARTDevice):LongWord;
Description: Implementation of UARTDeviceClose API for PL011 UART
| Note
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Not intended to be called directly by applications, use UARTDeviceClose instead
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function PL011UARTRead(UART:PUARTDevice; Buffer:Pointer; Size,Flags:LongWord; var Count:LongWord):LongWord;
Description: Implementation of UARTDeviceRead API for PL011 UART
| Note
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Not intended to be called directly by applications, use UARTDeviceRead instead
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function PL011UARTWrite(UART:PUARTDevice; Buffer:Pointer; Size,Flags:LongWord; var Count:LongWord):LongWord;
Description: Implementation of UARTDeviceWrite API for PL011 UART
| Note
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Not intended to be called directly by applications, use UARTDeviceWrite instead
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function PL011UARTStatus(UART:PUARTDevice):LongWord;
Description: Implementation of UARTDeviceStatus API for PL011 UART
| Note
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Not intended to be called directly by applications, use UARTDeviceStatus instead
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procedure PL011UARTInterruptHandler(UART:PUARTDevice);
Description: To be documented
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procedure PL011UARTReceive(UART:PUARTDevice);
Description: To be documented
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procedure PL011UARTTransmit(UART:PUARTDevice);
Description: To be documented
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