Difference between revisions of "Unit BootRPi3"
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| − | '' | + | '''Raspberry Pi 3''' |
| + | |||
| + | SoC: Broadcom BCM2837 | ||
| + | |||
| + | CPU: Cortex A53 (ARMv8) (4 @ 1200MHz) | ||
| + | Cache: L1 32KB (Per Core) / L2 512KB (Shared by all Cores) | ||
| + | |||
| + | FPU: VFPV3 | ||
| + | |||
| + | GPU: Broadcom VideoCore IV (VC4) | ||
| + | |||
| + | RAM: 1GB | ||
| + | |||
| + | USB: Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller (DWCOTG) | ||
| + | |||
| + | LAN: SMSC LAN9514 (SMSC95XX) | ||
| + | |||
| + | SD/MMC: Arasan (BCM2710) | ||
| + | |||
| + | WiFi: Broadcom (BCM43438) | ||
| + | |||
| + | Bluetooth: Broadcom (BCM43438) | ||
| + | |||
| + | Other: GPIO / SPI / I2C / I2S / PL011 (UART) / PWM / SMI / Watchdog (PM) / Random (RNG) / Timer ??? | ||
| + | |||
| + | '''Boot RPi3''' | ||
| + | |||
| + | The boot loader on the Raspberry Pi 3 will load this code at address 0x00008000 onwards and set the following registers before jumping to this code. | ||
| + | |||
| + | R0 - Zero | ||
| + | |||
| + | R1 - Machine Type (Raspberry Pi 3 or BCM2710 = 0x0C42) | ||
| + | |||
| + | R2 - Address of the ARM Tags structure (Normally 0x0100) | ||
| + | |||
| + | On entry to this code the processor will be in the following state: | ||
| + | |||
| + | World - Non Secure (Firmware causes a switch to Non Secure before jumping to Startup code) | ||
| + | |||
| + | Mode - Supervisor (ARM_MODE_SVC) Note: Firmware later than 2/10/2015 will boot in Hypervisor mode (ARM_MODE_HYP) | ||
| + | |||
| + | MMU - Disabled | ||
| + | |||
| + | FPU - Disabled | ||
| + | |||
| + | L1 Data Cache - Enabled (Firmware enabled prior to Non Secure switch) | ||
| + | |||
| + | L1 Instruction Cache - Enabled (Firmware enabled prior to Non Secure switch) | ||
| + | |||
| + | Branch Predication - Disabled | ||
| + | |||
| + | Unaligned Data Access - Enabled (Always enabled on ARMv8) | ||
| + | |||
| + | SMP Coherence - Enabled (Firmware enabled prior to Non Secure switch) | ||
| + | |||
| + | |||
| + | If the processor is in Hypervisor mode (Firmware behaviour after 2/10/2015) then Ultibo switches it to Supervisor mode during initial boot. | ||
| + | |||
| + | If the configuration option RPI3_SECURE_BOOT is set to 1 then Ultibo switches the processor back to Secure world during initial boot (see note below). | ||
| + | |||
| + | Ultibo then switches the processor to System mode for all operations and remains in either the Secure or Non Secure World as per the option above. | ||
| + | |||
| + | The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations. | ||
| + | |||
| + | Note that this code is currently identical to the Raspberry Pi 2 boot code but has been separated to allow for supporting 64 bit mode on the ARMv8 in future. Ultibo currently runs the RPi3 in 32 bit mode which is almost identical to ARMv7. | ||
=== Constants === | === Constants === | ||
Revision as of 02:26, 21 October 2016
Return to Unit Reference
Description
Raspberry Pi 3
SoC: Broadcom BCM2837
CPU: Cortex A53 (ARMv8) (4 @ 1200MHz) Cache: L1 32KB (Per Core) / L2 512KB (Shared by all Cores)
FPU: VFPV3
GPU: Broadcom VideoCore IV (VC4)
RAM: 1GB
USB: Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller (DWCOTG)
LAN: SMSC LAN9514 (SMSC95XX)
SD/MMC: Arasan (BCM2710)
WiFi: Broadcom (BCM43438)
Bluetooth: Broadcom (BCM43438)
Other: GPIO / SPI / I2C / I2S / PL011 (UART) / PWM / SMI / Watchdog (PM) / Random (RNG) / Timer ???
Boot RPi3
The boot loader on the Raspberry Pi 3 will load this code at address 0x00008000 onwards and set the following registers before jumping to this code.
R0 - Zero
R1 - Machine Type (Raspberry Pi 3 or BCM2710 = 0x0C42)
R2 - Address of the ARM Tags structure (Normally 0x0100)
On entry to this code the processor will be in the following state:
World - Non Secure (Firmware causes a switch to Non Secure before jumping to Startup code)
Mode - Supervisor (ARM_MODE_SVC) Note: Firmware later than 2/10/2015 will boot in Hypervisor mode (ARM_MODE_HYP)
MMU - Disabled
FPU - Disabled
L1 Data Cache - Enabled (Firmware enabled prior to Non Secure switch)
L1 Instruction Cache - Enabled (Firmware enabled prior to Non Secure switch)
Branch Predication - Disabled
Unaligned Data Access - Enabled (Always enabled on ARMv8)
SMP Coherence - Enabled (Firmware enabled prior to Non Secure switch)
If the processor is in Hypervisor mode (Firmware behaviour after 2/10/2015) then Ultibo switches it to Supervisor mode during initial boot.
If the configuration option RPI3_SECURE_BOOT is set to 1 then Ultibo switches the processor back to Secure world during initial boot (see note below).
Ultibo then switches the processor to System mode for all operations and remains in either the Secure or Non Secure World as per the option above.
The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.
Note that this code is currently identical to the Raspberry Pi 2 boot code but has been separated to allow for supporting 64 bit mode on the ARMv8 in future. Ultibo currently runs the RPi3 in 32 bit mode which is almost identical to ARMv7.
Constants
To be documented
Type definitions
To be documented
Public variables
To be documented
Function declarations
To be documented
Return to Unit Reference
