Difference between revisions of "Unit BootQEMUVPB"
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GPIO / I2C / Watchdog / SP804 Timer | GPIO / I2C / Watchdog / SP804 Timer | ||
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'''Boot QEMUVPB''' | '''Boot QEMUVPB''' | ||
The QMEU system emulator (qemu-system-arm) will load this code at address 0x00010000 onwards and set the following registers before jumping to this code. | The QMEU system emulator (qemu-system-arm) will load this code at address 0x00010000 onwards and set the following registers before jumping to this code. | ||
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R0 - Zero | R0 - Zero | ||
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R2 - Address of the ARM Tags structure (Normally 0x0100) | R2 - Address of the ARM Tags structure (Normally 0x0100) | ||
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On entry to this code the processor will be in the following state: | On entry to this code the processor will be in the following state: | ||
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World - Secure | World - Secure | ||
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Unaligned Data Access - Disabled | Unaligned Data Access - Disabled | ||
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Ultibo switches the processor to System mode for all operations and remains in the Secure world. | Ultibo switches the processor to System mode for all operations and remains in the Secure world. | ||
Revision as of 03:38, 23 November 2016
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Description
QEMU VersatilePB
SoC: ARM926EJ-S (Emulated)
CPU: Cortex A8 (ARMv7) (1 @ ???MHz) or Cortex A53 (ARMv8) (1 @ ???MHz)
Cache: L1 16KB / L2 0KB or L1 ??KB / L2 ??KB
FPU: VFPV3 or VFP
GPU: (None)
RAM: 256MB
USB: PCI OHCI USB controller
LAN: SMC 91c111 Ethernet adapter
SD/MMC: PL181 MultiMedia Card Interface with SD card
WiFi: (None)
Bluetooth: (None)
Other:
PL190 Vectored Interrupt Controller
Four PL011 UARTs
PL110 LCD controller
PL050 KMI with PS/2 keyboard and mouse
PCI host bridge
PCI OHCI USB controller
LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM devices
GPIO / I2C / Watchdog / SP804 Timer
Boot QEMUVPB
The QMEU system emulator (qemu-system-arm) will load this code at address 0x00010000 onwards and set the following registers before jumping to this code.
R0 - Zero
R1 - Machine Type (Versatile_PB = 0x0183)
R2 - Address of the ARM Tags structure (Normally 0x0100)
On entry to this code the processor will be in the following state:
World - Secure
Mode - Supervisor (ARM_MODE_SVC)
MMU - Disabled
FPU - Disabled
L1 Data Cache - Disabled
L1 Instruction Cache - Disabled
Branch Predication - Disabled
Unaligned Data Access - Disabled
Ultibo switches the processor to System mode for all operations and remains in the Secure world.
The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.
Constants
To be documented
Type definitions
To be documented
Public variables
To be documented
Function declarations
To be documented
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