Difference between revisions of "Unit PL011"

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----
 
----
  
−
''To be documented''
+
 
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 specific constants''' <code> PL011_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL011_UART_DESCRIPTION = 'ARM PrimeCell PL011 UART';</code>
 +
| Description of PL011 device
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MIN_BAUD = 300;</code>
 +
| Default minimum of 300 baud
 +
|-
 +
| <code>PL011_UART_MAX_BAUD = 1500000;</code>
 +
| Default maximum based on 24MHz clock
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MIN_DATABITS = SERIAL_DATA_5BIT;</code>
 +
| &nbsp;
 +
|-
 +
| <code>PL011_UART_MAX_DATABITS = SERIAL_DATA_8BIT;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MIN_STOPBITS = SERIAL_STOP_1BIT;</code>
 +
| &nbsp;
 +
|-
 +
| <code>PL011_UART_MAX_STOPBITS = SERIAL_STOP_2BIT;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MAX_PARITY = SERIAL_PARITY_EVEN;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MAX_FLOW = SERIAL_FLOW_RTS_CTS;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_CLOCK_RATE = 24000000;</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART data constants''' <code> PL011_UART_DR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_DR_OE = (1 shl 11);</code>
 +
| Overrun error
 +
|-
 +
| <code>PL011_UART_DR_BE = (1 shl 10);</code>
 +
| Break error
 +
|-
 +
| <code>PL011_UART_DR_PE = (1 shl 9);</code>
 +
| Parity error
 +
|-
 +
| <code>PL011_UART_DR_FE = (1 shl 8);</code>
 +
| Framing error
 +
|-
 +
| <code>PL011_UART_DR_DATA = ($FF shl 0);</code>
 +
| Receive / Transmit data
 +
|-
 +
|colspan="2"|<code>PL011_UART_DR_ERROR = PL011_UART_DR_OE or PL011_UART_DR_BE or PL011_UART_DR_PE or PL011_UART_DR_FE;</code>
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART receive status/error clear constants''' <code> PL011_UART_RSRECR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_RSRECR_OE = (1 shl 3);</code>
 +
| Overrun error
 +
|-
 +
| <code>PL011_UART_RSRECR_BE = (1 shl 2);</code>
 +
| Break error
 +
|-
 +
| <code>PL011_UART_RSRECR_PE = (1 shl 1);</code>
 +
| Parity error
 +
|-
 +
| <code>PL011_UART_RSRECR_FE = (1 shl 0);</code>
 +
| Framing error
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART flag constants''' <code> PL011_UART_FR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_FR_RI = (1 shl 8);</code>
 +
| Unsupported, write zero, read as don't care
 +
|-
 +
| <code>PL011_UART_FR_TXFE = (1 shl 7);</code>
 +
| Transmit FIFO empty
 +
|-
 +
| <code>PL011_UART_FR_RXFF = (1 shl 6);</code>
 +
| Receive FIFO full
 +
|-
 +
| <code>PL011_UART_FR_TXFF = (1 shl 5);</code>
 +
| Transmit FIFO full
 +
|-
 +
| <code>PL011_UART_FR_RXFE = (1 shl 4);</code>
 +
| Receive FIFO empty
 +
|-
 +
| <code>PL011_UART_FR_BUSY = (1 shl 3);</code>
 +
| UART busy
 +
|-
 +
| <code>PL011_UART_FR_DCD = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care
 +
|-
 +
| <code>PL011_UART_FR_DSR = (1 shl 1);</code>
 +
| Unsupported, write zero, read as don't care
 +
|-
 +
| <code>PL011_UART_FR_CTS = (1 shl 0);</code>
 +
| Clear to send (This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART integer baud rate divisor constants''' <code> PL011_UART_IBRD_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.htm
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_IBRD_MASK = ($FFFF shl 0);</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART fractional baud rate divisor constants ''' <code> PL011_UART_FBRD_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.htm
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_FBRD_MASK = ($3F shl 0);</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART line control constants''' <code> PL011_UART_LCRH_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_LCRH_SPS = (1 shl 7);</code>
 +
| Stick parity select
 +
|-
 +
| <code>PL011_UART_LCRH_WLEN  = (3 shl 5);</code>
 +
| Word length
 +
|-
 +
| <code>PL011_UART_LCRH_WLEN8 = (3 shl 5);</code>
 +
| 8 bits
 +
|-
 +
| <code>PL011_UART_LCRH_WLEN7 = (2 shl 5);</code>
 +
| 7 bits
 +
|-
 +
| <code>PL011_UART_LCRH_WLEN6 = (1 shl 5);</code>
 +
| 6 bits
 +
|-
 +
| <code>PL011_UART_LCRH_WLEN5 = (0 shl 5);</code>
 +
| 5 bits
 +
|-
 +
| <code>PL011_UART_LCRH_FEN = (1 shl 4);</code>
 +
| Enable FIFOs
 +
|-
 +
| <code>PL011_UART_LCRH_STP2 = (1 shl 3);</code>
 +
| Two stop bits select
 +
|-
 +
| <code>PL011_UART_LCRH_EPS = (1 shl 2);</code>
 +
| Even parity select (0 = odd parity / 1 = even parity)
 +
|-
 +
| <code>PL011_UART_LCRH_PEN = (1 shl 1);</code>
 +
| Parity enable
 +
|-
 +
| <code>PL011_UART_LCRH_BRK = (1 shl 0);</code>
 +
| Send break
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART control constants ''' <code> PL011_UART_CR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_CR_CTSEN = (1 shl 15);</code>
 +
| CTS hardware flow control enable (If this bit is set to 1 data is only transmitted when the nUARTCTS signal is asserted)
 +
|-
 +
| <code>PL011_UART_CR_RTSEN = (1 shl 14); </code>
 +
| RTS hardware flow control enable (If this bit is set to 1 data is only requested when there is space in the receive FIFO for it to be received)
 +
|-
 +
| <code>PL011_UART_CR_OUT2 = (1 shl 13);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_CR_OUT1 = (1 shl 12);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_CR_RTS = (1 shl 11);</code>
 +
| Request to send (This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW).
 +
|-
 +
| <code>PL011_UART_CR_DTR = (1 shl 10);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_CR_RXE = (1 shl 9);</code>
 +
| Receive enable
 +
|-
 +
| <code>PL011_UART_CR_TXE = (1 shl 8);</code>
 +
| Transmit enable
 +
|-
 +
| <code>PL011_UART_CR_LBE = (1 shl 7);</code>
 +
| Loopback enable
 +
|-
 +
|colspan="2"|''Bits 6:3 Reserved - Write as 0, read as don't care''
 +
|-
 +
| <code>PL011_UART_CR_SIRLP = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_CR_SIREN = (1 shl 1);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_CR_UARTEN = (1 shl 0);</code>
 +
| UART enable
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART interrupt FIFO level select constants''' <code> PL011_UART_IFLS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFPSEL = (7 shl 9);</code>
 +
| Unsupported, write zero, read as don't care
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFPSEL = (7 shl 6);</code>
 +
| Unsupported, write zero, read as don't care
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL = (7 shl 3);</code>
 +
| Receive interrupt FIFO level select
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL1_8 = (0 shl 3);</code>
 +
| b000 = Receive FIFO becomes 1/8 full
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL1_4 = (1 shl 3);</code>
 +
| b001 = Receive FIFO becomes 1/4 full
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL1_2 = (2 shl 3);</code>
 +
| b010 = Receive FIFO becomes 1/2 full
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL3_4 = (3 shl 3);</code>
 +
| b011 = Receive FIFO becomes 3/4 full
 +
|-
 +
| <code>PL011_UART_IFLS_RXIFLSEL7_8 = (4 shl 3);</code>
 +
| b100 = Receive FIFO becomes 7/8 full
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL = (7 shl 0);</code>
 +
| Transmit interrupt FIFO level select
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL1_8 = (0 shl 0);</code>
 +
| b000 = Transmit FIFO becomes 1/8 full
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL1_4 = (1 shl 0);</code>
 +
| b001 = Transmit FIFO becomes 1/4 full
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL1_2 = (2 shl 0);</code>
 +
| b010 = Transmit FIFO becomes 1/2 full
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL3_4 = (3 shl 0);</code>
 +
| b011 = Transmit FIFO becomes 3/4 full
 +
|-
 +
| <code>PL011_UART_IFLS_TXIFLSEL7_8 = (4 shl 0);</code>
 +
| b100 = Transmit FIFO becomes 7/8 full
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART interrupt mask set/clear constants''' <code> PL011_UART_IMSC_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_IMSC_OEIM = (1 shl 10);</code>
 +
| Overrun error interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_BEIM = (1 shl 9);</code>
 +
| Break error interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_PEIM = (1 shl 8);</code>
 +
| Parity error interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_FEIM = (1 shl 7);</code>
 +
| Framing error interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_RTIM = (1 shl 6);</code>
 +
| Receive timeout interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_TXIM = (1 shl 5);</code>
 +
| Transmit interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_RXIM = (1 shl 4);</code>
 +
| Receive interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_DSRMIM = (1 shl 3);</code>
 +
| Unsupported, write zero, read as don't care}.
 +
|-
 +
| <code>PL011_UART_IMSC_DCDMIM = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_IMSC_CTSMIM = (1 shl 1);</code>
 +
| nUARTCTS modem interrupt mask
 +
|-
 +
| <code>PL011_UART_IMSC_RIMIM = (1 shl 0);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART raw interrupt status constants''' <code> PL011_UART_RIS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_RIS_OERIS = (1 shl 10);</code>
 +
| Overrun error interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_BERIS = (1 shl 9);</code>
 +
| Break error interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_PERIS = (1 shl 8);</code>
 +
| Parity error interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_FERIS = (1 shl 7);</code>
 +
| Framing error interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_RTRIS = (1 shl 6);</code>
 +
| Receive timeout interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_TXRIS = (1 shl 5);</code>
 +
| Transmit interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_RXRIS = (1 shl 4);</code>
 +
| Receive interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_DSRMRIS = (1 shl 3);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_RIS_DCDMRIS = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care}.
 +
|-
 +
| <code>PL011_UART_RIS_CTSMRIS = (1 shl 1);</code>
 +
| nUARTCTS modem interrupt status
 +
|-
 +
| <code>PL011_UART_RIS_RIMRIS = (1 shl 0);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART masked interrupt status constants''' <code> PL011_UART_MIS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_MIS_OEMIS = (1 shl 10);</code>
 +
| Overrun error masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_BEMIS = (1 shl 9);</code>
 +
| Break error masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_PEMIS = (1 shl 8);</code>
 +
| Parity error masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_FEMIS = (1 shl 7);</code>
 +
| Framing error masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_RTMIS = (1 shl 6);</code>
 +
| Receive timeout masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_TXMIS = (1 shl 5);</code>
 +
| Transmit masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_RXMIS = (1 shl 4);</code>
 +
| Receive masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_DSRMMIS = (1 shl 3);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_MIS_DCDMMIS = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_MIS_CTSMMIS = (1 shl 1);</code>
 +
| nUARTCTS modem masked interrupt status
 +
|-
 +
| <code>PL011_UART_MIS_RIMMIS = (1 shl 0);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART interrupt clear constants''' <code> PL011_UART_ICR_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL011_UART_ICR_OEIC = (1 shl 10);</code>
 +
| Overrun error interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_BEIC = (1 shl 9);</code>
 +
| Break error interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_PEIC = (1 shl 8);</code>
 +
| Parity error interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_FEIC = (1 shl 7);</code>
 +
| Framing error interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_RTIC = (1 shl 6);</code>
 +
| Receive timeout interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_TXIC = (1 shl 5);</code>
 +
| Transmit interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_RXIC = (1 shl 4);</code>
 +
| Receive interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_DSRMIC = (1 shl 3);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_ICR_DCDMIC = (1 shl 2);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
| <code>PL011_UART_ICR_CTSMIC = (1 shl 1);</code>
 +
| nUARTCTS modem interrupt clear
 +
|-
 +
| <code>PL011_UART_ICR_RIMIC = (1 shl 0);</code>
 +
| Unsupported, write zero, read as don't care.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART DMA Control constants'''</div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|''This register is disabled, writing to it has no effect and reading returns 0.''
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART test control constants'''</div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART integration test input constants'''</div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART integration test output constants'''</div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL011 UART test data constants'''</div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 +
|-
 +
|}
 +
</div></div>
 +
<br />
  
 
=== Type definitions ===
 
=== Type definitions ===

Revision as of 00:00, 14 December 2016

Return to Unit Reference


Description

To be documented

Constants


PL011 specific constants PL011_*
PL011_UART_DESCRIPTION = 'ARM PrimeCell PL011 UART'; Description of PL011 device
 
PL011_UART_MIN_BAUD = 300; Default minimum of 300 baud
PL011_UART_MAX_BAUD = 1500000; Default maximum based on 24MHz clock
 
PL011_UART_MIN_DATABITS = SERIAL_DATA_5BIT;  
PL011_UART_MAX_DATABITS = SERIAL_DATA_8BIT;  
 
PL011_UART_MIN_STOPBITS = SERIAL_STOP_1BIT;  
PL011_UART_MAX_STOPBITS = SERIAL_STOP_2BIT;  
 
PL011_UART_MAX_PARITY = SERIAL_PARITY_EVEN;  
 
PL011_UART_MAX_FLOW = SERIAL_FLOW_RTS_CTS;  
 
PL011_UART_CLOCK_RATE = 24000000;  


PL011 UART data constants PL011_UART_DR_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_DR_OE = (1 shl 11); Overrun error
PL011_UART_DR_BE = (1 shl 10); Break error
PL011_UART_DR_PE = (1 shl 9); Parity error
PL011_UART_DR_FE = (1 shl 8); Framing error
PL011_UART_DR_DATA = ($FF shl 0); Receive / Transmit data
PL011_UART_DR_ERROR = PL011_UART_DR_OE or PL011_UART_DR_BE or PL011_UART_DR_PE or PL011_UART_DR_FE;


PL011 UART receive status/error clear constants PL011_UART_RSRECR_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_RSRECR_OE = (1 shl 3); Overrun error
PL011_UART_RSRECR_BE = (1 shl 2); Break error
PL011_UART_RSRECR_PE = (1 shl 1); Parity error
PL011_UART_RSRECR_FE = (1 shl 0); Framing error


PL011 UART flag constants PL011_UART_FR_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_FR_RI = (1 shl 8); Unsupported, write zero, read as don't care
PL011_UART_FR_TXFE = (1 shl 7); Transmit FIFO empty
PL011_UART_FR_RXFF = (1 shl 6); Receive FIFO full
PL011_UART_FR_TXFF = (1 shl 5); Transmit FIFO full
PL011_UART_FR_RXFE = (1 shl 4); Receive FIFO empty
PL011_UART_FR_BUSY = (1 shl 3); UART busy
PL011_UART_FR_DCD = (1 shl 2); Unsupported, write zero, read as don't care
PL011_UART_FR_DSR = (1 shl 1); Unsupported, write zero, read as don't care
PL011_UART_FR_CTS = (1 shl 0); Clear to send (This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW)


PL011 UART integer baud rate divisor constants PL011_UART_IBRD_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.htm
 
PL011_UART_IBRD_MASK = ($FFFF shl 0);  


PL011 UART fractional baud rate divisor constants PL011_UART_FBRD_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.htm
 
PL011_UART_FBRD_MASK = ($3F shl 0);  


PL011 UART line control constants PL011_UART_LCRH_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_LCRH_SPS = (1 shl 7); Stick parity select
PL011_UART_LCRH_WLEN = (3 shl 5); Word length
PL011_UART_LCRH_WLEN8 = (3 shl 5); 8 bits
PL011_UART_LCRH_WLEN7 = (2 shl 5); 7 bits
PL011_UART_LCRH_WLEN6 = (1 shl 5); 6 bits
PL011_UART_LCRH_WLEN5 = (0 shl 5); 5 bits
PL011_UART_LCRH_FEN = (1 shl 4); Enable FIFOs
PL011_UART_LCRH_STP2 = (1 shl 3); Two stop bits select
PL011_UART_LCRH_EPS = (1 shl 2); Even parity select (0 = odd parity / 1 = even parity)
PL011_UART_LCRH_PEN = (1 shl 1); Parity enable
PL011_UART_LCRH_BRK = (1 shl 0); Send break


PL011 UART control constants PL011_UART_CR_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_CR_CTSEN = (1 shl 15); CTS hardware flow control enable (If this bit is set to 1 data is only transmitted when the nUARTCTS signal is asserted)
PL011_UART_CR_RTSEN = (1 shl 14); RTS hardware flow control enable (If this bit is set to 1 data is only requested when there is space in the receive FIFO for it to be received)
PL011_UART_CR_OUT2 = (1 shl 13); Unsupported, write zero, read as don't care.
PL011_UART_CR_OUT1 = (1 shl 12); Unsupported, write zero, read as don't care.
PL011_UART_CR_RTS = (1 shl 11); Request to send (This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW).
PL011_UART_CR_DTR = (1 shl 10); Unsupported, write zero, read as don't care.
PL011_UART_CR_RXE = (1 shl 9); Receive enable
PL011_UART_CR_TXE = (1 shl 8); Transmit enable
PL011_UART_CR_LBE = (1 shl 7); Loopback enable
Bits 6:3 Reserved - Write as 0, read as don't care
PL011_UART_CR_SIRLP = (1 shl 2); Unsupported, write zero, read as don't care.
PL011_UART_CR_SIREN = (1 shl 1); Unsupported, write zero, read as don't care.
PL011_UART_CR_UARTEN = (1 shl 0); UART enable


PL011 UART interrupt FIFO level select constants PL011_UART_IFLS_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_IFLS_RXIFPSEL = (7 shl 9); Unsupported, write zero, read as don't care
PL011_UART_IFLS_TXIFPSEL = (7 shl 6); Unsupported, write zero, read as don't care
PL011_UART_IFLS_RXIFLSEL = (7 shl 3); Receive interrupt FIFO level select
PL011_UART_IFLS_RXIFLSEL1_8 = (0 shl 3); b000 = Receive FIFO becomes 1/8 full
PL011_UART_IFLS_RXIFLSEL1_4 = (1 shl 3); b001 = Receive FIFO becomes 1/4 full
PL011_UART_IFLS_RXIFLSEL1_2 = (2 shl 3); b010 = Receive FIFO becomes 1/2 full
PL011_UART_IFLS_RXIFLSEL3_4 = (3 shl 3); b011 = Receive FIFO becomes 3/4 full
PL011_UART_IFLS_RXIFLSEL7_8 = (4 shl 3); b100 = Receive FIFO becomes 7/8 full
PL011_UART_IFLS_TXIFLSEL = (7 shl 0); Transmit interrupt FIFO level select
PL011_UART_IFLS_TXIFLSEL1_8 = (0 shl 0); b000 = Transmit FIFO becomes 1/8 full
PL011_UART_IFLS_TXIFLSEL1_4 = (1 shl 0); b001 = Transmit FIFO becomes 1/4 full
PL011_UART_IFLS_TXIFLSEL1_2 = (2 shl 0); b010 = Transmit FIFO becomes 1/2 full
PL011_UART_IFLS_TXIFLSEL3_4 = (3 shl 0); b011 = Transmit FIFO becomes 3/4 full
PL011_UART_IFLS_TXIFLSEL7_8 = (4 shl 0); b100 = Transmit FIFO becomes 7/8 full


PL011 UART interrupt mask set/clear constants PL011_UART_IMSC_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_IMSC_OEIM = (1 shl 10); Overrun error interrupt mask
PL011_UART_IMSC_BEIM = (1 shl 9); Break error interrupt mask
PL011_UART_IMSC_PEIM = (1 shl 8); Parity error interrupt mask
PL011_UART_IMSC_FEIM = (1 shl 7); Framing error interrupt mask
PL011_UART_IMSC_RTIM = (1 shl 6); Receive timeout interrupt mask
PL011_UART_IMSC_TXIM = (1 shl 5); Transmit interrupt mask
PL011_UART_IMSC_RXIM = (1 shl 4); Receive interrupt mask
PL011_UART_IMSC_DSRMIM = (1 shl 3); Unsupported, write zero, read as don't care}.
PL011_UART_IMSC_DCDMIM = (1 shl 2); Unsupported, write zero, read as don't care.
PL011_UART_IMSC_CTSMIM = (1 shl 1); nUARTCTS modem interrupt mask
PL011_UART_IMSC_RIMIM = (1 shl 0); Unsupported, write zero, read as don't care.


PL011 UART raw interrupt status constants PL011_UART_RIS_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_RIS_OERIS = (1 shl 10); Overrun error interrupt status
PL011_UART_RIS_BERIS = (1 shl 9); Break error interrupt status
PL011_UART_RIS_PERIS = (1 shl 8); Parity error interrupt status
PL011_UART_RIS_FERIS = (1 shl 7); Framing error interrupt status
PL011_UART_RIS_RTRIS = (1 shl 6); Receive timeout interrupt status
PL011_UART_RIS_TXRIS = (1 shl 5); Transmit interrupt status
PL011_UART_RIS_RXRIS = (1 shl 4); Receive interrupt status
PL011_UART_RIS_DSRMRIS = (1 shl 3); Unsupported, write zero, read as don't care.
PL011_UART_RIS_DCDMRIS = (1 shl 2); Unsupported, write zero, read as don't care}.
PL011_UART_RIS_CTSMRIS = (1 shl 1); nUARTCTS modem interrupt status
PL011_UART_RIS_RIMRIS = (1 shl 0); Unsupported, write zero, read as don't care.


PL011 UART masked interrupt status constants PL011_UART_MIS_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_MIS_OEMIS = (1 shl 10); Overrun error masked interrupt status
PL011_UART_MIS_BEMIS = (1 shl 9); Break error masked interrupt status
PL011_UART_MIS_PEMIS = (1 shl 8); Parity error masked interrupt status
PL011_UART_MIS_FEMIS = (1 shl 7); Framing error masked interrupt status
PL011_UART_MIS_RTMIS = (1 shl 6); Receive timeout masked interrupt status
PL011_UART_MIS_TXMIS = (1 shl 5); Transmit masked interrupt status
PL011_UART_MIS_RXMIS = (1 shl 4); Receive masked interrupt status
PL011_UART_MIS_DSRMMIS = (1 shl 3); Unsupported, write zero, read as don't care.
PL011_UART_MIS_DCDMMIS = (1 shl 2); Unsupported, write zero, read as don't care.
PL011_UART_MIS_CTSMMIS = (1 shl 1); nUARTCTS modem masked interrupt status
PL011_UART_MIS_RIMMIS = (1 shl 0); Unsupported, write zero, read as don't care.


PL011 UART interrupt clear constants PL011_UART_ICR_*
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
PL011_UART_ICR_OEIC = (1 shl 10); Overrun error interrupt clear
PL011_UART_ICR_BEIC = (1 shl 9); Break error interrupt clear
PL011_UART_ICR_PEIC = (1 shl 8); Parity error interrupt clear
PL011_UART_ICR_FEIC = (1 shl 7); Framing error interrupt clear
PL011_UART_ICR_RTIC = (1 shl 6); Receive timeout interrupt clear
PL011_UART_ICR_TXIC = (1 shl 5); Transmit interrupt clear
PL011_UART_ICR_RXIC = (1 shl 4); Receive interrupt clear
PL011_UART_ICR_DSRMIC = (1 shl 3); Unsupported, write zero, read as don't care.
PL011_UART_ICR_DCDMIC = (1 shl 2); Unsupported, write zero, read as don't care.
PL011_UART_ICR_CTSMIC = (1 shl 1); nUARTCTS modem interrupt clear
PL011_UART_ICR_RIMIC = (1 shl 0); Unsupported, write zero, read as don't care.


PL011 UART DMA Control constants
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html
 
This register is disabled, writing to it has no effect and reading returns 0.


PL011 UART test control constants
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html


PL011 UART integration test input constants
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html


PL011 UART integration test output constants
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html


PL011 UART test data constants
See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0183g/index.html


Type definitions

To be documented

Public variables

To be documented

Function declarations


PL011 functions 

function PL011UARTCreate(Address:LongWord; const Name:String; IRQ,ClockRate:LongWord):PUARTDevice;
Description: Create and register a new PL011 UART device which can be accessed using the UART API
Address The address of the PL011 registers
Name The text description of this device which will show in the device list (Optional)
IRQ The interrupt number for the PL011
ClockRate The clock source frequency for the PL011
Return Pointer to the new UART device or nil if the UART device could not be created 


function PL011UARTDestroy(UART:PUARTDevice):LongWord;
Description: Close, deregister and destroy a PL011 UART device created by this driver
UART The UART device to destroy
Return ERROR_SUCCESS if completed or another error code on failure


PL011 UART functions 

function PL011UARTOpen(UART:PUARTDevice; BaudRate,DataBits,StopBits,Parity,FlowControl:LongWord):LongWord;
Description: Implementation of UARTDeviceOpen API for PL011 UART
Note Not intended to be called directly by applications, use UARTDeviceOpen instead 


function PL011UARTClose(UART:PUARTDevice):LongWord;
Description: Implementation of UARTDeviceClose API for PL011 UART
Note Not intended to be called directly by applications, use UARTDeviceClose instead 


function PL011UARTRead(UART:PUARTDevice; Buffer:Pointer; Size,Flags:LongWord; var Count:LongWord):LongWord;
Description: Implementation of UARTDeviceRead API for PL011 UART
Note Not intended to be called directly by applications, use UARTDeviceRead instead 


function PL011UARTWrite(UART:PUARTDevice; Buffer:Pointer; Size,Flags:LongWord; var Count:LongWord):LongWord;
Description: Implementation of UARTDeviceWrite API for PL011 UART
Note Not intended to be called directly by applications, use UARTDeviceWrite instead 


function PL011UARTStatus(UART:PUARTDevice):LongWord;
Description: Implementation of UARTDeviceStatus API for PL011 UART
Note Not intended to be called directly by applications, use UARTDeviceStatus instead 


procedure PL011UARTInterruptHandler(UART:PUARTDevice);
Description: To be documented
Note None documented 


procedure PL011UARTReceive(UART:PUARTDevice);
Description: To be documented
Note None documented 


procedure PL011UARTTransmit(UART:PUARTDevice);
Description: To be documented
Note None documented


Return to Unit Reference

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