Difference between revisions of "Unit BootRPi3"

Revision as of 02:29, 21 October 2016

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Description

Raspberry Pi 3

SoC: Broadcom BCM2837

CPU: Cortex A53 (ARMv8) (4 @ 1200MHz) Cache: L1 32KB (Per Core) / L2 512KB (Shared by all Cores)

FPU: VFPV3

GPU: Broadcom VideoCore IV (VC4)

RAM: 1GB

USB: Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller (DWCOTG)

LAN: SMSC LAN9514 (SMSC95XX)

SD/MMC: Arasan (BCM2710)

WiFi: Broadcom (BCM43438)

Bluetooth: Broadcom (BCM43438)

Other: GPIO / SPI / I2C / I2S / PL011 (UART) / PWM / SMI / Watchdog (PM) / Random (RNG) / Timer ???

Boot RPi3

The boot loader on the Raspberry Pi 3 will load this code at address 0x00008000 onwards and set the following registers before jumping to this code.

R0 - Zero

R1 - Machine Type (Raspberry Pi 3 or BCM2710 = 0x0C42)

R2 - Address of the ARM Tags structure (Normally 0x0100)

On entry to this code the processor will be in the following state:

World - Non Secure (Firmware causes a switch to Non Secure before jumping to Startup code)

Mode - Supervisor (ARM_MODE_SVC) Note: Firmware later than 2/10/2015 will boot in Hypervisor mode (ARM_MODE_HYP)

MMU - Disabled

FPU - Disabled

L1 Data Cache - Enabled (Firmware enabled prior to Non Secure switch)

L1 Instruction Cache - Enabled (Firmware enabled prior to Non Secure switch)

Branch Predication - Disabled

Unaligned Data Access - Enabled (Always enabled on ARMv8)

SMP Coherence - Enabled (Firmware enabled prior to Non Secure switch)

If the processor is in Hypervisor mode (Firmware behaviour after 2/10/2015) then Ultibo switches it to Supervisor mode during initial boot.

If the configuration option RPI3_SECURE_BOOT is set to 1 then Ultibo switches the processor back to Secure world during initial boot (see note below).

Ultibo then switches the processor to System mode for all operations and remains in either the Secure or Non Secure World as per the option above.

The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.

Note that this code is currently identical to the Raspberry Pi 2 boot code but has been separated to allow for supporting 64 bit mode on the ARMv8 in future. Ultibo currently runs the RPi3 in 32 bit mode which is almost identical to ARMv7.

ARM64 support on Raspberry Pi 3

Very little is known so far about the implementation of 64 bit mode by the RPi firmware, however some details have started to appear.

There is a config.txt switch (arm_control=0x200) which causes the firmware to boot all 4 cores in 64 bit mode instead of 32 bit mode. It appears that currently the firmware does not supply any loader code when booting in 64 bit mode and the switch kernel_old=1 also needs to be used to load the kernel image at address 0x00000000. This also means that the kernel image must deal with the startup of all 4 cores and holding the secondaries until the primary has completed the system initialization. No ATAG parameters are provided when using kernel_old=1 so command line parameters would not be available.

See this post for known information: https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=137963

It is likely that a 64 bit loader will be included in the firmware at some point in order to support Linux boot in 64 bit mode. Without it device tree support etc would not be available and therefore make Linux use the old style device setup.

Returning to Secure World:

The Raspberry Pi 3 firmware always switches to Non Secure world in order to:

a) Reset CNTVOFF (Virtual Offset register) to zero

b) Switch to Hypervisor mode (Firmware later than 2/10/2015)

It is not normally possible (by design) to return from the Non Secure world to the Secure world except by invoking the Secure Monitor which then handles any requests in the Secure world.

However due to the fact that this switch is performed by the boot loader code (loaded between 0x00000000 and 0x000000FF by the firmware) and that the code appears to set the secure, non secure and monitor vector base addresses to 0x00000000 and because all memory is writable from non secure at boot (the MMU is disabled) then the option exists to return to the Secure world as follows:

- Install a new Secure Monitor Call vector at the appropriate point in the vector table

- Clean the data cache by Modified Virtual Address at address 0x00000000

- Perform a data synchronisation barrier

- Invalidate the entire instruction cache

- Perform a data synchronisation barrier

- Perform an instruction synchronisation barrier

- Perform a Secure Monitor Call (SMC)

- From within the newly installed Secure Monitor Call read the Secure Configuration Register (SCR) mask off the Non Secure (NS) bit, rewrite the SCR and then return to Supervisor mode

Secondary cores also switch back to the Secure world using the same technique however they do not need to install the new SMC vector and instead use the one installed by the primary core.

Future changes to the firmware will hopefully not invalidate this technique, however there is also the option to use the config.txt parameter kernel_old=1 which would load Ultibo at 0x00000000 and allow us to setup the boot state independant of the firmware. This would require changes to both Ultibo (this boot module) and to the FPC compiler to change the linker start location.

Constants

To be documented

Type definitions

To be documented

Public variables

To be documented

Function declarations

To be documented

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