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|
| | ---- | | ---- |
| | | | |
| − | '''Ultibo Platform interface unit for ARMv7''' | + | '''Ultibo Platform Interface unit for ARMv7''' |
| | | | |
| | The ARMv7 does not support the SWP/SWPB instructions for syncronisation (Lock/Mutex/Semaphore etc) unless enabled. | | The ARMv7 does not support the SWP/SWPB instructions for syncronisation (Lock/Mutex/Semaphore etc) unless enabled. |
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| | |- | | |- |
| | | <code>ARMV7_CP15_C2_TTBR_NOS = (1 shl 5);</code> | | | <code>ARMV7_CP15_C2_TTBR_NOS = (1 shl 5);</code> |
| − | | Not Outer Shareable bit (0 Outer Shareable / 1 Inner Shareable) | + | | Not Outer Shareable bit (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C2_TTBR_RGN_OUTER_NONCACHED = (0 shl 3);</code> | | | <code>ARMV7_CP15_C2_TTBR_RGN_OUTER_NONCACHED = (0 shl 3);</code> |
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|
| | |- | | |- |
| | | <code>ARMV7_CP15_C2_TTBR_S = (1 shl 1);</code> | | | <code>ARMV7_CP15_C2_TTBR_S = (1 shl 1);</code> |
| − | | Shareable bit (0 Non Shareable / 1 Shareable) | + | | Shareable bit (0 Non Shareable/1 Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C2_TTBR_C_INNER_CACHED = (1 shl 0);</code> | | | <code>ARMV7_CP15_C2_TTBR_C_INNER_CACHED = (1 shl 0);</code> |
| − | | Cacheable bit (0 Inner Non Cacheable / 1 Inner Cacheable) (ARMv7-A base only) | + | | Cacheable bit (0 Inner Non Cacheable/1 Inner Cacheable) (ARMv7-A base only) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C2_TTBR_IRGN_INNER_NONCACHED = (0 shl 6) or (0 shl 0);</code> | | | <code>ARMV7_CP15_C2_TTBR_IRGN_INNER_NONCACHED = (0 shl 6) or (0 shl 0);</code> |
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|
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS7 = (1 shl 31);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS7 = (1 shl 31);</code> |
| − | | Outer Shareable property mapping for memory attributes 7, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 7, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS6 = (1 shl 30);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS6 = (1 shl 30);</code> |
| − | | Outer Shareable property mapping for memory attributes 6, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 6, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS5 = (1 shl 29);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS5 = (1 shl 29);</code> |
| − | | Outer Shareable property mapping for memory attributes 5, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 5, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS4 = (1 shl 28);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS4 = (1 shl 28);</code> |
| − | | Outer Shareable property mapping for memory attributes 4, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 4, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS3 = (1 shl 27);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS3 = (1 shl 27);</code> |
| − | | Outer Shareable property mapping for memory attributes 3, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 3, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS2 = (1 shl 26);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS2 = (1 shl 26);</code> |
| − | | Outer Shareable property mapping for memory attributes 2, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 2, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS1 = (1 shl 25);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS1 = (1 shl 25);</code> |
| − | | Outer Shareable property mapping for memory attributes 1, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 1, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NOS0 = (1 shl 24);</code> | | | <code>ARMV7_CP15_C10_PRRR_NOS0 = (1 shl 24);</code> |
| − | | Outer Shareable property mapping for memory attributes 0, if the region is mapped as Normal Shareable (0 Outer Shareable / 1 Inner Shareable) | + | | Outer Shareable property mapping for memory attributes 0, if the region is mapped as Normal Shareable (0 Outer Shareable/1 Inner Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NS1 = (1 shl 19);</code> | | | <code>ARMV7_CP15_C10_PRRR_NS1 = (1 shl 19);</code> |
| − | | Mapping of S = 1 attribute for Normal memory (0 Not Sharable / 1 Shareable) | + | | Mapping of S = 1 attribute for Normal memory (0 Not Sharable/1 Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_NS0 = (1 shl 18);</code> | | | <code>ARMV7_CP15_C10_PRRR_NS0 = (1 shl 18);</code> |
| − | | Mapping of S = 0 attribute for Normal memory (0 Not Sharable / 1 Shareable) | + | | Mapping of S = 0 attribute for Normal memory (0 Not Sharable/1 Shareable) |
| | |- | | |- |
| | | <code>ARMV7_CP15_C10_PRRR_DS1 = (1 shl 17);</code> | | | <code>ARMV7_CP15_C10_PRRR_DS1 = (1 shl 17);</code> |
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| − | ! '''Note''' | + | ! Note |
| | | None documented | | | None documented |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| − | ! '''Note''' | + | ! Note |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
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| − | ! '''Note''' | + | ! Note |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
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| − | ! '''Note''' | + | ! Note |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
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| − | ! '''Note''' | + | ! Note |
| | | None documented | | | None documented |
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| | <br /> | | <br /> |
| | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> | | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> |
| − | <pre style="border: 0; padding-bottom:0px;">procedure ARMv7Halt; assembler; nostackframe; public name'_haltproc';</pre> | + | <pre style="border: 0; padding-bottom:0px;">procedure ARMv7Halt; assembler; nostackframe; public name '_haltproc';</pre> |
| | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' The purpose of the Wait For Interrupt operation is to put the processor in to a low power state</div> | | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' The purpose of the Wait For Interrupt operation is to put the processor in to a low power state</div> |
| | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> | | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual | | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
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| − | ! '''Note''' | + | ! Note |
| | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual | | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
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| − | ! '''Note''' | + | ! Note |
| | | See Page A8-316 of the ARMv7 Architecture Reference Manual | | | See Page A8-316 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See Page A8-808 of the ARMv7 Architecture Reference Manual | | | See Page A8-808 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual | | | See Standby mode on page A8-810 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page A8-90 of the ARMv7 Architecture Reference Manual | | | See page A8-90 of the ARMv7 Architecture Reference Manual |
| | Note that this is also available in the FPC RTL as ReadBarrier/WriteBarrier See: \source\rtl\arm\arm.inc | | Note that this is also available in the FPC RTL as ReadBarrier/WriteBarrier See: \source\rtl\arm\arm.inc |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page A8-92 of the ARMv7 Architecture Reference Manual | | | See page A8-92 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page A8-102 of the ARMv7 Architecture Reference Manual | | | See page A8-102 of the ARMv7 Architecture Reference Manual |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-138 of the ARMv7 Architecture Reference Manual | | | See page B3-138 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-138 of the ARMv7 Architecture Reference Manual | | | See page B3-138 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-138 of the ARMv7 Architecture Reference Manual | | | See page B3-138 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; background: white;" | | {| class="wikitable" style="font-size: 14px; background: white;" |
| | |- | | |- |
| − | ! '''Note''' | + | ! Note |
| | | See page B3-127 of the ARMv7 Architecture Reference Manual | | | See page B3-127 of the ARMv7 Architecture Reference Manual |
| | |- | | |- |
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| | <br /> | | <br /> |
| | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> | | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> |
Exception encountered, of type "Error"