Difference between revisions of "Unit BootQEMUVPB"
| (10 intermediate revisions by the same user not shown) | |||
| Line 4: | Line 4: | ||
=== Description === | === Description === | ||
---- | ---- | ||
| + | |||
| + | '''Ultibo Initialization code for QEMU VersatilePB unit''' | ||
'''QEMU VersatilePB''' | '''QEMU VersatilePB''' | ||
SoC: ARM926EJ-S (Emulated) | SoC: ARM926EJ-S (Emulated) | ||
| − | |||
| − | CPU: Cortex A8 (ARMv7) (1 @ ???MHz) | + | CPU: Cortex A8 (ARMv7) (1 @ ???MHz) or Cortex A53 (ARMv8) (1 @ ???MHz) |
| − | + | ||
| − | or Cortex A53 (ARMv8) (1 @ ???MHz) | + | |
| − | + | Cache: L1 16KB/L2 0KB or L1 ??KB/L2 ??KB | |
| − | Cache: L1 16KB / L2 0KB | + | |
| − | + | ||
| − | or L1 ??KB / L2 ??KB | + | |
| − | + | FPU: VFPV3 or VFP | |
| − | FPU: VFPV3 | + | |
| − | + | ||
| − | or VFP | + | |
| − | + | ||
GPU: (None) | GPU: (None) | ||
| Line 38: | Line 30: | ||
Bluetooth: (None) | Bluetooth: (None) | ||
| − | |||
Other: | Other: | ||
| Line 56: | Line 47: | ||
LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM devices | LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM devices | ||
| − | + | GPIO/I2C/Watchdog/SP804 Timer | |
| − | GPIO / I2C / Watchdog / SP804 Timer | + | |
'''Boot QEMUVPB''' | '''Boot QEMUVPB''' | ||
| − | The | + | The QEMU system emulator (qemu-system-arm) will load this code at address 0x00010000 onwards and set the following registers before jumping to this code. |
| − | + | ||
R0 - Zero | R0 - Zero | ||
| Line 70: | Line 59: | ||
R2 - Address of the ARM Tags structure (Normally 0x0100) | R2 - Address of the ARM Tags structure (Normally 0x0100) | ||
| − | |||
On entry to this code the processor will be in the following state: | On entry to this code the processor will be in the following state: | ||
| − | |||
World - Secure | World - Secure | ||
| Line 90: | Line 77: | ||
Unaligned Data Access - Disabled | Unaligned Data Access - Disabled | ||
| − | |||
Ultibo switches the processor to System mode for all operations and remains in the Secure world. | Ultibo switches the processor to System mode for all operations and remains in the Secure world. | ||
| Line 99: | Line 85: | ||
---- | ---- | ||
| − | '' | + | ''None defined'' |
=== Type definitions === | === Type definitions === | ||
---- | ---- | ||
| − | '' | + | ''None defined'' |
=== Public variables === | === Public variables === | ||
---- | ---- | ||
| − | '' | + | ''None defined'' |
=== Function declarations === | === Function declarations === | ||
---- | ---- | ||
| − | |||
| + | '''Boot functions''' | ||
| + | |||
| + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> | ||
| + | <pre style="border: 0; padding-bottom:0px;">procedure Startup; assembler; nostackframe; public name '_START';</pre> | ||
| + | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' Entry point of Ultibo on QEMU VersatilePB, this will be the very first byte executed and will be loaded by QEMU at address 0x00010000</div> | ||
| + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> | ||
| + | {| class="wikitable" style="font-size: 14px; background: white;" | ||
| + | |- | ||
| + | ! Note | ||
| + | | None documented | ||
| + | |- | ||
| + | |} | ||
| + | </div></div> | ||
| + | <br /> | ||
| + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> | ||
| + | <pre style="border: 0; padding-bottom:0px;">procedure Vectors; assembler; nostackframe; </pre> | ||
| + | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' ARM exception vector table which is copied to address 0 by the StartupHandler</div> | ||
| + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> | ||
| + | {| class="wikitable" style="font-size: 14px; background: white;" | ||
| + | |- | ||
| + | ! Note | ||
| + | | See A2.6 "Exceptions" of the ARM Architecture Reference Manual | ||
| + | |- | ||
| + | |} | ||
| + | </div></div> | ||
| + | <br /> | ||
| + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;"> | ||
| + | <pre style="border: 0; padding-bottom:0px;">procedure StartupHandler; assembler; nostackframe;</pre> | ||
| + | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' Startup handler routine executed to start the Ultibo kernel</div> | ||
| + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> | ||
| + | {| class="wikitable" style="font-size: 14px; background: white;" | ||
| + | |- | ||
| + | ! Note | ||
| + | | None documented | ||
| + | |- | ||
| + | |} | ||
| + | </div></div> | ||
| + | <br /> | ||
Return to [[Unit_Reference|Unit Reference]] | Return to [[Unit_Reference|Unit Reference]] | ||
Latest revision as of 01:19, 22 April 2022
Return to Unit Reference
Description
Ultibo Initialization code for QEMU VersatilePB unit
QEMU VersatilePB
SoC: ARM926EJ-S (Emulated)
CPU: Cortex A8 (ARMv7) (1 @ ???MHz) or Cortex A53 (ARMv8) (1 @ ???MHz)
Cache: L1 16KB/L2 0KB or L1 ??KB/L2 ??KB
FPU: VFPV3 or VFP
GPU: (None)
RAM: 256MB
USB: PCI OHCI USB controller
LAN: SMC 91c111 Ethernet adapter
SD/MMC: PL181 MultiMedia Card Interface with SD card
WiFi: (None)
Bluetooth: (None)
Other:
PL190 Vectored Interrupt Controller
Four PL011 UARTs
PL110 LCD controller
PL050 KMI with PS/2 keyboard and mouse
PCI host bridge
PCI OHCI USB controller
LSI53C895A PCI SCSI Host Bus Adapter with hard disk and CD-ROM devices
GPIO/I2C/Watchdog/SP804 Timer
Boot QEMUVPB
The QEMU system emulator (qemu-system-arm) will load this code at address 0x00010000 onwards and set the following registers before jumping to this code.
R0 - Zero
R1 - Machine Type (Versatile_PB = 0x0183)
R2 - Address of the ARM Tags structure (Normally 0x0100)
On entry to this code the processor will be in the following state:
World - Secure
Mode - Supervisor (ARM_MODE_SVC)
MMU - Disabled
FPU - Disabled
L1 Data Cache - Disabled
L1 Instruction Cache - Disabled
Branch Predication - Disabled
Unaligned Data Access - Disabled
Ultibo switches the processor to System mode for all operations and remains in the Secure world.
The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.
Constants
None defined
Type definitions
None defined
Public variables
None defined
Function declarations
Boot functions
procedure Startup; assembler; nostackframe; public name '_START';
| Note | None documented |
|---|
procedure Vectors; assembler; nostackframe;
| Note | See A2.6 "Exceptions" of the ARM Architecture Reference Manual |
|---|
procedure StartupHandler; assembler; nostackframe;
| Note | None documented |
|---|
Return to Unit Reference
