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| | ---- | | ---- |
| | | | |
| − | '''Ultibo Platform interface unit for QEMU VersatilePB''' | + | '''Ultibo Platform Interface unit for QEMU VersatilePB''' |
| − | | + | |
| − | ''To be documented''
| + | |
| | | | |
| | === Constants === | | === Constants === |
| Line 19: |
Line 17: |
| | |- | | |- |
| | | <code>QEMUVPB_STARTUP_ADDRESS = $00010000;</code> | | | <code>QEMUVPB_STARTUP_ADDRESS = $00010000;</code> |
| − | | Address of StartupHandler on Reset | + | | Address of StartupHandler on Reset (Obtain from linker) |
| | |- | | |- |
| | |} | | |} |
| Line 93: |
Line 91: |
| | | <code>QEMUVPB_KERNEL_NAME = 'kernel64.bin';</code> | | | <code>QEMUVPB_KERNEL_NAME = 'kernel64.bin';</code> |
| | | | | | |
| | + | |- |
| | + | | <code>QEMUVPB_KERNEL_CONFIG = '';</code> |
| | + | | Not available as a file |
| | + | |- |
| | + | | <code>QEMUVPB_KERNEL_COMMAND = '';</code> |
| | + | | Not available as a file |
| | + | |- |
| | + | | <code>QEMUVPB_FIRMWARE_FILES = '';</code> |
| | + | | Not available as a file |
| | + | |- |
| | + | | <code>QEMUVPB_DTB_FILES = '';</code> |
| | + | | Not available as a file |
| | |- | | |- |
| | |} | | |} |
| Line 342: |
Line 352: |
| | |- | | |- |
| | | <code>PL110_CLCD_CONTROL_BGR = (1 shl 8);</code> | | | <code>PL110_CLCD_CONTROL_BGR = (1 shl 8);</code> |
| − | | RGB of BGR format selection (0 = RGB normal output/1 = BGR red and blue swapped.) | + | | RGB or BGR format selection (0 = RGB normal output/1 = BGR red and blue swapped.) |
| | |- | | |- |
| | | <code>PL110_CLCD_CONTROL_BEBO = (1 shl 9);</code> | | | <code>PL110_CLCD_CONTROL_BEBO = (1 shl 9);</code> |
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| | {| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;" | | {| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;" |
| | |- | | |- |
| − | | <code>InterruptEntries:array[0..(VERSATILEPB_IRQ_COUNT - 1)] of TInterruptEntry;</code> | + | | <code>InterruptEntries:array[0..(VERSATILEPB_IRQ_COUNT - 1)] of PInterruptEntry;</code> |
| | | style="width: 40%;"| | | | style="width: 40%;"| |
| | |- | | |- |
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| | {| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;" | | {| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;" |
| | |- | | |- |
| − | | <code>FIQEnabled:LongWord;</code> | + | | <code>FIQEnabled:array[0..1] of LongWord;</code> |
| − | | style="width: 40%;"|The single IRQ number to Enable as FIQ instead (See: TPL190InterruptRegisters) | + | | style="width: 40%;"|2 groups of FIQs to Enable/Disable (See: TPL190InterruptRegisters) |
| | |- | | |- |
| | |} | | |} |
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| | ! Note | | ! Note |
| | | Not intended to be called directly by applications, use FramebufferDeviceCommit instead. | | | Not intended to be called directly by applications, use FramebufferDeviceCommit instead. |
| − | |-
| |
| − | |}
| |
| − | </div></div>
| |
| − | <br />
| |
| − | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 0px; padding-bottom: 15px;">
| |
| − | <pre style="border: 0; padding-bottom:0px;">function QEMUVPBFramebufferDeviceSetProperties(Framebuffer:PFramebufferDevice; Properties:PFramebufferProperties):LongWord;</pre>
| |
| − | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' Implementation of FramebufferDeviceSetProperties API for PL110 Framebuffer</div>
| |
| − | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
| |
| − | {| class="wikitable" style="font-size: 14px; background: white;"
| |
| − | |-
| |
| − | ! Note
| |
| − | | Not intended to be called directly by applications, use FramebufferDeviceSetProperties instead.
| |
| | |- | | |- |
| | |} | | |} |
Latest revision as of 05:40, 7 April 2023
Return to Unit Reference
Description
Ultibo Platform Interface unit for QEMU VersatilePB
Constants
[Expand]
QEMUVPB specific constants QEMUVPB_*
QEMUVPB_STARTUP_ADDRESS = $00010000;
|
Address of StartupHandler on Reset (Obtain from linker)
|
[Expand]
QEMUVPB page table QEMUVPB_PAGE_TABLE_*
QEMUVPB_PAGE_TABLE_BASE = $00004000;
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Place the first level Page Table after the interrupt vectors at 0x00001000 and before the code start at 0x00010000
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QEMUVPB_PAGE_TABLE_SIZE = SIZE_16K;
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ARMv7 first level Page Table is exactly 16KB in size (4096 32 bit (4 byte) entries)
|
[Expand]
QEMUVPB vector table QEMUVPB_VECTOR_TABLE_*
QEMUVPB_VECTOR_TABLE_BASE = $00001000;
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Place the Interrupt Vector Table at 0x00001000 before the code start at 0x00010000
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QEMUVPB_VECTOR_TABLE_SIZE = SIZE_64;
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The Interrupt Vector Table is exactly 64 bytes (16 32 bit (4 byte) entries)
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QEMUVPB_VECTOR_TABLE_COUNT = 8;
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The Interrupt Vector Table contains 8 entries on an ARMv7 device
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[Expand]
QEMUVPB CPU count QEMUVPB_CPU_*
QEMUVPB_CPU_COUNT = VERSATILEPB_CPU_COUNT;
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QEMUVPB_CPU_BOOT = CPU_ID_0;
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QEMUVPB_CPU_MASK = CPU_AFFINITY_0;
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[Expand]
QEMUVPB SWI QEMUVPB_SWI_*
QEMUVPB_SWI_COUNT = 256;
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Number of available SWI entries
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[Expand]
QEMUVPB kernel name QEMUVPB_KERNEL_*
QEMUVPB_KERNEL_NAME = 'kernel.bin';
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QEMUVPB_KERNEL_NAME = 'kernel64.bin';
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QEMUVPB_KERNEL_CONFIG = ;
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Not available as a file
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QEMUVPB_KERNEL_COMMAND = ;
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Not available as a file
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QEMUVPB_FIRMWARE_FILES = ;
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Not available as a file
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QEMUVPB_DTB_FILES = ;
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Not available as a file
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[Expand]
PL110 specific constants PL110_*
PL110_FRAMEBUFFER_DESCRIPTION = 'ARM PrimeCell PL110 Color LCD';
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Description of PL110 device
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[Expand]
PL110 mode PL110_MODE_*
PL110_MODE_UNKNOWN = 0;
|
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PL110_MODE_VGA = 1;
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Connected to a VGA display
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PL110_MODE_SVGA = 2;
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Connected to a SVGA display
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PL110_MODE_TFT = 3;
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Connected to a TFT display
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PL110_MODE_STN = 4;
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Connected to an STN display
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[Expand]
PL110 register offset PL110_CLCD_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
|
|
|
PL110_CLCD_TIMING0 = $00000000;
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Horizontal Axis Panel Control Register
|
PL110_CLCD_TIMING1 = $00000004;
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Vertical Axis Panel Control Register
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PL110_CLCD_TIMING2 = $00000008;
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Clock and Signal Polarity Control Register
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PL110_CLCD_TIMING3 = $0000000c;
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Line End Control Register
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PL110_CLCD_UPBASE = $00000010;
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Upper Panel Frame Base Address Registers
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PL110_CLCD_LPBASE = $00000014;
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Lower Panel Frame Base Address Registers
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PL110_CLCD_CONTROL = $00000018;
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Control Register Note: Reversed in VersatilePB implementation, 0x0000001c in PL110 TRM
|
PL110_CLCD_IMSC = $0000001c;
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Interrupt Mask Set/Clear Register Note: Reversed in VersatilePB implementation, 0x00000018 in PL110 TRM
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PL110_CLCD_RIS = $00000020;
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Raw Interrupt Status Register
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PL110_CLCD_MIS = $00000024;
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Masked Interrupt Status Register
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PL110_CLCD_ICR = $00000028;
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Interrupt Clear Register
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PL110_CLCD_UPCURR = $0000002C;
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Upper Panel Current Address Value Registers
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PL110_CLCD_LPCURR = $00000030;
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Lower Panel Current Address Value Registers
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PL110_CLCD_PALETTE = $00000200;
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Color Palette Register
|
[Expand]
PL110 CLCD timing0 PL110_CLCD_TIMING0_*
[Expand]
PL110 CLCD timing1 PL110_CLCD_TIMING1_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
|
|
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PL110_CLCD_TIMING1_VBP = ($FF shl 24);
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Vertical back porch
|
PL110_CLCD_TIMING1_VFP = ($FF shl 16);
|
Vertical front porch
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PL110_CLCD_TIMING1_VSW = ($FC shl 10);
|
Vertical synchronization pulse width
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PL110_CLCD_TIMING1_LPP = ($3FF shl 0);
|
Lines per panel is the number of active lines per screen (Program to number of lines required minus 1)
|
[Expand]
PL110 CLCD timing2 PL110_CLCD_TIMING2_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
|
|
|
PL110_CLCD_TIMING2_PCD_HI = ($1F shl 27);
|
Upper five bits of Panel Clock Divisor
|
PL110_CLCD_TIMING2_BCD = (1 shl 26);
|
Bypass pixel clock divider
|
PL110_CLCD_TIMING2_CPL = ($3FF shl 16);
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Clocks per line
|
PL110_CLCD_TIMING2_IOE = (1 shl 14);
|
Invert output enable
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PL110_CLCD_TIMING2_IPC = (1 shl 13);
|
Invert panel clock
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PL110_CLCD_TIMING2_IHS = (1 shl 12);
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Invert horizontal synchron
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PL110_CLCD_TIMING2_IVS = (1 shl 11);
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Invert vertical synchronization
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PL110_CLCD_TIMING2_ACB = ($1F shl 6);
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AC bias pin frequency
|
PL110_CLCD_TIMING2_CLKSEL = (1 shl 5);
|
This bit drives the CLCDCLKSEL signal which is used as the select signal for the external LCD clock multiplexor
|
PL110_CLCD_TIMING2_PCD_LO = ($1F shl 0);
|
Lower five bits of Panel Clock Divisor
|
[Expand]
PL110 CLCD timing3 PL110_CLCD_TIMING3_*
[Expand]
PL110 CLCD control PL110_CLCD_CONTROL_*
| See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
|
|
|
PL110_CLCD_CONTROL_LCDEN = (1 shl 0);
|
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PL110_CLCD_CONTROL_LCDBPP1 = (0 shl 1);
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LCD bits per pixel: 000 = 1 bpp
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PL110_CLCD_CONTROL_LCDBPP2 = (1 shl 1);
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LCD bits per pixel: 001 = 2 bpp
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PL110_CLCD_CONTROL_LCDBPP4 = (2 shl 1);
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LCD bits per pixel: 010 = 4 bpp
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PL110_CLCD_CONTROL_LCDBPP8 = (3 shl 1);
|
LCD bits per pixel: 011 = 8 bpp
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PL110_CLCD_CONTROL_LCDBPP16 = (4 shl 1);
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LCD bits per pixel: 100 = 16 bpp
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PL110_CLCD_CONTROL_LCDBPP16_565 = (6 shl 1);
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LCD bits per pixel: 110 = 16 bpp 565 (PL111 only)
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PL110_CLCD_CONTROL_LCDBPP16_444 = (7 shl 1);
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LCD bits per pixel: 111 = 16 bpp 444 (PL111 only)
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PL110_CLCD_CONTROL_LCDBPP24 = (5 shl 1);
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LCD bits per pixel: 101 = 24 bpp
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PL110_CLCD_CONTROL_LCDBW = (1 shl 4);
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STN LCD is monochrome (black and white) (0 = STN LCD is color/1 = STN LCD is monochrome)
|
PL110_CLCD_CONTROL_LCDTFT = (1 shl 5);
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LCD is TFT (0 = LCD is an STN display, use gray scaler/1 = LCD is TFT, do not use gray scaler)
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PL110_CLCD_CONTROL_LCDMONO8 = (1 shl 6);
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Monochrome LCD has an 8-bit interface (0 = mono LCD uses 4-bit interface/1 = mono LCD uses 8-bit interface)
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PL110_CLCD_CONTROL_LCDDUAL = (1 shl 7);
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LCD interface is dual panel STN (0 = single panel LCD is in use/1 = dual panel LCD is in use)
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PL110_CLCD_CONTROL_BGR = (1 shl 8);
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RGB or BGR format selection (0 = RGB normal output/1 = BGR red and blue swapped.)
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PL110_CLCD_CONTROL_BEBO = (1 shl 9);
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Big-endian byte order (0 = little-endian byte order/1 = big-endian byte order)
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PL110_CLCD_CONTROL_BEPO = (1 shl 10);
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Big-endian pixel ordering within a byte (0 = little-endian pixel ordering within a byte/1= big-endian pixel ordering within a byte)
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PL110_CLCD_CONTROL_LCDPWR = (1 shl 11);
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LCD power enable
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PL110_CLCD_CONTROL_LCDVCOMP_VSYNC = (0 shl 12);
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Generate interrupt at: 00 = start of vertical synchronization
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PL110_CLCD_CONTROL_LCDVCOMP_BPORCH = (1 shl 12);
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Generate interrupt at: 01 = start of back porch
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PL110_CLCD_CONTROL_LCDVCOMP_VIDEO = (2 shl 12);
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Generate interrupt at: 10 = start of active video
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PL110_CLCD_CONTROL_LCDVCOMP_FPORCH = (3 shl 12);
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Generate interrupt at: 11 = start of front porch
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PL110_CLCD_CONTROL_LDMAFIFOTIME = (1 shl 15);
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Unknown
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PL110_CLCD_CONTROL_WATERMARK = (1 shl 16);
|
LCD DMA FIFO Watermark level
|
[Expand]
PL110 control PL110_CONTROL_*
PL110_CONTROL_VGA = PL110_CLCD_CONTROL_LCDTFT or PL110_CLCD_CONTROL_LCDVCOMP_BPORCH;
|
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PL110_CONTROL_SVGA = PL110_CLCD_CONTROL_LCDTFT or PL110_CLCD_CONTROL_LCDVCOMP_BPORCH;
|
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[Expand]
PL110 timing0 PL110_TIMING0_*
PL110_TIMING0_VGA = $3F1F3F9C;
|
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PL110_TIMING0_SVGA = $1313A4C4;
|
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[Expand]
PL110 timing1 PL110_TIMING1_*
PL110_TIMING1_VGA = $090B61DF;
|
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PL110_TIMING1_SVGA = $0505F657;
|
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[Expand]
PL110 timing2 PL110_TIMING2_*
PL110_TIMING2_VGA = $067F1800;
|
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PL110_TIMING2_SVGA = $071F1800;
|
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Type definitions
PL110 CLCD registers
[Expand]
PPL110CLCDRegisters = ^TPL110CLCDRegisters;
TPL110CLCDRegisters = record
| Note: Layout of the PL110 registers (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html)
|
TIMING0:LongWord;
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Horizontal Axis Panel Control Register
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TIMING1:LongWord;
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Vertical Axis Panel Control Register
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TIMING2:LongWord;
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Clock and Signal Polarity Control Register
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TIMING3:LongWord;
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Line End Control Register
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UPBASE:LongWord;
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Upper Panel Frame Base Address Registers
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LPBASE:LongWord;
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Lower Panel Frame Base Address Registers
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CONTROL:LongWord;
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Control Register Note: Reversed in VersatilePB implementation, 0x0000001c in PL110 TRM
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IMSC:LongWord;
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Interrupt Mask Set/Clear Register Note: Reversed in VersatilePB implementation, 0x00000018 in PL110 TRM
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RIS:LongWord;
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Raw Interrupt Status Register
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MIS:LongWord;
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Masked Interrupt Status Register
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ICR:LongWord;
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Interrupt Clear Register
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UPCURR:LongWord;
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Upper Panel Current Address Value Registers
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LPCURR:LongWord;
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Lower Panel Current Address Value Registers
|
PL110 framebuffer
[Expand]
PPL110Framebuffer = ^TPL110Framebuffer;
TPL110Framebuffer = record
| Framebuffer Properties
|
Framebuffer:TFramebufferDevice;
|
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| PL110 Properties
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Mode:LongWord;
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PL110 framebuffer mode (eg PL110_MODE_TFT)
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Depth:LongWord;
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Framebuffer color depth (eg FRAMEBUFFER_DEPTH_16)
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Width:LongWord;
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Framebuffer width in pixels
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Height:LongWord;
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Framebuffer height in pixels
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Rotation:LongWord;
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Framebuffer rotation (eg FRAMEBUFFER_ROTATION_180)
|
| Driver Properties
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Control:LongWord;
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Preset Control register value
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Timing0:LongWord;
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Preset Timing0 register value
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Timing1:LongWord;
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Preset Timing1 register value
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Timing2:LongWord;
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Preset Timing2 register value
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Timing3:LongWord;
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Preset Timing2 register value
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Registers:PPL110CLCDRegisters;
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PL110 registers
|
Public variables
QEMUVPB specific Ultibo variables
QEMUVPBInitialized:Boolean;
|
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Clock variables
ClockGetLast:LongWord;
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Value of 24MHz Counter on last ClockGetCount or ClockGetTotal call
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ClockGetBase:Int64;
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Base value for 64-bit clock, incremented each time the 24MHz Counter rolls over (Only accurate if ClockGetCount/ClockGetTotal is called at least once per 178 seconds)
|
ClockGetLock:THandle = INVALID_HANDLE_VALUE;
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Lock handle for creating 64-bit clock from a 32-bit register
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ClockGetTimer:THandle = INVALID_HANDLE_VALUE;
|
Timer handle for ensuring clock is read periodically to maintain accurracy
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Timer variables
Timer0Registers:PSP804TimerRegisters;
|
Use Timer0 for Clock
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Timer2Registers:PSP804TimerRegisters;
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Use Timer2 for Scheduler
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Interrupt variables
PrimaryInterruptRegisters:PPL190InterruptRegisters;
|
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SecondaryInterruptRegisters:PVersatilePBInterruptRegisters;
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InterruptEntries:array[0..(VERSATILEPB_IRQ_COUNT - 1)] of PInterruptEntry;
|
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System call
SystemCallEntries:array[0..QEMUVPB_SWI_COUNT - 1] of TSystemCallEntry;
|
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IRQ/FIQ
IRQEnabled:array[0..1] of LongWord;
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2 groups of IRQs to Enable/Disable (See: TPL190InterruptRegisters)
|
FIQEnabled:array[0..1] of LongWord;
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2 groups of FIQs to Enable/Disable (See: TPL190InterruptRegisters)
|
Function declarations
Initialization functions
[Expand]
procedure QEMUVPBInit;
Description: To be documented
QEMUVPB platform functions
[Expand]
procedure QEMUVPBBoardInit;
Description: To be documented
[Expand]
procedure QEMUVPBMemoryInit;
Description: To be documented
[Expand]
procedure QEMUVPBClockInit;
Description: To be documented
[Expand]
procedure QEMUVPBPowerInit;
Description: To be documented
[Expand]
procedure QEMUVPBInterruptInit;
Description: To be documented
[Expand]
procedure QEMUVPBPeripheralInit;
Description: To be documented
[Expand]
procedure QEMUVPBFramebufferInit;
Description: To be documented
[Expand]
procedure QEMUVPBPageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU
[Expand]
function QEMUVPBRequestExIRQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request registration of the supplied handler to the specified IRQ number
[Expand]
function QEMUVPBReleaseExIRQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request deregistration of the supplied handler from the specified IRQ number
[Expand]
function QEMUVPBRequestExFIQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request registration of the supplied handler to the specified FIQ number
[Expand]
function QEMUVPBReleaseExFIQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request deregistration of the supplied handler from the specified FIQ number
[Expand]
function QEMUVPBRegisterInterrupt(Number,Mask,Priority,Flags:LongWord; Handler:TSharedInterruptHandler; Parameter:Pointer):LongWord;
Description: Request registration of the supplied handler to the specified interrupt number (Where Applicable)
[Expand]
function QEMUVPBDeregisterInterrupt(Number,Mask,Priority,Flags:LongWord; Handler:TSharedInterruptHandler; Parameter:Pointer):LongWord;
Description: Request deregistration of the supplied handler from the specified interrupt number (Where Applicable)
[Expand]
function QEMUVPBRegisterSystemCallEx(CPUID,Number:LongWord; Handler:TSystemCallHandler; HandlerEx:TSystemCallExHandler):LongWord;
Description: Request registration of the supplied extended handler to the specified System Call number
[Expand]
function QEMUVPBDeregisterSystemCallEx(CPUID,Number:LongWord; Handler:TSystemCallHandler; HandlerEx:TSystemCallExHandler):LongWord;
Description: Request deregistration of the supplied extended handler from the specified System Call number
[Expand]
function QEMUVPBGetInterruptEntry(Number,Instance:LongWord; var Interrupt:TInterruptEntry):LongWord;
Description: Get the interrupt entry for the specified interrupt number and instance
| Note
|
Get the interrupt entry for the specified interrupt number
|
[Expand]
function QEMUVPBGetSystemCallEntry(Number:LongWord):TSystemCallEntry;
Description: Get the system call entry for the specified system call number
[Expand]
function QEMUVPBSystemRestart(Delay:LongWord):LongWord;
Description: To be documented
[Expand]
function QEMUVPBSystemShutdown(Delay:LongWord):LongWord;
Description: To be documented
[Expand]
function QEMUVPBClockGetCount:LongWord;
Description: Gets the current system clock count (32 least significant bits of total)
| Note
|
On the VersatilePB this comes from the 24MHz counter which will overflow every 178 seconds and increment the rollover value. Because we return the lower 32 bits then the value returned by this function will rollover to zero every 4295 seconds or about every 71 minutes.
|
[Expand]
function QEMUVPBClockGetTotal:Int64;
Description: Gets the total system clock count
| Note
|
On the VersatilePB this comes from the 24MHz counter which will overflow every 178 seconds and increment the rollover value. This is only accurate if either ClockGetCount or ClockGetTotal is called at least once per 178 seconds in order to increment the rollover.
|
[Expand]
procedure QEMUVPBClockGetTimer(Data:Pointer);
Description: Timer procedure to ensure ClockGetTotal is called at least once per rollover interval
| Note
|
Not intended to be called directly by applications
|
QEMUVPB thread functions
[Expand]
procedure QEMUVPBSchedulerInit;
Description: Initialize the scheduler interrupt on the boot CPU
QEMUVPB clock functions
[Expand]
procedure QEMUVPBClockInterrupt(Parameter:Pointer);
Description: Interrupt handler function for the clock interrupt
| Note
|
This schedules another clock interrupt to occur CLOCK_CYCLES_PER_TICK in the future, then updates ClockTicks and ClockSeconds and checks for timers to trigger.
|
[Expand]
procedure QEMUVPBClockUpdate(Cycles:LongWord; var Last:LongWord);
Description: Setup a clock interrupt to trigger after the specified number of clock cycles
| Cycles
|
Number of cycles after which the timer interrupt is to be triggered
|
| Note
|
This refers to native clock cycles as specified by CLOCK_FREQUENCY
|
QEMUVPB scheduler functions
[Expand]
function QEMUVPBSchedulerInterrupt(CPUID:LongWord; Thread:TThreadHandle; Parameter:Pointer):TThreadHandle;
Description: Interrupt handler function for the scheduler interrupt
| Note
|
This schedules another scheduler interrupt to occur SCHEDULER_CLOCKS_PER_INTERRUPT in the future, then checks for threads to wakeup or timeout and the next thread to schedule.
|
[Expand]
procedure QEMUVPBSchedulerUpdate(Cycles:LongWord; var Last:LongWord);
Description: Setup a scheduler interrupt to trigger after the specified number of clock cycles
| Cycles
|
Number of cycles after which the scheduler interrupt is to be triggered
|
| Note
|
This refers to native clock cycles as specified by VERSATILEPB_TIMER_FREQUENCY
|
[Expand]
procedure QEMUVPBSchedulerSystemCall(Request:PSystemCallRequest);
Description: System Call handler for the scheduler
| Note
|
This is registered to receive requests for the SYSTEM_CALL_CONTEXT_SWITCH and will perform a context switch from within an SWI
|
QEMUVPB framebuffer functions
[Expand]
function QEMUVPBFramebufferDeviceAllocate(Framebuffer:PFramebufferDevice; Properties:PFramebufferProperties):LongWord;
Description: Implementation of FramebufferDeviceAllocate API for PL110 Framebuffer
| Note
|
Not intended to be called directly by applications, use FramebufferDeviceAllocate instead.
|
[Expand]
function QEMUVPBFramebufferDeviceRelease(Framebuffer:PFramebufferDevice):LongWord;
Description: Implementation of FramebufferDeviceRelease API for PL110 Framebuffer
| Note
|
Not intended to be called directly by applications, use FramebufferDeviceRelease instead.
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[Expand]
function QEMUVPBFramebufferDeviceBlank(Framebuffer:PFramebufferDevice; Blank:Boolean):LongWord;
Description: Implementation of FramebufferDevicBlank API for PL110 Framebuffer
| Note
|
Not intended to be called directly by applications, use FramebufferDevicBlank instead.
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[Expand]
function QEMUVPBFramebufferDeviceCommit(Framebuffer:PFramebufferDevice; Address:PtrUInt; Size,Flags:LongWord):LongWord;
Description: Implementation of FramebufferDeviceCommit API for PL110 Framebuffer
| Note
|
Not intended to be called directly by applications, use FramebufferDeviceCommit instead.
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QEMUVPB helper functions
[Expand]
procedure QEMUVPBBootBlink; assembler; nostackframe;
Description: Output characters to UART0 without dependency on any other RTL setup
[Expand]
procedure QEMUVPBBootOutput(Value:LongWord);
Description: Output characters to UART0 without dependency on any other RTL setup
[Expand]
procedure QEMUVPBBootConsoleStart;
Description: To be documented
[Expand]
procedure QEMUVPBBootConsoleWrite(const Value:String);
Description: To be documented
[Expand]
procedure QEMUVPBBootConsoleWriteEx(const Value:String; X,Y:LongWord);
Description: To be documented
[Expand]
function QEMUVPBBootConsoleGetX:LongWord;
Description: To be documented
[Expand]
function QEMUVPBBootConsoleGetY:LongWord;
Description: To be documented
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