Difference between revisions of "Unit GENET"

Latest revision as of 06:27, 3 August 2022

`UMAC_HD_BKP_CTRL = $004;`
`HD_FC_EN = (1 shl 0);`
`HD_FC_BKOFF_OK = (1 shl 1);`
`IPG_CONFIG_RX_SHIFT = 2;`
`IPG_CONFIG_RX_MASK = $1F;`

`UMAC_CMD = $008;`
`CMD_TX_EN = (1 shl 0);`
`CMD_RX_EN = (1 shl 1);`
`UMAC_SPEED_10 = 0;`
`UMAC_SPEED_100 = 1;`
`UMAC_SPEED_1000 = 2;`
`UMAC_SPEED_2500 = 3;`
`CMD_SPEED_SHIFT = 2;`
`CMD_SPEED_MASK = 3;`
`CMD_PROMISC = (1 shl 4);`
`CMD_PAD_EN = (1 shl 5);`
`CMD_CRC_FWD = (1 shl 6);`
`CMD_PAUSE_FWD = (1 shl 7);`
`CMD_RX_PAUSE_IGNORE = (1 shl 8);`
`CMD_TX_ADDR_INS = (1 shl 9);`
`CMD_HD_EN = (1 shl 10);`
`CMD_SW_RESET = (1 shl 13);`
`CMD_LCL_LOOP_EN = (1 shl 15);`
`CMD_AUTO_CONFIG = (1 shl 22);`
`CMD_CNTL_FRM_EN = (1 shl 23);`
`CMD_NO_LEN_CHK = (1 shl 24);`
`CMD_RMT_LOOP_EN = (1 shl 25);`
`CMD_PRBL_EN = (1 shl 27);`
`CMD_TX_PAUSE_IGNORE = (1 shl 28);`
`CMD_TX_RX_EN = (1 shl 29);`
`CMD_RUNT_FILTER_DIS = (1 shl 30);`

`UMAC_MAC0 = $00C;`
`UMAC_MAC1 = $010;`
`UMAC_MAX_FRAME_LEN = $014;`

`UMAC_MODE = $44;`
`MODE_LINK_STATUS = (1 shl 5);`

`UMAC_EEE_CTRL = $064;`
`EN_LPI_RX_PAUSE = (1 shl 0);`
`EN_LPI_TX_PFC = (1 shl 1);`
`EN_LPI_TX_PAUSE = (1 shl 2);`
`EEE_EN = (1 shl 3);`
`RX_FIFO_CHECK = (1 shl 4);`
`EEE_TX_CLK_DIS = (1 shl 5);`
`DIS_EEE_10M = (1 shl 6);`
`LP_IDLE_PREDICTION_MODE = (1 shl 7);`

`UMAC_EEE_LPI_TIMER = $068;`
`UMAC_EEE_WAKE_TIMER = $06C;`
`UMAC_EEE_REF_COUNT = $070;`
`EEE_REFERENCE_COUNT_MASK = $ffff;`

`UMAC_TX_FLUSH = $334;`

`UMAC_MIB_START = $400;`

`UMAC_MDIO_CMD = $614;`
`MDIO_START_BUSY = (1 shl 29);`
`MDIO_READ_FAIL = (1 shl 28);`
`MDIO_RD = (2 shl 26);`
`MDIO_WR = (1 shl 26);`
`MDIO_PMD_SHIFT = 21;`
`MDIO_PMD_MASK = $1F;`
`MDIO_REG_SHIFT = 16;`
`MDIO_REG_MASK = $1F;`

`UMAC_RBUF_OVFL_CNT_V1 = $61C;`
`RBUF_OVFL_CNT_V2 = $80;`
`RBUF_OVFL_CNT_V3PLUS = $94;`

`UMAC_MPD_CTRL = $620;`
`MPD_EN = (1 shl 0);`
`MPD_PW_EN = (1 shl 27);`
`MPD_MSEQ_LEN_SHIFT = 16;`
`MPD_MSEQ_LEN_MASK = $FF;`

`UMAC_MPD_PW_MS = $624;`
`UMAC_MPD_PW_LS = $628;`
`UMAC_RBUF_ERR_CNT_V1 = $634;`
`RBUF_ERR_CNT_V2 = $84;`
`RBUF_ERR_CNT_V3PLUS = $98;`
`UMAC_MDF_ERR_CNT = $638;`
`UMAC_MDF_CTRL = $650;`
`UMAC_MDF_ADDR = $654;`
`UMAC_MIB_CTRL = $580;`
`MIB_RESET_RX = (1 shl 0);`
`MIB_RESET_RUNT = (1 shl 1);`
`MIB_RESET_TX = (1 shl 2);`

[Expand]

Receive buffer registers RBUF_*

[Expand]

Hardware filter block (HFB) RBUF_HFB_*

[Expand]

Transmit buffer registers TBUF_*

[Expand]

Hardware filter block (HFB) registers HFB_*

[Expand]

UniMAC INTRL2 registers INTRL2_CPU_*

[Expand]

UniMAC INTRL2 IRQ0 definitions UMAC_IRQ0_*

[Expand]

UniMAC INTRL2 IRQ1 definitions UMAC_IRQ1_*

[Expand]

GENET register block offsets GENET_*_OFF

[Expand]

SYS block offsets and register definitions SYS_*

[Expand]

Ext block register offsets and definitions EXT_*

[Expand]

DMA rings size DMA_RING_SIZE*

[Expand]

DMA registers common definitions DMA_RW_POINTER_*

[Expand]

DMA ring size register DMA_RING_*

[Expand]

DMA interrupt threshold register DMA_INTR_*

[Expand]

DMA XON/XOFF register DMA_XON_THREHOLD_*

[Expand]

DMA flow period register DMA_FLOW_*

[Expand]

DMA control register DMA_EN_*

[Expand]

DMA status register DMA_DESC_*

[Expand]

DMA SCB burst size register DMA_SCB_BURST_*

[Expand]

DMA activity vector register DMA_ACTIVITY_*

[Expand]

DMA backpressure mask register DMA_BACKPRESSURE_MASK*

[Expand]

DMA backpressure status register DMA_BACKPRESSURE_*

[Expand]

DMA override register DMA_*_MODE_*

[Expand]

DMA timeout register DMA_TIMEOUT_*

[Expand]

TDMA rate limiting control register DMA_RATE_*

[Expand]

TDMA arbitration control register DMA_ARBITER_*

[Expand]

TX/RX DMA descriptor common bits DMA_BUFLENGTH_*

[Expand]

TX specific DMA descriptor bits DMA_TX_*

[Expand]

RX specific DMA descriptor bits DMA_RX_*

[Expand]

GENET power management mode GENET_POWER_*

[Expand]

GENET hardware flags GENET_HAS_*

[Expand]

RX/TX DMA registers DMA_CTRL*

[Expand]

RDMA/TDMA ring registers TDMA_*

[Expand]

UniMAC specific constants MDIO_*

[Expand]

Broadcom PHY ID PHY_ID_BCM*

[Expand]

Broadcom PHY flags PHY_BCM_FLAGS_*

[Expand]

Broadcom BCM54XX register definitions MII_BCM54XX_*

[Expand]

Broadcom auxilliary control shadow access registers MII_BCM54XX_AUXCTL_*

[Expand]

Broadcom LED source encodings BCM_LED_SRC_*

[Expand]

Broadcom multicolor LED configurations (expansion register 4) BCM_*_MULTICOLOR*

[Expand]

BCM5482 shadow registers BCM54XX_SHD_*

[Expand]

Expansion shadow access registers MII_BCM54XX_EXP_*

[Expand]

BCM5482 secondary SerDes registers BCM5482_SSD_*

[Expand]

BCM54810 registers BCM54810_*

Type definitions

GENET network

[Expand]

PGENETNetwork = ^TGENETNetwork;

TGENETNetwork = record

Network Properties
`Network:TNetworkDevice;`
Driver Properties
`IRQ0:LongWord;`
`IRQ1:LongWord;`
`Address:Pointer;`	Device register base address
`MDIOOffset:LongWord;`
`Lock:TSpinHandle;`	Device lock (Differs from lock in Network device) (Spin lock due to use by interrupt handler)
`Version:LongWord;`	Device version (GENET_V1..GENETV5)
`PhyRevision:LongWord;`	PHY revision (GENET_V1..GENETV4 devices only)
`Status64Enable:LongBool;`	True if 64 byte RX/TX status block is enabled (for hardware checksum etc)
`RXChecksumEnable:LongBool;`	True if RX checksum is enabled
`CRCForwardEnable:LongBool;`	True if CRC forwarding is enabled
`IRQStatus:LongWord;`	Non TX/RX interrupts forwarded to worker thread for servicing
`PendingCount:LongWord;`	Number of worker requests pending for this network
`WaiterThread:TThreadId;`	Thread waiting for pending requests to complete (for network close)
`StatusTimer:TTimerHandle;`	Timer for status change detection
Hardware Parameters (Version specific)
`TXQueues:LongWord;`
`TXDescriptorsPerQueue:LongWord;`
`RXQueues:LongWord;`
`RXDescriptorsPerQueue:LongWord;`
`BackPressureEnableShift:LongWord;`
`BackPressureMask:LongWord;`
`HFBFilterCount:LongWord;`
`HFBFilterSize:LongWord;`
`QTAGMask:LongWord;`
`TXBufferOffset:LongWord;`
`HFBOffset:LongWord;`
`HFBRegOffset:LongWord;`
`RXDMAOffset:LongWord;`
`TXDMAOffset:LongWord;`
`WordsPerDescriptor:LongWord;`
`Flags:LongWord;`
`Q16TXDescriptorCount:LongWord;`
`Q16RXDescriptorCount:LongWord;`
DMA Parameters (Version specific)
`DMARXCheckBit:LongWord;`
`RXDMARegOffset:LongWord;`
`TXDMARegOffset:LongWord;`
`DMADescriptorSize:LongWord;`
`DMARegisters:TGENETDMARegisters;`
`DMARingRegisters:TGENETDMARingRegisters;`
PHY Parameters
`PhyId:LongWord;`	PHY Identifier
`PhyAddr:LongWord;`	PHY Bus Address
`PhyMode:LongWord;`	PHY Interface Mode
`PhyFlags:LongWord;`	PHY Flags
`PhyInternal:LongBool;`
`PhyExternal:LongBool;`
`Link:LongInt;`	0 = Down / 1 = Up
`Speed:LongInt;`	10/100/1000 Mbps
`Duplex:LongInt;`	0 = Half / 1 = Full
`Pause:LongInt;`
`OldLink:LongInt;`
`OldSpeed:LongInt;`
`OldDuplex:LongInt;`
`OldPause:LongInt;`
RX/TX Parameters
`RXRings:TGENETRXRings;`
`TXRings:TGENETTXRings;`
`RXControlBlocks:PGENETControlBlocks;`
`TXControlBlocks:PGENETControlBlocks;`
Statistics Properties
`InterruptCount:LongWord;`	Number of interrupt requests received by the device

GENET RX/TX control block

[Expand]

PGENETControlBlock = ^TGENETControlBlock;

TGENETControlBlock = record

GENET control blocks

[Expand]

PGENETControlBlocks = ^TGENETControlBlocks;

TGENETControlBlocks = array[0..GENET_TOTAL_DESC - 1] of TGENETControlBlock;

GENET RX ring int enable

`TGENETRXRingIntEnable = procedure(Network:PGENETNetwork; Ring:PGENETRXRing);`

GENET RX ring int disable

`TGENETRXRingIntDisable = procedure(Network:PGENETNetwork; Ring:PGENETRXRing);`

GENET RX ring buffer

[Expand]

PGENETRXRing = ^TGENETRXRing;

TGENETRXRing = record

GENET RX rings buffer

[Expand]

PGENETRXRings = ^TGENETRXRings;

TGENETRXRings = array[0..GENET_DESC_INDEX] of TGENETRXRing;

GENET TX ring int enable

`TGENETTXRingIntEnable = procedure(Network:PGENETNetwork;Ring:PGENETTXRing);`

GENET TX ring int disable

`TGENETTXRingIntDisable = procedure(Network:PGENETNetwork;Ring:PGENETTXRing);`

GENET TX ring buffer

[Expand]

PGENETTXRing = ^TGENETTXRing;

TGENETTXRing = record

GENET TX rings buffer

[Expand]

PGENETTXRings = ^TGENETTXRings;

TGENETTXRings = array[0..GENET_DESC_INDEX] of TGENETTXRing;

GENET RX/TX DMA registers

[Expand]

PGENETDMARegisters = ^TGENETDMARegisters;

TGENETDMARegisters = array[DMA_RING_CFG..DMA_RING16_TIMEOUT] of Byte;

GENET RX/TX DMA ring registers

[Expand]

PGENETDMARingRegisters = ^TGENETDMARingRegisters;

TGENETDMARingRegisters = array[TDMA_READ_PTR..TDMA_WRITE_PTR_HI] of Byte;

GENET status 64

[Expand]

PGENETStatus64 = ^TGENETStatus64;

TGENETStatus64 = record

Public variables

GENET specific variables

`GENET_PHY_MODE:String;`

`GENET_PHY_ADDR:LongWord;`

`GENET_SKIP_UMAC_RESET:Boolean;`

`GENET_NO_PHY_INTERRUPT:Boolean;`

Function declarations

GENET functions

[Expand]

function GENETNetworkCreate(Address:PtrUInt; MDIOOffset:LongWord; IRQ0,IRQ1:LongWord):PNetworkDevice;

Description: Create and register a new GENET Network device which can be accessed using the Network API

[Expand]

function GENETNetworkDestroy(Network:PNetworkDevice):LongWord;

Description: Close, deregister and destroy a GENET Network device created by this driver

GENET network functions

[Expand]

function GENETNetworkOpen(Network:PNetworkDevice):LongWord;

Description: Implementation of NetworkDeviceOpen API for GENET Network

[Expand]

function GENETNetworkClose(Network:PNetworkDevice):LongWord;

Description: Implementation of NetworkDeviceClose API for GENET Network

[Expand]

function GENETNetworkControl(Network:PNetworkDevice; Request:Integer; Argument1:PtrUInt; var Argument2:PtrUInt):LongWord;

Description: Implementation of NetworkDeviceControl API for GENET Network

[Expand]

function GENETBufferAllocate(Network:PNetworkDevice; var Entry:PNetworkEntry):LongWord;

Description: Implementation of NetworkBufferAllocate API for GENET Network

[Expand]

function GENETBufferRelease(Network:PNetworkDevice; Entry:PNetworkEntry):LongWord;

Description: Implementation of NetworkBufferRelease API for GENET Network

[Expand]

function GENETBufferReceive(Network:PNetworkDevice; var Entry:PNetworkEntry):LongWord;

Description: Implementation of NetworkBufferReceive API for GENET Network

[Expand]

function GENETBufferTransmit(Network:PNetworkDevice; Entry:PNetworkEntry):LongWord;

Description: Implementation of NetworkBufferTransmit API for GENET Network

GENET helper functions

[Expand]

function GENETGetHardwareParameters(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETGetMACAddress(Network:PGENETNetwork; Address:PHardwareAddress):LongWord;

Description: Get the current MAC address from a GENET Network device

[Expand]

function GENETSetMACAddress(Network:PGENETNetwork; Address:PHardwareAddress):LongWord;

Description: Set the current MAC address for a GENET Network device

[Expand]

procedure GENETPowerUp(Network:PGENETNetwork; Mode:LongWord);

Description: To be documented

[Expand]

function GENETPowerDown(Network:PGENETNetwork; Mode:LongWord):LongWord;

Description: Power down the unimac, based on mode

[Expand]

procedure GENETResetUMAC(Network:PGENETNetwork);

Description: To be documented

[Expand]

procedure GENETUMACReset(Network:PGENETNetwork);

Description: To be documented

[Expand]

procedure GENETInitUMAC(Network:PGENETNetwork);

Description: To be documented

[Expand]

function GENETInitializeDMA(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETFinalizeDMA(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETShutdownDMA(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETDisableDMA(Network:PGENETNetwork; FlushRX:Boolean):LongWord;

Description: Returns a reusable DMA control register value

[Expand]

procedure GENETEnableDMA(Network:PGENETNetwork; DMAControl:LongWord);

Description: To be documented

[Expand]

function GENETInitRXQueues(Network:PGENETNetwork):LongWord;

Description: Initialize RX queues

[Expand]

procedure GENETInitTXQueues(Network:PGENETNetwork);

Description: Initialize TX queues

[Expand]

function GENETInitRXRing(Network:PGENETNetwork; Index,Size,First,Last:LongWord):LongWord;

Description: Initialize an RX DMA ring

[Expand]

procedure GENETInitTXRing(Network:PGENETNetwork; Index,Size,First,Last:LongWord);

Description: Initialize a TX DMA ring along with corresponding hardware registers

[Expand]

function GENETAllocRXBuffers(Network:PGENETNetwork; Ring:PGENETRXRing):LongWord;

Description: Assign buffer to RX DMA descriptor

[Expand]

procedure GENETFreeRXBuffers(Network:PGENETNetwork);

Description: To be documented

[Expand]

procedure GENETHFBInit(Network:PGENETNetwork);

Description: To be documented

[Expand]

procedure GENETHFBClear(Network:PGENETNetwork);

Description: Clear Hardware Filter Block and disable all filtering

[Expand]

procedure GENETInterfaceStart(Network:PGENETNetwork);

Description: To be documented

[Expand]

procedure GENETInterfaceStop(Network:PGENETNetwork);

Description: To be documented

[Expand]

function GENETMIIProbe(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

procedure GENETMIISetup(Network:PGENETNetwork);

Description: Setup netdev link state when PHY link status change and update UMAC and RGMII block when link up

[Expand]

function GENETMIIConfig(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETMIIWait(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function GENETPhyReadStatus(Network:PGENETNetwork):LongWord;

Description: Check the link status and update current link state

UniMAC helper functions

[Expand]

procedure UniMACMDIOStart(Network:PGENETNetwork);

Description: To be documented

[Expand]

function UniMACMDIOBusy(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function UniMACMDIOPoll(Network:PGENETNetwork):LongWord;

Description: To be documented

[Expand]

function UniMACMDIORead(Network:PGENETNetwork; Reg:LongWord; var Value:Word):LongWord;

Description: To be documented

[Expand]

function UniMACMDIOWrite(Network:PGENETNetwork; Reg:LongWord; Value:Word):LongWord;

Description: To be documented

[Expand]

function UniMACMDIOReset(Network:PGENETNetwork):LongWord;

Description: To be documented

Return to Unit Reference

Broadcom Gigabit Ethernet controller

`GENET_NETWORK_DESCRIPTION = 'Broadcom GENET (Gigabit Ethernet) controller';`	Description of GENET device

`GENET_MAX_TX_ENTRIES = SIZE_256;`	Number of Transmit buffers allocated
`GENET_MAX_RX_ENTRIES = SIZE_512;`	Number of Receive buffers allocated

`GENET_MAX_PACKET_SIZE = 2048;`

`GENET_V1 = 1;`	Version information
`GENET_V2 = 2;`	Version information
`GENET_V3 = 3;`	Version information
`GENET_V4 = 4;`	Version information
`GENET_V5 = 5;`	Version information

`GENET_TOTAL_DESC = 256`	Total number of Buffer Descriptors, same for RX/TX

`GENET_DESC_INDEX = 16;`	Max number of descriptor queues (plus 1 for default)

`GENET_ETH_BRCM_TAG_LEN = 6;`
`GENET_ETH_PAD = 8;`
`GENET_ETH_MAX_MTU_SIZE = (ETHERNET_MTU + ETHERNET_HEADER_SIZE + ETHERNET_VLAN_SIZE + GENET_ETH_BRCM_TAG_LEN + ETHERNET_CRC_SIZE + GENET_ETH_PAD);`

`GENET_Q0_PRIORITY = 0;`	Default highest priority queue for multi queue support

`CLEAR_ALL_HFB = $FF;`	Misc configuration

`STATUS_RX_EXT_MASK = $1FFFFF;`
`STATUS_RX_CSUM_MASK = $FFFF;`
`STATUS_RX_CSUM_OK = $10000;`
`STATUS_RX_CSUM_FR = $20000;`
`STATUS_RX_PROTO_TCP = 0;`
`STATUS_RX_PROTO_UDP = 1;`
`STATUS_RX_PROTO_ICMP = 2;`
`STATUS_RX_PROTO_OTHER = 3;`
`STATUS_RX_PROTO_MASK = 3;`
`STATUS_RX_PROTO_SHIFT = 18;`
`STATUS_FILTER_INDEX_MASK = $FFFF;`

`STATUS_TX_CSUM_START_MASK = $7FFF;`
`STATUS_TX_CSUM_START_SHIFT = 16;`
`STATUS_TX_CSUM_PROTO_UDP = $8000;`
`STATUS_TX_CSUM_OFFSET_MASK = $7FFF;`
`STATUS_TX_CSUM_LV = $80000000;`

`DMA_DESC_LENGTH_STATUS = $00;`	In bytes of data in buffer
`DMA_DESC_ADDRESS_LO = $04;`	Lower bits of PA
`DMA_DESC_ADDRESS_HI = $08;`	Upper 32 bits of PA, GENETv4+

`RBUF_CTRL = $00;`
`RBUF_64B_EN = (1 shl 0);`
`RBUF_ALIGN_2B = (1 shl 1);`
`RBUF_BAD_DIS = (1 shl 2);`

`RBUF_STATUS = $0C;`
`RBUF_STATUS_WOL = (1 shl 0);`
`RBUF_STATUS_MPD_INTR_ACTIVE = (1 shl 1);`
`RBUF_STATUS_ACPI_INTR_ACTIVE = (1 shl 2);`

`RBUF_CHK_CTRL = $14;`
`RBUF_RXCHK_EN = (1 shl 0);`
`RBUF_SKIP_FCS = (1 shl 4);`

`RBUF_ENERGY_CTRL = $9c;`
`RBUF_EEE_EN = (1 shl 0);`
`RBUF_PM_EN = (1 shl 1);`

`RBUF_TBUF_SIZE_CTRL = $b4;`

Difference between revisions of "Unit GENET"

Latest revision as of 06:27, 3 August 2022

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Type definitions

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Function declarations

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@@ Line 5: / Line 5: @@
 ----
-'''Broadcom GENET Gigabit Ethernet Driver'''
+'''Broadcom GENET Gigabit Ethernet Driver unit'''
 This driver supports members of the Broadcom family of Gigabit Ethernet devices including the BCM54213PE contained in the Raspberry Pi 4B.
@@ Line 611: / Line 611: @@
 <br />
 <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
-<div style="font-size: 14px; padding-left: 12px;">'''UniMAC intrl2 registers''' <code> INTRL2_CPU_* </code></div>
+<div style="font-size: 14px; padding-left: 12px;">'''UniMAC INTRL2 registers''' <code> INTRL2_CPU_* </code></div>
 <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 {| class="wikitable" style="font-size: 14px; background: white;"
@@ Line 1,231: / Line 1,231: @@
 | <code>DMA_RX_FI_SHIFT = $0007;</code>
 | &nbsp;
-|-DMA_DESC_ALLOC_MASK = $00FF;
+|-
-| <code>NAME_</code>
+| <code>DMA_DESC_ALLOC_MASK = $00FF;</code>
 | &nbsp;
 |-
@@ Line 2,158: / Line 2,158: @@
 ----
-''To be documented''
+'''GENET network'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETNetwork = ^TGENETNetwork;</code>
+<code>TGENETNetwork = record</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''Network Properties''
+|-
+| <code>Network:TNetworkDevice;</code>
+| style="width: 50%;"|&nbsp;
+|-
+|colspan="2"|''Driver Properties''
+|-
+| <code>IRQ0:LongWord;</code>
+| &nbsp;
+|-
+| <code>IRQ1:LongWord;</code>
+| &nbsp;
+|-
+| <code>Address:Pointer;</code>
+| Device register base address
+|-
+| <code>MDIOOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>Lock:TSpinHandle;</code>
+| Device lock (Differs from lock in Network device) (Spin lock due to use by interrupt handler)
+|-
+| <code>Version:LongWord;</code>
+| Device version (GENET_V1..GENETV5)
+|-
+| <code>PhyRevision:LongWord;</code>
+| PHY revision (GENET_V1..GENETV4 devices only)
+|-
+| <code>Status64Enable:LongBool;</code>
+| True if 64 byte RX/TX status block is enabled (for hardware checksum etc)
+|-
+| <code>RXChecksumEnable:LongBool;</code>
+| True if RX checksum is enabled
+|-
+| <code>CRCForwardEnable:LongBool;</code>
+| True if CRC forwarding is enabled
+|-
+| <code>IRQStatus:LongWord;</code>
+| Non TX/RX interrupts forwarded to worker thread for servicing
+|-
+| <code>PendingCount:LongWord;</code>
+| Number of worker requests pending for this network
+|-
+| <code>WaiterThread:TThreadId;</code>
+| Thread waiting for pending requests to complete (for network close)
+|-
+| <code>StatusTimer:TTimerHandle;</code>
+| Timer for status change detection
+|-
+|colspan="2"|Hardware Parameters (Version specific)
+|-
+| <code>TXQueues:LongWord;</code>
+| &nbsp;
+|-
+| <code>TXDescriptorsPerQueue:LongWord;</code>
+| &nbsp;
+|-
+| <code>RXQueues:LongWord;</code>
+| &nbsp;
+|-
+| <code>RXDescriptorsPerQueue:LongWord;</code>
+| &nbsp;
+|-
+| <code>BackPressureEnableShift:LongWord;</code>
+| &nbsp;
+|-
+| <code>BackPressureMask:LongWord;</code>
+| &nbsp;
+|-
+| <code>HFBFilterCount:LongWord;</code>
+| &nbsp;
+|-
+| <code>HFBFilterSize:LongWord;</code>
+| &nbsp;
+|-
+| <code>QTAGMask:LongWord;</code>
+| &nbsp;
+|-
+| <code>TXBufferOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>HFBOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>HFBRegOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>RXDMAOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>TXDMAOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>WordsPerDescriptor:LongWord;</code>
+| &nbsp;
+|-
+| <code>Flags:LongWord;</code>
+| &nbsp;
+|-
+| <code>Q16TXDescriptorCount:LongWord;</code>
+| &nbsp;
+|-
+| <code>Q16RXDescriptorCount:LongWord;</code>
+| &nbsp;
+|-
+|colspan="2"|DMA Parameters (Version specific)
+|-
+| <code>DMARXCheckBit:LongWord;</code>
+| &nbsp;
+|-
+| <code>RXDMARegOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>TXDMARegOffset:LongWord;</code>
+| &nbsp;
+|-
+| <code>DMADescriptorSize:LongWord;</code>
+| &nbsp;
+|-
+| <code>DMARegisters:TGENETDMARegisters;</code>
+| &nbsp;
+|-
+| <code>DMARingRegisters:TGENETDMARingRegisters;</code>
+| &nbsp;
+|-
+|colspan="2"|PHY Parameters
+|-
+| <code>PhyId:LongWord;</code>
+| PHY Identifier
+|-
+| <code>PhyAddr:LongWord;</code>
+| PHY Bus Address
+|-
+| <code>PhyMode:LongWord;</code>
+| PHY Interface Mode
+|-
+| <code>PhyFlags:LongWord;</code>
+| PHY Flags
+|-
+| <code>PhyInternal:LongBool;</code>
+| &nbsp;
+|-
+| <code>PhyExternal:LongBool;</code>
+| &nbsp;
+|-
+| <code>Link:LongInt;</code>
+| 0 = Down / 1 = Up
+|-
+| <code>Speed:LongInt;</code>
+| 10/100/1000 Mbps
+|-
+| <code>Duplex:LongInt;</code>
+| 0 = Half / 1 = Full
+|-
+| <code>Pause:LongInt;</code>
+| &nbsp;
+|-
+| <code>OldLink:LongInt;</code>
+| &nbsp;
+|-
+| <code>OldSpeed:LongInt;</code>
+| &nbsp;
+|-
+| <code>OldDuplex:LongInt;</code>
+| &nbsp;
+|-
+| <code>OldPause:LongInt;</code>
+| &nbsp;
+|-
+|colspan="2"|RX/TX Parameters
+|-
+| <code>RXRings:TGENETRXRings;</code>
+| &nbsp;
+|-
+| <code>TXRings:TGENETTXRings;</code>
+| &nbsp;
+|-
+| <code>RXControlBlocks:PGENETControlBlocks;</code>
+| &nbsp;
+|-
+| <code>TXControlBlocks:PGENETControlBlocks;</code>
+| &nbsp;
+|-
+|colspan="2"|''Statistics Properties''
+|-
+| <code>InterruptCount:LongWord;</code>
+| Number of interrupt requests received by the device
+|-
+|}
+</div></div>
+'''GENET RX/TX control block'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETControlBlock = ^TGENETControlBlock;</code>
+<code>TGENETControlBlock = record</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''RX/TX Control Block''
+|-
+| <code>DescriptorAddress:PtrUInt;</code>
+| style="width: 50%;"|&nbsp;
+|-
+| <code>Entry:PNetworkEntry;</code>
+| &nbsp;
+|-
+|}
+</div></div>
+'''GENET control blocks'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETControlBlocks = ^TGENETControlBlocks;</code>
+<code>TGENETControlBlocks = array[0..GENET_TOTAL_DESC - 1] of TGENETControlBlock;</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+| &nbsp;
+| style="width: 50%;"|&nbsp;
+|-
+|}
+</div></div>
+'''GENET RX ring int enable'''
+{| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;"
+|-
+| <code>TGENETRXRingIntEnable = procedure(Network:PGENETNetwork; Ring:PGENETRXRing);</code>
+| style="width: 40%;"|
+|-
+|}
+'''GENET RX ring int disable'''
+{| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;"
+|-
+| <code>TGENETRXRingIntDisable = procedure(Network:PGENETNetwork; Ring:PGENETRXRing);</code>
+| style="width: 40%;"|
+|-
+|}
+'''GENET RX ring buffer'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETRXRing = ^TGENETRXRing;</code>
+<code>TGENETRXRing = record</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''RX Ring Buffer''
+|-
+| <code>Network:PGENETNetwork;</code>
+| style="width: 50%;"|The owner of this RX ring
+|-
+| <code>Worker:TWorkerHandle;</code>
+| Handle of worker currently servicing RX ring
+|-
+| <code>Index:LongWord;</code>
+| RX ring index
+|-
+| <code>Size:LongWord;</code>
+| RX ring size
+|-
+| <code>Consumer:LongWord;</code>
+| RX last consumer index
+|-
+| <code>Read:LongWord;</code>
+| RX ring read pointer
+|-
+| <code>First:LongWord;</code>
+| RX ring initial CB ptr
+|-
+| <code>Last:LongWord;</code>
+| RX ring end CB ptr
+|-
+| <code>OldDiscards:LongWord;</code>
+| &nbsp;
+|-
+| <code>ControlBlocks:PGENETControlBlocks;</code>
+| RX ring buffer control block
+|-
+| <code>IntEnable:TGENETRXRingIntEnable;</code>
+| &nbsp;
+|-
+| <code>IntDisable:TGENETRXRingIntDisable;</code>
+| &nbsp;
+|-
+|}
+</div></div>
+'''GENET RX rings buffer'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETRXRings = ^TGENETRXRings;</code>
+<code>TGENETRXRings = array[0..GENET_DESC_INDEX] of TGENETRXRing;</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+| &nbsp;
+| style="width: 50%;"|&nbsp;
+|-
+|}
+</div></div>
+'''GENET TX ring int enable'''
+{| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;"
+|-
+| <code>TGENETTXRingIntEnable = procedure(Network:PGENETNetwork;Ring:PGENETTXRing);</code>
+| style="width: 40%;"|
+|-
+|}
+'''GENET TX ring int disable'''
+{| class="wikitable" style="font-size: 14px; text-align: left; width: 100%; height: 50px;"
+|-
+| <code>TGENETTXRingIntDisable = procedure(Network:PGENETNetwork;Ring:PGENETTXRing);</code>
+| style="width: 40%;"|
+|-
+|}
+'''GENET TX ring buffer'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETTXRing = ^TGENETTXRing;</code>
+<code>TGENETTXRing = record</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''TX Ring Buffer''
+|-
+| <code>Network:PGENETNetwork;</code>
+| style="width: 50%;"|The owner of this TX ring
+|-
+| <code>Worker:TWorkerHandle;</code>
+| Handle of worker currently servicing TX ring
+|-
+| <code>Index:LongWord;</code>
+| TX ring index
+|-
+| <code>Queue:LongWord;</code>
+| TX queue index
+|-
+| <code>Size:LongWord;</code>
+| TX ring size
+|-
+| <code>Clean:LongWord;</code>
+| TX ring clean pointer
+|-
+| <code>Consumer:LongWord;</code>
+| TX last consumer index
+|-
+| <code>Free:LongWord;</code>
+| TX number of free descriptors
+|-
+| <code>Write:LongWord;</code>
+| TX ring write pointer SW copy
+|-
+| <code>Producer:LongWord;</code>
+| TX ring producer index SW copy
+|-
+| <code>First:LongWord;</code>
+| TX ring initial CB ptr
+|-
+| <code>Last:LongWord;</code>
+| TX ring end CB ptr
+|-
+| <code>ControlBlocks:PGENETControlBlocks;</code>
+| TX ring buffer control block
+|-
+| <code>IntEnable:TGENETTXRingIntEnable;</code>
+| &nbsp;
+|-
+| <code>IntDisable:TGENETTXRingIntDisable;</code>
+| &nbsp;
+|-
+|}
+</div></div>
+'''GENET TX rings buffer'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETTXRings = ^TGENETTXRings;</code>
+<code>TGENETTXRings = array[0..GENET_DESC_INDEX] of TGENETTXRing;</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+| &nbsp;
+| style="width: 50%;"|&nbsp;
+|-
+|}
+</div></div>
+'''GENET RX/TX DMA registers'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETDMARegisters = ^TGENETDMARegisters;</code>
+<code>TGENETDMARegisters = array[DMA_RING_CFG..DMA_RING16_TIMEOUT] of Byte;</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''RX/TX DMA registers''
+|-
+| &nbsp;
+| style="width: 50%;"|&nbsp;
+|-
+|}
+</div></div>
+'''GENET RX/TX DMA ring registers'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETDMARingRegisters = ^TGENETDMARingRegisters;</code>
+<code>TGENETDMARingRegisters = array[TDMA_READ_PTR..TDMA_WRITE_PTR_HI] of Byte;</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+|colspan="2"|''RX/TX DMA ring registers''
+|-
+| &nbsp;
+| style="width: 50%;"|&nbsp;
+|-
+|}
+</div></div>
+'''GENET status 64'''
+<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;">
+<code>PGENETStatus64 = ^TGENETStatus64;</code>
+<code>TGENETStatus64 = record</code>
+<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
+{| class="wikitable" style="font-size: 14px; background: white;"
+|-
+| <code>LengthStatus:LongWord;</code>
+| style="width: 50%;"|Length and peripheral status
+|-
+| <code>ExtendedStatus:LongWord;</code>
+| Extended status
+|-
+| <code>RXChecksum:LongWord;</code>
+| Partial RX checksum
+|-
+| <code>Unused1:array[0..8] of LongWord;</code>
+| Unused
+|-
+| <code>TXCheckusmInfo:LongWord;</code>
+| TX checksum info
+|-
+| <code>Unused2:array[0..2] of LongWord;</code>
+| Unused
+|-
+|}
+</div></div>
+<br />
 === Public variables ===

`DMA_MAX_BURST_LENGTH = $08;`
`DMA_FC_THRESH_HI = (GENET_TOTAL_DESC shr 4);`
`DMA_FC_THRESH_LO = 5;`

`RBUF_HFB_CTRL_V1 = $38;`
`RBUF_HFB_FILTER_EN_SHIFT = 16;`
`RBUF_HFB_FILTER_EN_MASK = $ffff0000;`
`RBUF_HFB_EN = (1 shl 0);`
`RBUF_HFB_256B = (1 shl 1);`
`RBUF_ACPI_EN = (1 shl 2);`

`RBUF_HFB_LEN_V1 = $3C;`
`RBUF_FLTR_LEN_MASK = $FF;`
`RBUF_FLTR_LEN_SHIFT = 8;`

`TBUF_CTRL = $00;`
`TBUF_BP_MC = $0C;`
`TBUF_ENERGY_CTRL = $14;`
`TBUF_EEE_EN = (1 shl 0);`
`TBUF_PM_EN = (1 shl 1);`

`TBUF_CTRL_V1 = $80;`
`TBUF_BP_MC_V1 = $A0;`

`HFB_CTRL = $00;`
`HFB_FLT_ENABLE_V3PLUS = $04;`
`HFB_FLT_LEN_V2 = $04;`
`HFB_FLT_LEN_V3PLUS = $1C;`

`INTRL2_CPU_STAT = $00;`
`INTRL2_CPU_SET = $04;`
`INTRL2_CPU_CLEAR = $08;`
`INTRL2_CPU_MASK_STATUS = $0C;`
`INTRL2_CPU_MASK_SET = $10;`
`INTRL2_CPU_MASK_CLEAR = $14;`

`UMAC_IRQ0_SCB = (1 shl 0);`
`UMAC_IRQ0_EPHY = (1 shl 1);`
`UMAC_IRQ0_PHY_DET_R = (1 shl 2);`
`UMAC_IRQ0_PHY_DET_F = (1 shl 3);`
`UMAC_IRQ0_LINK_UP = (1 shl 4);`
`UMAC_IRQ0_LINK_DOWN = (1 shl 5);`
`UMAC_IRQ0_LINK_EVENT = (UMAC_IRQ0_LINK_UP or UMAC_IRQ0_LINK_DOWN);`
`UMAC_IRQ0_UMAC = (1 shl 6);`
`UMAC_IRQ0_UMAC_TSV = (1 shl 7);`
`UMAC_IRQ0_TBUF_UNDERRUN = (1 shl 8);`
`UMAC_IRQ0_RBUF_OVERFLOW = (1 shl 9);`
`UMAC_IRQ0_HFB_SM = (1 shl 10);`
`UMAC_IRQ0_HFB_MM = (1 shl 11);`
`UMAC_IRQ0_MPD_R = (1 shl 12);`
`UMAC_IRQ0_RXDMA_MBDONE = (1 shl 13);`
`UMAC_IRQ0_RXDMA_PDONE = (1 shl 14);`
`UMAC_IRQ0_RXDMA_BDONE = (1 shl 15);`
`UMAC_IRQ0_RXDMA_DONE = UMAC_IRQ0_RXDMA_MBDONE;`
`UMAC_IRQ0_TXDMA_MBDONE = (1 shl 16);`
`UMAC_IRQ0_TXDMA_PDONE = (1 shl 17);`
`UMAC_IRQ0_TXDMA_BDONE = (1 shl 18);`
`UMAC_IRQ0_TXDMA_DONE = UMAC_IRQ0_TXDMA_MBDONE;`
Only valid for GENETv3+
`UMAC_IRQ0_MDIO_DONE = (1 shl 23);`
`UMAC_IRQ0_MDIO_ERROR = (1 shl 24);`

`UMAC_IRQ1_TX_INTR_MASK = $FFFF;`
`UMAC_IRQ1_RX_INTR_MASK = $FFFF;`
`UMAC_IRQ1_RX_INTR_SHIFT = 16;`

`GENET_SYS_OFF = $0000;`
`GENET_GR_BRIDGE_OFF = $0040;`
`GENET_EXT_OFF = $0080;`
`GENET_INTRL2_0_OFF = $0200;`
`GENET_INTRL2_1_OFF = $0240;`
`GENET_RBUF_OFF = $0300;`
`GENET_UMAC_OFF = $0800;`

`SYS_REV_CTRL = $00;`
`SYS_PORT_CTRL = $04;`
`PORT_MODE_INT_EPHY = 0;`
`PORT_MODE_INT_GPHY = 1;`
`PORT_MODE_EXT_EPHY = 2;`
`PORT_MODE_EXT_GPHY = 3;`
`PORT_MODE_EXT_RVMII_25 = (4 or (1 shl 4));`
`PORT_MODE_EXT_RVMII_50 = 4;`
`LED_ACT_SOURCE_MAC = (1 shl 9);`

`SYS_RBUF_FLUSH_CTRL = $08;`
`SYS_TBUF_FLUSH_CTRL = $0C;`
`RBUF_FLUSH_CTRL_V1 = $04;`

`DMA_RING_SIZE = $40;`
`DMA_RINGS_SIZE = (DMA_RING_SIZE * (GENET_DESC_INDEX + 1));`

`DMA_RW_POINTER_MASK = $1FF;`
`DMA_P_INDEX_DISCARD_CNT_MASK = $FFFF;`
`DMA_P_INDEX_DISCARD_CNT_SHIFT = 16;`
`DMA_BUFFER_DONE_CNT_MASK = $FFFF;`
`DMA_BUFFER_DONE_CNT_SHIFT = 16;`
`DMA_P_INDEX_MASK = $FFFF;`
`DMA_C_INDEX_MASK = $FFFF;`

`DMA_RING_SIZE_MASK = $FFFF;`
`DMA_RING_SIZE_SHIFT = 16;`
`DMA_RING_BUFFER_SIZE_MASK = $FFFF;`

`DMA_XON_THREHOLD_MASK = $FFFF;`
`DMA_XOFF_THRESHOLD_MASK = $FFFF;`
`DMA_XOFF_THRESHOLD_SHIFT = 16;`

`EXT_EXT_PWR_MGMT = $00;`
`EXT_PWR_DOWN_BIAS = (1 shl 0);`
`EXT_PWR_DOWN_DLL = (1 shl 1);`
`EXT_PWR_DOWN_PHY = (1 shl 2);`
`EXT_PWR_DN_EN_LD = (1 shl 3);`
`EXT_ENERGY_DET = (1 shl 4);`
`EXT_IDDQ_FROM_PHY = (1 shl 5);`
`EXT_IDDQ_GLBL_PWR = (1 shl 7);`
`EXT_PHY_RESET = (1 shl 8);`
`EXT_ENERGY_DET_MASK = (1 shl 12);`
`EXT_PWR_DOWN_PHY_TX = (1 shl 16);`
`EXT_PWR_DOWN_PHY_RX = (1 shl 17);`
`EXT_PWR_DOWN_PHY_SD = (1 shl 18);`
`EXT_PWR_DOWN_PHY_RD = (1 shl 19);`
`EXT_PWR_DOWN_PHY_EN = (1 shl 20);`

`EXT_RGMII_OOB_CTRL = $0C;`
`RGMII_MODE_EN_V123 = (1 shl 0);`
`RGMII_LINK = (1 shl 4);`
`OOB_DISABLE = (1 shl 5);`
`RGMII_MODE_EN = (1 shl 6);`
`ID_MODE_DIS = (1 shl 16);`

`EXT_GPHY_CTRL = $1C;`
`EXT_CFG_IDDQ_BIAS = (1 shl 0);`
`EXT_CFG_PWR_DOWN = (1 shl 1);`
`EXT_CK25_DIS = (1 shl 4);`
`EXT_GPHY_RESET = (1 shl 5);`

`DMA_FLOW_PERIOD_MASK = $FFFF;`
`DMA_MAX_PKT_SIZE_MASK = $FFFF;`
`DMA_MAX_PKT_SIZE_SHIFT = 16;`

`DMA_EN = (1 shl 0);`
`DMA_RING_BUF_EN_SHIFT = $01;`
`DMA_RING_BUF_EN_MASK = $FFFF;`
`DMA_TSB_SWAP_EN = (1 shl 20);`

`DMA_DISABLED = (1 shl 0);`
`DMA_DESC_RAM_INIT_BUSY = (1 shl 1);`

`DMA_BACKPRESSURE_MASK = $1FFFF;`
`DMA_PFC_ENABLE = (1 shl 31);`

`DMA_LITTLE_ENDIAN_MODE = (1 shl 0);`
`DMA_REGISTER_MODE = (1 shl 1);`

`DMA_TIMEOUT_MASK = $FFFF;`
`DMA_TIMEOUT_VAL = 5000;`	Micro seconds

`DMA_ARBITER_MODE_MASK = $03;`
`DMA_RING_BUF_PRIORITY_MASK = $1F;`
`DMA_RING_BUF_PRIORITY_SHIFT = 5;`
`DMA_RATE_ADJ_MASK = $FF;`

`DMA_BUFLENGTH_MASK = $0fff;`
`DMA_BUFLENGTH_SHIFT = 16;`
`DMA_OWN = $8000;`
`DMA_EOP = $4000;`
`DMA_SOP = $2000;`
`DMA_WRAP = $1000;`

`DMA_TX_UNDERRUN = $0200;`
`DMA_TX_APPEND_CRC = $0040;`
`DMA_TX_OW_CRC = $0020;`
`DMA_TX_DO_CSUM = $0010;`
`DMA_TX_QTAG_SHIFT = 7;`

`DMA_RX_CHK_V3PLUS = $8000;`
`DMA_RX_CHK_V12 = $1000;`
`DMA_RX_BRDCAST = $0040;`
`DMA_RX_MULT = $0020;`
`DMA_RX_LG = $0010;`
`DMA_RX_NO = $0008;`
`DMA_RX_RXER = $0004;`
`DMA_RX_CRC_ERROR = $0002;`
`DMA_RX_OV = $0001;`
`DMA_RX_FI_MASK = $001F;`
`DMA_RX_FI_SHIFT = $0007;`
`DMA_DESC_ALLOC_MASK = $00FF;`

`DMA_ARBITER_RR = $00;`
`DMA_ARBITER_WRR = $01;`
`DMA_ARBITER_SP = $02;`

`GENET_POWER_CABLE_SENSE = 0;`
`GENET_POWER_PASSIVE = 1;`
`GENET_POWER_WOL_MAGIC = 2;`

`GENET_HAS_40BITS = (1 shl 0);`
`GENET_HAS_EXT= (1 shl 1);`
`GENET_HAS_MDIO_INTR = (1 shl 2);`
`GENET_HAS_MOCA_LINK_DET = (1 shl 3);`

`DMA_RING_CFG = 0;`
`DMA_CTRL = 1;`
`DMA_STATUS = 2;`
`DMA_SCB_BURST_SIZE = 3;`
`DMA_ARB_CTRL = 4;`
`DMA_PRIORITY_0 = 5;`
`DMA_PRIORITY_1 = 6;`
`DMA_PRIORITY_2 = 7;`
`DMA_INDEX2RING_0 = 8;`
`DMA_INDEX2RING_1 = 9;`
`DMA_INDEX2RING_2 = 10;`
`DMA_INDEX2RING_3 = 11;`
`DMA_INDEX2RING_4 = 12;`
`DMA_INDEX2RING_5 = 13;`
`DMA_INDEX2RING_6 = 14;`
`DMA_INDEX2RING_7 = 15;`
`DMA_RING0_TIMEOUT = 16;`
`DMA_RING1_TIMEOUT = 17;`
`DMA_RING2_TIMEOUT = 18;`
`DMA_RING3_TIMEOUT = 19;`
`DMA_RING4_TIMEOUT = 20;`
`DMA_RING5_TIMEOUT = 21;`
`DMA_RING6_TIMEOUT = 22;`
`DMA_RING7_TIMEOUT = 23;`
`DMA_RING8_TIMEOUT = 24;`
`DMA_RING9_TIMEOUT = 25;`
`DMA_RING10_TIMEOUT = 26;`
`DMA_RING11_TIMEOUT = 27;`
`DMA_RING12_TIMEOUT = 28;`
`DMA_RING13_TIMEOUT = 29;`
`DMA_RING14_TIMEOUT = 30;`
`DMA_RING15_TIMEOUT = 31;`
`DMA_RING16_TIMEOUT = 32;`

Merge the common fields and just prefix with T/D the registers having different meaning depending on the direction

`TDMA_READ_PTR = 0;`
`RDMA_WRITE_PTR = TDMA_READ_PTR;`
`TDMA_READ_PTR_HI = 1;`
`RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI;`
`TDMA_CONS_INDEX = 2;`
`RDMA_PROD_INDEX = TDMA_CONS_INDEX;`
`TDMA_PROD_INDEX = 3;`
`RDMA_CONS_INDEX = TDMA_PROD_INDEX;`
`DMA_RING_BUF_SIZE = 4;`
`DMA_START_ADDR = 5;`
`DMA_START_ADDR_HI = 6;`
`DMA_END_ADDR = 7;`
`DMA_END_ADDR_HI = 8;`
`DMA_MBUF_DONE_THRESH = 9;`
`TDMA_FLOW_PERIOD = 10;`
`RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD;`
`TDMA_WRITE_PTR = 11;`
`RDMA_READ_PTR = TDMA_WRITE_PTR;`
`TDMA_WRITE_PTR_HI = 12;`
`RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI;`

Broadcom UniMAC MDIO bus controller

`MDIO_CMD = $00;`
See UMAC_MDIO_CMD

`MDIO_START_BUSY = (1 shl 29);`
`MDIO_READ_FAIL = (1 shl 28);`
`MDIO_RD = (2 shl 26);`
`MDIO_WR = (1 shl 26);`
`MDIO_PMD_SHIFT = 21;`
`MDIO_PMD_MASK = $1F;`
`MDIO_REG_SHIFT = 16;`
`MDIO_REG_MASK = $1F;`

`MDIO_CFG = $04;`
`MDIO_C22 = (1 shl 0);`
`MDIO_C45 = 0;`
`MDIO_CLK_DIV_SHIFT = 4;`
`MDIO_CLK_DIV_MASK = $3F;`
`MDIO_SUPP_PREAMBLE = (1 shl 12);`

`PHY_ID_BCM50610 = $0143bd60;`
`PHY_ID_BCM50610M = $0143bd70;`
`PHY_ID_BCM5241 = $0143bc30;`
`PHY_ID_BCMAC131 = $0143bc70;`
`PHY_ID_BCM5481 = $0143bca0;`
`PHY_ID_BCM5395 = $0143bcf0;`
`PHY_ID_BCM54810 = $03625d00;`
`PHY_ID_BCM5482 = $0143bcb0;`
`PHY_ID_BCM5411 = $00206070;`
`PHY_ID_BCM5421 = $002060e0;`
`PHY_ID_BCM54210E = $600d84a0;`
`PHY_ID_BCM5464 = $002060b0;`
`PHY_ID_BCM5461 = $002060c0;`
`PHY_ID_BCM54612E = $03625e60;`
`PHY_ID_BCM54616S = $03625d10;`
`PHY_ID_BCM57780 = $03625d90;`
`PHY_ID_BCM89610 = $03625cd0;`

`PHY_ID_BCM7250 = $ae025280;`
`PHY_ID_BCM7255 = $ae025120;`
`PHY_ID_BCM7260 = $ae025190;`
`PHY_ID_BCM7268 = $ae025090;`
`PHY_ID_BCM7271 = $ae0253b0;`
`PHY_ID_BCM7278 = $ae0251a0;`
`PHY_ID_BCM7364 = $ae025260;`
`PHY_ID_BCM7366 = $600d8490;`
`PHY_ID_BCM7346 = $600d8650;`
`PHY_ID_BCM7362 = $600d84b0;`
`PHY_ID_BCM7425 = $600d86b0;`
`PHY_ID_BCM7429 = $600d8730;`
`PHY_ID_BCM7435 = $600d8750;`
`PHY_ID_BCM74371 = $ae0252e0;`
`PHY_ID_BCM7439 = $600d8480;`
`PHY_ID_BCM7439_2 = $ae025080;`
`PHY_ID_BCM7445 = $600d8510;`

`PHY_ID_BCM_CYGNUS = $ae025200;`
`PHY_ID_BCM_OMEGA = $ae025100;`

`PHY_ID_MASK = $fffffff0;`

`PHY_BCM_FLAGS_MODE_COPPER = $00000001;`
`PHY_BCM_FLAGS_MODE_1000BX = $00000002;`
`PHY_BCM_FLAGS_INTF_SGMII = $00000010;`
`PHY_BCM_FLAGS_INTF_XAUI = $00000020;`
`PHY_BRCM_WIRESPEED_ENABLE = $00000100;`
`PHY_BRCM_AUTO_PWRDWN_ENABLE = $00000200;`
`PHY_BRCM_RX_REFCLK_UNUSED = $00000400;`
`PHY_BRCM_STD_IBND_DISABLE = $00000800;`
`PHY_BRCM_EXT_IBND_RX_ENABLE = $00001000;`
`PHY_BRCM_EXT_IBND_TX_ENABLE = $00002000;`
`PHY_BRCM_CLEAR_RGMII_MODE = $00004000;`
`PHY_BRCM_DIS_TXCRXC_NOENRGY = $00008000;`
`PHY_BRCM_EN_MASTER_MODE = $00010000;`

Common to most Broadcom PHYs

`MII_BCM54XX_ECR = $10;`	BCM54xx extended control register
`MII_BCM54XX_ECR_IM = $1000;`	Interrupt mask
`MII_BCM54XX_ECR_IF = $0800;`	Interrupt force

`MII_BCM54XX_ESR = $11;`	BCM54xx extended status register
`MII_BCM54XX_ESR_IS = $1000;`	Interrupt status

`MII_BCM54XX_EXP_DATA = $15;`	Expansion register data
`MII_BCM54XX_EXP_SEL = $17;`	Expansion register select
`MII_BCM54XX_EXP_SEL_SSD = $0e00;`	Secondary SerDes select
`MII_BCM54XX_EXP_SEL_ER = $0f00;`	Expansion register select
`MII_BCM54XX_EXP_SEL_ETC = $0d00;`	Expansion register spare + 2k mem

`MII_BCM54XX_AUX_CTL = $18;`	Auxiliary control register
`MII_BCM54XX_ISR = $1a;`	BCM54xx interrupt status register
`MII_BCM54XX_IMR = $1b;`	BCM54xx interrupt mask register
`MII_BCM54XX_INT_CRCERR = $0001;`	CRC error
`MII_BCM54XX_INT_LINK = $0002;`	Link status changed
`MII_BCM54XX_INT_SPEED = $0004;`	Link speed change
`MII_BCM54XX_INT_DUPLEX = $0008;`	Duplex mode changed
`MII_BCM54XX_INT_LRS = $0010;`	Local receiver status changed
`MII_BCM54XX_INT_RRS = $0020;`	Remote receiver status changed
`MII_BCM54XX_INT_SSERR = $0040;`	Scrambler synchronization error
`MII_BCM54XX_INT_UHCD = $0080;`	Unsupported HCD negotiated
`MII_BCM54XX_INT_NHCD = $0100;`	No HCD
`MII_BCM54XX_INT_NHCDL = $0200;`	No HCD link
`MII_BCM54XX_INT_ANPR = $0400;`	Auto-negotiation page received
`MII_BCM54XX_INT_LC = $0800;`	All counters below 128
`MII_BCM54XX_INT_HC = $1000;`	Counter above 32768
`MII_BCM54XX_INT_MDIX = $2000;`	MDIX status change
`MII_BCM54XX_INT_PSERR = $4000;`	Pair swap error

`MII_BCM54XX_SHD = $1c;`	0x1c shadow registers
`MII_BCM54XX_SHD_WRITE = $8000;`

PHY REG 0x18

`MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL = $00;`
`MII_BCM54XX_AUXCTL_ACTL_TX_6DB = $0400;`
`MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA = $0800;`

`MII_BCM54XX_AUXCTL_SHDWSEL_MISC = $07;`
`MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN = $0010;`
`MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN = $0100;`
`MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX = $0200;`
`MII_BCM54XX_AUXCTL_MISC_WREN = $8000;`

`MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT = 12;`
`MII_BCM54XX_AUXCTL_SHDWSEL_MASK = $0007;`