Difference between revisions of "Unit BootRPi"
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<div style="font-size: 14px; padding-left: 12px;">'''Description:''' Entry point of Ultibo on Raspberry Pi, this will be the very first byte executed and will be loaded by the GPU at address 0x00008000</div> | <div style="font-size: 14px; padding-left: 12px;">'''Description:''' Entry point of Ultibo on Raspberry Pi, this will be the very first byte executed and will be loaded by the GPU at address 0x00008000</div> | ||
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Latest revision as of 01:19, 22 April 2022
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Description
Ultibo Initialization code for Raspberry Pi unit
Raspberry Pi
SoC: Broadcom BCM2835
CPU: ARM1176 (ARMv6) (1 @ 700MHz)
Cache: L1 16KB/L2 128KB (Shared with GPU)
FPU: VFPV2
GPU: Broadcom VideoCore IV (VC4)
RAM: 512MB (256MB on Model A/A+)
USB: Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go Controller (DWCOTG)
LAN: SMSC LAN9512 (SMSC LAN9514 on Model B+/No LAN on Model A/A+/Zero) (SMSC95XX)
SD/MMC: Arasan (BCM2708)
WiFi: (None)
Bluetooth: (None)
Other: GPIO/SPI/I2C/I2S/PL011 (UART)/PWM/SMI/Watchdog (PM)/Random (RNG)/Timer
Boot RPi
The boot loader on the Raspberry Pi will load this code at address 0x00008000 onwards and set the following registers before jumping to this code.
R0 - Zero
R1 - Machine Type (Raspberry Pi or BCM2708 = 0x0c42)
R2 - Address of the ARM Tags structure (Normally 0x0100)
On entry to this code the processor will be in the following state:
World - Secure
Mode - Supervisor (ARM_MODE_SVC)
MMU - Disabled
FPU - Disabled
L1 Data Cache - Disabled
L1 Instruction Cache - Disabled
Branch Predication - Disabled
Unaligned Data Access - Disabled
Ultibo switches the processor to System mode for all operations and remains in the Secure world.
The initialization process enables the MMU, FPU, L1 Cache and other performance optimizations.
Constants
None defined
Type definitions
None defined
Public variables
None defined
Function declarations
Boot functions
procedure Startup; assembler; nostackframe; public name '_START';
| Note | None documented |
|---|
procedure Vectors; assembler; nostackframe;
| Note | See A2.6 "Exceptions" of the ARM Architecture Reference Manual |
|---|
procedure StartupHandler; assembler; nostackframe;
| Note | None documented |
|---|
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