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| (One intermediate revision by the same user not shown) |
| Line 5: |
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| | ---- | | ---- |
| | | | |
| − | '''ARM Generic Interrupt Controller Driver''' | + | '''ARM Generic Interrupt Controller Driver unit''' |
| | | | |
| | === Constants === | | === Constants === |
| Line 690: |
Line 690: |
| | ---- | | ---- |
| | | | |
| − | ''To be documented'' | + | |
| | + | '''ARM GIC state''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | |
| | + | <code>TGICState = record</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | |colspan="2"|Describes the state of a block of interrupts (32 per record) |
| | + | |- |
| | + | | <code>Enabled:LongWord;</code> |
| | + | | style="width: 50%;"|Bit mask of the enabled interrupts |
| | + | |- |
| | + | | <code>Available:LongWord;</code> |
| | + | | Bit mask of the available interrupts |
| | + | |- |
| | + | | <code>Permanent:LongWord;</code> |
| | + | | Bit mask of the permanently enabled interrupts |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | |
| | + | '''ARM GIC states''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PGICStates = ^TGICStates;</code> |
| | + | |
| | + | <code>TGICStates = array[0..31] of TGICState;</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | | |
| | + | | style="width: 50%;"| |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | |
| | + | '''ARM GIC entries''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PGICEntries = ^TGICEntries;</code> |
| | + | |
| | + | <code>TGICEntries = array[0..1023] of PInterruptEntry;</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | | |
| | + | | style="width: 50%;"| |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | |
| | + | '''ARM GIC arrays''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PGICArrays = ^TGICArrays;</code> |
| | + | |
| | + | <code>TGICArrays = array[0..7] of PGICEntries;</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | | |
| | + | | style="width: 50%;"| |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | |
| | + | '''ARM GIC device''' |
| | + | |
| | + | <div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial;"> |
| | + | <code>PGICDevice = ^TGICDevice;</code> |
| | + | |
| | + | <code>TGICDevice = record</code> |
| | + | <div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;"> |
| | + | {| class="wikitable" style="font-size: 14px; background: white;" |
| | + | |- |
| | + | |colspan="2"|''GIC Properties'' |
| | + | |- |
| | + | | <code>DistAddress:PtrUInt;</code> |
| | + | | style="width: 50%;"| |
| | + | |- |
| | + | | <code>CPUAddress:PtrUInt;</code> |
| | + | | |
| | + | |- |
| | + | | <code>CPUCount:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>IRQCount:LongWord;</code> |
| | + | | |
| | + | |- |
| | + | | <code>SecureMode:LongBool;</code> |
| | + | | |
| | + | |- |
| | + | | <code>FIQAvailable:LongBool;</code> |
| | + | | |
| | + | |- |
| | + | | <code>GICEnabled:LongBool;</code> |
| | + | | |
| | + | |- |
| | + | |colspan="2"|''Interrupt Properties'' |
| | + | |- |
| | + | | <code>Interrupts:PGICEntries;</code> |
| | + | | Array of interrupt entries |
| | + | |- |
| | + | | <code>LocalInterrupts:PGICArrays;</code> |
| | + | | Arrays of local interrupt entries (1 array per CPU) |
| | + | |- |
| | + | | <code>SoftwareInterrupts:PGICArrays;</code> |
| | + | | Arrays of software interrupt entries (1 array per CPU) |
| | + | |- |
| | + | |colspan="2"|''State Properties'' |
| | + | |- |
| | + | | <code>States:PGICStates;</code> |
| | + | | Array of interrupt states |
| | + | |- |
| | + | | <code>LocalStates:PGICStates;</code> |
| | + | | Array of local interrupt states (1 element per CPU) |
| | + | |- |
| | + | | <code>SoftwareStates:PGICStates;</code> |
| | + | | Array of software interrupt states (1 element per CPU) |
| | + | |- |
| | + | |} |
| | + | </div></div> |
| | + | <br /> |
| | | | |
| | === Public variables === | | === Public variables === |
Latest revision as of 05:10, 31 August 2021
Return to Unit Reference
Description
ARM Generic Interrupt Controller Driver unit
Constants
[Expand]
ARM GIC specific constants ARM_GIC_*
ARM_GIC_MAX_DEVICES = 4;
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ARM_GIC_SGI_BASE = 0;
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Software Generated Interrupts from 0 to 15
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ARM_GIC_PPI_BASE = 16;
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Private Peripheral Interrupts from 16 to 31
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ARM_GIC_SPI_BASE = 32;
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Shared Peripheral Interrupts from 32 to 1019 (Maximum)
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ARM_GIC_SPI_MAX = 1019;
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ARM_GIC_SGI_COUNT = 16;
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16 Software Generated Interrupts
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ARM_GIC_PPI_COUNT = 16;
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16 Private Peripheral Interrupts
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ARM_GIC_SPI_COUNT = 988;
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988 Shared Peripheral Interrupts (Maximum)
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ARM_GIC_GROUP1_INTERRUPT = 1022;
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Returned by GICC_IAR when a Group1 interrupt is the highest priority interrupt pending
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ARM_GIC_SPURIOUS_INTERRUPT = 1023;
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Return by GICC_IAR when there is no pending interrupt
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[Expand]
ARM GIC distributor registers ARM_GICD_*
ARM_GICD_CTLR = $000;
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Distributor Control Register
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ARM_GICD_TYPER = $004;
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Interrupt Controller Type Register
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ARM_GICD_IIDR = $008;
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Distributor Implementer Identification Register
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ARM_GICD_IGROUPR0 = $080;
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Interrupt Group Registers
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ARM_GICD_ISENABLER0 = $100;
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Interrupt Set-Enable Registers
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ARM_GICD_ICENABLER0 = $180;
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Interrupt Clear-Enable Registers
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ARM_GICD_ISPENDR0 = $200;
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Interrupt Set-Pending Registers
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ARM_GICD_ICPENDR0 = $280;
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Interrupt Clear-Pending Registers
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ARM_GICD_ISACTIVER0 = $300;
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GICv2 Interrupt Set-Active Registers
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ARM_GICD_ICACTIVER0 = $380;
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Interrupt Clear-Active Registers
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ARM_GICD_IPRIORITYR0 = $400;
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Interrupt Priority Registers
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ARM_GICD_ITARGETSR0 = $800;
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Interrupt Processor Targets Registers
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ARM_GICD_ICFGR0 = $C00;
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Interrupt Configuration Registers
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ARM_GICD_NSACR0 = $E00;
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Non-secure Access Control Registers (Optional)
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ARM_GICD_SGIR = $F00;
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Software Generated Interrupt Register
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ARM_GICD_CPENDSGIR0 = $F10;
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SGI Clear-Pending Registers
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ARM_GICD_SPENDSGIR0 = $F20;
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SGI Set-Pending Registers
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[Expand]
ARM GIC distributor control register ARM_GICD_CTLR_*
| Non secure copy (Also appropriate bits for Secure copy)
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ARM_GICD_CTLR_DISABLE = (0 shl 0);
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ARM_GICD_CTLR_ENABLE = (1 shl 0);
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Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces
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| Secure copy
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ARM_GICD_CTLRS_DISABLE = (0 shl 0);
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ARM_GICD_CTLRS_ENABLE_GROUP1 = (1 shl 1);
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Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces
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ARM_GICD_CTLRS_ENABLE_GROUP0 = (1 shl 0);
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Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces
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[Expand]
ARM GIC interrupt controller type register ARM_GICD_TYPER_*
ARM_GICD_TYPER_LSPI_MASK = ($1F shl 11);
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If the GIC implements the Security Extensions, the value of this field is the maximum number of implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111)
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ARM_GICD_TYPER_SECURITY_EXT = (1 shl 10);
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Indicates whether the GIC implements the Security Extensions
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ARM_GICD_TYPER_CPUNUM_MASK = (7 shl 5);
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Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is one more than the value of this field
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ARM_GICD_TYPER_IRQNUM_MASK = ($1F shl 0);
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Indicates the maximum number of interrupts that the GIC supports. The maximum number of interrupts is 32(N+1)
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ARM_GICD_TYPER_LSPI_SHIFT = 11;
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ARM_GICD_TYPER_SECURITY_SHIFT = 10;
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ARM_GICD_TYPER_CPUNUM_SHIFT = 5;
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ARM_GICD_TYPER_IRQNUM_SHIFT = 0;
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[Expand]
ARM GIC distributor implementer identification register ARM_GICD_IIDR_*
ARM_GICD_IIDR_PRODUCTID_MASK = ($FF shl 24);
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An IMPLEMENTATION DEFINED product identifier
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ARM_GICD_IIDR_VARIANT_MASK = ($F shl 16);
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An IMPLEMENTATION DEFINED variant number
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ARM_GICD_IIDR_REVISION_MASK = ($F shl 12);
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An IMPLEMENTATION DEFINED revision number
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ARM_GICD_IIDR_IMPLEMENTOR_MASK = ($FFF shl 0);
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Contains the JEP106 code of the company that implemented the GIC Distributor
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ARM_GICD_IIDR_PRODUCTID_SHIFT = 24;
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ARM_GICD_IIDR_VARIANT_SHIFT = 16;
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ARM_GICD_IIDR_REVISION_SHIFT = 12;
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ARM_GICD_IIDR_IMPLEMENTOR_SHIFT = 0;
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[Expand]
ARM GIC interrupt priority register ARM_GICD_IPRIORITYR_*
ARM_GICD_IPRIORITYR_MASK = $FF;
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Each byte of the priority register holds a priority value
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[Expand]
ARM GIC interrupt processor targets register ARM_GICD_ITARGETSR_*
ARM_GICD_ITARGETSR_MASK = $FF;
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Each byte of the targets register holds a bit mask of the CPU targets
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[Expand]
ARM GIC interrupt configuration register ARM_GICD_ICFGR_*
ARM_GICD_ICFGR_MASK = $03;
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ARM_GICD_ICFGR_LEVEL_SENSITIVE = (0 shl 1);
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Corresponding interrupt is level-sensitive
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ARM_GICD_ICFGR_EDGE_TRIGGERED = (1 shl 1);
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Corresponding interrupt is edge-triggered
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[Expand]
ARM GIC non-secure access control register (Group 0 Interrupts) ARM_GICD_NSACR_*
ARM_GICD_NSACR_MASK = $03;
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ARM_GICD_NSACR_NONE = $0;
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No Non-secure access is permitted to fields associated with the corresponding interrupt
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ARM_GICD_NSACR_SET = $1;
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Non-secure write access is permitted to fields associated with the corresponding interrupt in the GICD_ISPENDRn registers
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ARM_GICD_NSACR_CLEAR = $2;
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Adds Non-secure write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDRn registers
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ARM_GICD_NSACR_TARGET = $3;
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Adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ITARGETSRn registers
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[Expand]
ARM GIC software generated interrupt register ARM_GICD_SGIR_*
ARM_GICD_SGIR_CPUFILTER_MASK = ($03 shl 24);
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Determines how the distributor must process the requested SGI
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ARM_GICD_SGIR_CPUTARGET_MASK = ($FF shl 16);
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When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the interrupt
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ARM_GICD_SGIR_NSATT = (1 shl 15);
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Specifies the required security value of the SGI
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ARM_GICD_SGIR_INTID_MASK = ($F shl 0);
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The Interrupt ID of the SGI to forward to the specified CPU interfaces
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ARM_GICD_SGIR_CPUFILTER_SHIFT = 24;
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ARM_GICD_SGIR_CPUTARGET_SHIFT = 16;
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ARM_GICD_SGIR_NSATT_SHIFT = 15;
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ARM_GICD_SGIR_INTID_SHIFT = 0;
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ARM_GICD_SGIR_CPUFILTER_LIST = $0;
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Forward the interrupt to the CPU interfaces specified in the CPUTargetList field
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ARM_GICD_SGIR_CPUFILTER_ALL = $1;
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Forward the interrupt to all CPU interfaces except that of the processor that requested the interrupt
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ARM_GICD_SGIR_CPUFILTER_SELF = $2;
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Forward the interrupt only to the CPU interface of the processor that requested the interrupt
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[Expand]
ARM GIC SGI clear-pending registers ARM_GICD_CPENDSGIR_*
ARM_GICD_CPENDSGIR_MASK = $FF;
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[Expand]
ARM GIC SGI set-pending registers ARM_GICD_SPENDSGIR_*
ARM_GICD_SPENDSGIR_MASK = $FF;
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[Expand]
ARM GIC CPU registers ARM_GICC_*
ARM_GICC_CTLR = $0000;
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CPU Interface Control Register
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ARM_GICC_PMR = $0004;
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Interrupt Priority Mask Register
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ARM_GICC_BPR = $0008;
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Binary Point Register
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ARM_GICC_IAR = $000C;
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Interrupt Acknowledge Register
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ARM_GICC_EOIR = $0010;
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End of Interrupt Register
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ARM_GICC_RPR = $0014;
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Running Priority Register
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ARM_GICC_HPPIR = $0018;
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Highest Priority Pending Interrupt Register
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ARM_GICC_ABPR = $001C;
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Aliased Binary Point Register
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ARM_GICC_AIAR = $0020;
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Aliased Interrupt Acknowledge Register
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ARM_GICC_AEOIR = $0024;
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Aliased End of Interrupt Register
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ARM_GICC_AHPPIR = $0028;
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Aliased Highest Priority Pending Interrupt Register
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ARM_GICC_APR0 = $00D0;
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Active Priorities Registers
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ARM_GICC_NSAPR0 = $00E0;
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Non-secure Active Priorities Registers
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ARM_GICC_IIDR = $00FC;
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CPU Interface Identification Register
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ARM_GICC_DIR = $1000;
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Deactivate Interrupt Register
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[Expand]
ARM GIC CPU interface control register ARM_GICC_CTLR_*
| Non secure copy (Also appropriate bits for Secure copy)
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ARM_GICC_CTLR_DISABLE = (0 shl 0);
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ARM_GICC_CTLR_EOI_MODE = (1 shl 9);
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ARM_GICC_CTLR_IRQ_BYPASS = (1 shl 6);
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ARM_GICC_CTLR_FIQ_BYPASS = (1 shl 5);
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ARM_GICC_CTLR_ENABLE = (1 shl 0);
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Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor
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| Secure copy
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ARM_GICC_CTLRS_DISABLE = (0 shl 0);
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ARM_GICC_CTLRS_EOI_MODE_NS = (1 shl 10);
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Alias of EOImodeNS from the Non-secure copy of this register
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ARM_GICC_CTLRS_EOI_MODE = (1 shl 9);
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Controls the behavior of accesses to GICC_EOIR and GICC_DIR register
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ARM_GICC_CTLRS_IRQ_BYPASS_GROUP1 = (1 shl 8);
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Alias of IRQBypDisGrp1 from the Non-secure copy of this register
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ARM_GICC_CTLRS_FIQ_BYPASS_GROUP1 = (1 shl 7);
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Alias of FIQBypDisGrp1 from the Non-secure copy of this register
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ARM_GICC_CTLRS_IRQ_BYPASS_GROUP0 = (1 shl 6);
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When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass IRQ signal is signaled to the processor
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ARM_GICC_CTLRS_FIQ_BYPASS_GROUP0 = (1 shl 5);
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When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass FIQ signal is signaled to the processor
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ARM_GICC_CTLRS_CBPR = (1 shl 4);
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Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts
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ARM_GICC_CTLRS_FIQ_ENABLE = (1 shl 3);
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Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal
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ARM_GICC_CTLRS_ACKCTL = (1 shl 2);
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Controls behaviour when the highest priority pending interrupt is a Group 1 interrupt
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ARM_GICC_CTLRS_ENABLE_GROUP1 = (1 shl 1);
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Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor
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ARM_GICC_CTLRS_ENABLE_GROUP0 = (1 shl 0);
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Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor
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[Expand]
ARM GIC interrupt priority mask register ARM_GICC_PMR_*
ARM_GICC_PMR_PRIORITY = $F0;
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The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor
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[Expand]
ARM GIC binary point register ARM_GICC_BPR_*
ARM_GICC_BPR_BINARYPOINT_MASK = (7 shl 0);
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The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field
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[Expand]
ARM GIC interrupt acknowledge register ARM_GICC_IAR_*
ARM_GICC_IAR_CPUID_MASK = $07;
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For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt
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ARM_GICC_IAR_INTERRUPTID_MASK = $3FF;
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A read of the GICC_IAR returns the interrupt ID of the highest priority pending interrupt for the CPU interface. The read returns a spurious interrupt ID of 1023 if any of the following apply: forwarding of interrupts by the Distributor to the CPU interface is disabled, signaling of interrupts by the CPU interface to the connected processor is disabled orno pending interrupt on the CPU interface has sufficient priority for the interface to signal it to the processor.
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ARM_GICC_IAR_CPUID_SHIFT = 10;
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ARM_GICC_IAR_INTERRUPTID_SHIFT = 0;
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[Expand]
ARM GIC end of interrupt register ARM_GICC_EOIR_*
ARM_GICC_EOIR_CPUID_MASK = $07;
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On a multiprocessor implementation, if the write refers to an SGI, this field contains the CPUID value from the corresponding GICC_IAR access
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ARM_GICC_EOIR_EOIINTID_MASK = $3FF;
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The Interrupt ID value from the corresponding GICC_IAR access
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ARM_GICC_EOIR_CPUID_SHIFT = 10;
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ARM_GICC_EOIR_EOIINTID_SHIFT = 0;
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[Expand]
ARM GIC running priority register ARM_GICC_RPR_*
ARM_GICC_RPR_PRIORITY_MASK = $FF;
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The current running priority on the CPU interface
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[Expand]
ARM GIC highest priority pending interrupt register ARM_GICC_HPPIR_*
ARM_GICC_HPPIR_CPUID_MASK = $07;
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On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt
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ARM_GICC_HPPIR_PENDINTID_MASK = $3FF;
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The interrupt ID of the highest priority pending interrupt
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ARM_GICC_HPPIR_CPUID_SHIFT = 10;
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ARM_GICC_HPPIR_PENDINTID_SHIFT = 0;
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[Expand]
ARM GIC aliased binary point register ARM_GICC_ABPR_*
ARM_GICC_ABPR_BINARYPOINT_MASK = ARM_GICC_BPR_BINARYPOINT_MASK;
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A Binary Point Register for handling Group 1 interrupts
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[Expand]
ARM GIC aliased interrupt acknowledge register ARM_GICC_AIAR_*
ARM_GICC_AIAR_CPUID_MASK = ARM_GICC_IAR_CPUID_MASK;
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An Interrupt Acknowledge register for handling Group 1 interrupts
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ARM_GICC_AIAR_INTERRUPTID_MASK = ARM_GICC_IAR_INTERRUPTID_MASK;
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ARM_GICC_AIAR_CPUID_SHIFT = ARM_GICC_IAR_CPUID_SHIFT;
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ARM_GICC_AIAR_INTERRUPTID_SHIFT = ARM_GICC_IAR_INTERRUPTID_SHIFT;
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[Expand]
ARM GIC aliased end of interrupt register ARM_GICC_AEOIR_*
ARM_GICC_AEOIR_CPUID_MASK = ARM_GICC_EOIR_CPUID_MASK;
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An end of interrupt register for handling Group 1 interrupts
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ARM_GICC_AEOIR_EOIINTID_MASK = ARM_GICC_EOIR_EOIINTID_MASK;
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ARM_GICC_AEOIR_CPUID_SHIFT = ARM_GICC_EOIR_CPUID_SHIFT;
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ARM_GICC_AEOIR_EOIINTID_SHIFT = ARM_GICC_EOIR_EOIINTID_SHIFT;
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[Expand]
ARM GIC aliased highest priority pending interrupt register ARM_GICC_AHPPIR_*
ARM_GICC_AHPPIR_CPUID_MASK = ARM_GICC_HPPIR_CPUID_MASK;
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A Highest Priority Pending Interrupt register for the handling of Group 1 interrupts
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ARM_GICC_AHPPIR_PENDINTID_MASK = ARM_GICC_HPPIR_PENDINTID_MASK;
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ARM_GICC_AHPPIR_CPUID_SHIFT = ARM_GICC_HPPIR_CPUID_SHIFT;
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ARM_GICC_AHPPIR_PENDINTID_SHIFT = ARM_GICC_HPPIR_PENDINTID_SHIFT;
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[Expand]
ARM GIC CPU interface identification register ARM_GICC_IIDR_*
ARM_GICC_IIDR_PRODUCTID_MASK = ($FFF shl 20);
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An IMPLEMENTATION DEFINED product identifier
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ARM_GICC_IIDR_ARCHITECTURE_MASK = ($F shl 16);
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The value of this field depends on the GIC architecture version (0x1 for GICv1 / 0x2 for GICv2)
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ARM_GICC_IIDR_REVISION_MASK = ($F shl 12);
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An IMPLEMENTATION DEFINED revision number for the CPU interface
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ARM_GICC_IIDR_IMPLEMENTOR_MASK = ($FFF shl 0);
|
Contains the JEP106 code of the company that implemented the GIC CPU interface
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ARM_GICC_IIDR_PRODUCTID_SHIFT = 20;
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ARM_GICC_IIDR_ARCHITECTURE_SHIFT = 16;
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ARM_GICC_IIDR_REVISION_SHIFT = 12;
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ARM_GICC_IIDR_IMPLEMENTOR_SHIFT = 0;
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[Expand]
ARM GIC deactivate interrupt register ARM_GICC_DIR_*
ARM_GICC_DIR_CPUID_MASK = $07;
|
For an SGI in a multiprocessor implementation, this field identifies the processor that requested the interrupt
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ARM_GICC_DIR_INTERRUPTID_MASK = $3FF;
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The interrupt ID
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ARM_GICC_DIR_CPUID_SHIFT = 10;
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ARM_GICC_DIR_INTERRUPTID_SHIFT = 0;
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Type definitions
ARM GIC state
[Expand]
TGICState = record
| Describes the state of a block of interrupts (32 per record)
|
Enabled:LongWord;
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Bit mask of the enabled interrupts
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Available:LongWord;
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Bit mask of the available interrupts
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Permanent:LongWord;
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Bit mask of the permanently enabled interrupts
|
ARM GIC states
[Expand]
PGICStates = ^TGICStates;
TGICStates = array[0..31] of TGICState;
ARM GIC entries
[Expand]
PGICEntries = ^TGICEntries;
TGICEntries = array[0..1023] of PInterruptEntry;
ARM GIC arrays
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PGICArrays = ^TGICArrays;
TGICArrays = array[0..7] of PGICEntries;
ARM GIC device
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PGICDevice = ^TGICDevice;
TGICDevice = record
| GIC Properties
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DistAddress:PtrUInt;
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CPUAddress:PtrUInt;
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CPUCount:LongWord;
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IRQCount:LongWord;
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SecureMode:LongBool;
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FIQAvailable:LongBool;
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GICEnabled:LongBool;
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| Interrupt Properties
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Interrupts:PGICEntries;
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Array of interrupt entries
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LocalInterrupts:PGICArrays;
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Arrays of local interrupt entries (1 array per CPU)
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SoftwareInterrupts:PGICArrays;
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Arrays of software interrupt entries (1 array per CPU)
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| State Properties
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States:PGICStates;
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Array of interrupt states
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LocalStates:PGICStates;
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Array of local interrupt states (1 element per CPU)
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SoftwareStates:PGICStates;
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Array of software interrupt states (1 element per CPU)
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Public variables
None defined
Function declarations
ARM GIC functions
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function ARMGICCreate(DistAddress,CPUAddress:PtrUInt):PGICDevice;
Description: To be documented
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function ARMGICStart(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetEntry(GIC:PGICDevice; CPUID,Number,Flags:LongWord; var Entry:TInterruptEntry; Index:LongWord):LongWord;
Description: To be documented
| Note
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The returned Entry is a copy of the registered value. Caller should free Entry if required.
For shared entries the Index parameter indicates which entry in the chain to return (0 equals first etc).
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function ARMGICRegisterEntry(GIC:PGICDevice; const Entry:TInterruptEntry):LongWord;
Description: To be documented
| Note
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Entry must be allocated from heap as a pointer so it will be retained while the interrupt remains registered.
Entry must not be freed by the caller.
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function ARMGICDeregisterEntry(GIC:PGICDevice; const Entry:TInterruptEntry):LongWord;
Description: To be documented
| Note
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The Entry can be a local temporary copy allocated either from the stack or on the heap, this routine will free the original Entry passed to Register once it is successfully deregistered.
Caller should free Entry if required.
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ARM GIC interrupt functions
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function ARMGICDispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: To be documented
| Note
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Called by ARMv7/8IRQHandler in PlatformARMv7/8
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function ARMGICDispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: To be documented
| Note
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Called by ARMv7/8FIQHandler in PlatformARMv7/8
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function ARMGICDispatchInterrupt(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: Process any pending IRQ/FIQ requests
| Note
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Called by ARMGICDispatchIRQ/ARMGICDispatchFIQ.
A DataMemoryBarrier is executed before and after calling this function.
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ARM GIC helper functions
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function ARMGICIsValid(GIC:PGICDevice; Number:LongWord):Boolean;
Description: To be documented
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function ARMGICIsLocal(GIC:PGICDevice; Number:LongWord):Boolean;
Description: To be documented
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function ARMGICIsSoftware(GIC:PGICDevice; Number:LongWord):Boolean;
Description: To be documented
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function ARMGICIsGlobal(GIC:PGICDevice; Number:LongWord):Boolean;
Description: To be documented
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function ARMGICGetIRQCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetFIQCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQStart(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQRouting(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetFIQRouting(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQLocalCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetFIQLocalCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQLocalStart(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQSoftwareCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetFIQSoftwareCount(GIC:PGICDevice):LongWord;
Description: To be documented
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function ARMGICGetIRQSoftwateStart(GIC:PGICDevice):LongWord;
Description: To be documented
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