Difference between revisions of "Unit PlatformQEMUVPB"

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|-
 
|-
 
| <code>QEMUVPB_KERNEL_NAME = 'kernel64.bin';</code>
 
| <code>QEMUVPB_KERNEL_NAME = 'kernel64.bin';</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 specific constants''' <code> PL110_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_FRAMEBUFFER_DESCRIPTION = 'ARM PrimeCell PL110 Color LCD';</code>
 +
| Description of PL110 device
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 mode''' <code> PL110_MODE_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_MODE_UNKNOWN = 0;</code>
 +
| &nbsp;
 +
|-
 +
| <code>PL110_MODE_VGA = 1;</code>
 +
| Connected to a VGA display
 +
|-
 +
| <code>PL110_MODE_SVGA = 2;</code>
 +
| Connected to a SVGA display
 +
|-
 +
| <code>PL110_MODE_TFT = 3;</code>
 +
| Connected to a TFT display
 +
|-
 +
| <code>PL110_MODE_STN = 4;</code>
 +
| Connected to an STN display
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 register offset''' <code> PL110_CLCD_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_TIMING0 = $00000000;</code>
 +
| Horizontal Axis Panel Control Register
 +
|-
 +
| <code>PL110_CLCD_TIMING1 = $00000004;</code>
 +
| Vertical Axis Panel Control Register
 +
|-
 +
| <code>PL110_CLCD_TIMING2 = $00000008;</code>
 +
| Clock and Signal Polarity Control Register
 +
|-
 +
| <code>PL110_CLCD_TIMING3 = $0000000c;</code>
 +
| Line End Control Register
 +
|-
 +
| <code>PL110_CLCD_UPBASE = $00000010;</code>
 +
| Upper Panel Frame Base Address Registers
 +
|-
 +
| <code>PL110_CLCD_LPBASE = $00000014;</code>
 +
| Lower Panel Frame Base Address Registers
 +
|-
 +
| <code>PL110_CLCD_CONTROL = $00000018;</code>
 +
| Control Register ''Note: Reversed in VersatilePB implementation, 0x0000001c in PL110 TRM''
 +
|-
 +
| <code>PL110_CLCD_IMSC = $0000001c;</code>
 +
| Interrupt Mask Set/Clear Register ''Note: Reversed in VersatilePB implementation, 0x00000018 in PL110 TRM''
 +
|-
 +
| <code>PL110_CLCD_RIS = $00000020;</code>
 +
| Raw Interrupt Status Register
 +
|-
 +
| <code>PL110_CLCD_MIS = $00000024;</code>
 +
| Masked Interrupt Status Register
 +
|-
 +
| <code>PL110_CLCD_ICR = $00000028;</code>
 +
| Interrupt Clear Register
 +
|-
 +
| <code>PL110_CLCD_UPCURR = $0000002C;</code>
 +
| Upper Panel Current Address Value Registers
 +
|-
 +
| <code>PL110_CLCD_LPCURR = $00000030;</code>
 +
| Lower Panel Current Address Value Registers
 +
|-
 +
| <code>PL110_CLCD_PALETTE = $00000200;</code>
 +
| Color Palette Register
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 CLCD timing0''' <code> PL110_CLCD_TIMING0_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_TIMING0_HBP = ($FF shl 24);</code>
 +
| Horizontal back porch
 +
|-
 +
| <code>PL110_CLCD_TIMING0_HFP = ($FF shl 16);</code>
 +
| Horizontal front porch
 +
|-
 +
| <code>PL110_CLCD_TIMING0_HSW = ($FF shl 8);</code>
 +
| Horizontal synchronization pulse width
 +
|-
 +
| <code>PL110_CLCD_TIMING0_PPL = ($FC shl 2);</code>
 +
| Pixels-per-line (Actual pixels-per-line = 16 * (PPL + 1))
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 CLCD timing1''' <code> PL110_CLCD_TIMING1_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_TIMING1_VBP = ($FF shl 24);</code>
 +
| Vertical back porch
 +
|-
 +
| <code>PL110_CLCD_TIMING1_VFP = ($FF shl 16);</code>
 +
| Vertical front porch
 +
|-
 +
| <code>PL110_CLCD_TIMING1_VSW = ($FC shl 10);</code>
 +
| Vertical synchronization pulse width
 +
|-
 +
| <code>PL110_CLCD_TIMING1_LPP = ($3FF shl 0);</code>
 +
| Lines per panel is the number of active lines per screen (Program to number of lines required minus 1)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 CLCD timing2''' <code> PL110_CLCD_TIMING2_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_TIMING2_PCD_HI = ($1F shl 27);</code>
 +
| Upper five bits of Panel Clock Divisor
 +
|-
 +
| <code>PL110_CLCD_TIMING2_BCD = (1 shl 26);</code>
 +
| Bypass pixel clock divider
 +
|-
 +
| <code>PL110_CLCD_TIMING2_CPL = ($3FF shl 16);</code>
 +
| Clocks per line
 +
|-
 +
| <code>PL110_CLCD_TIMING2_IOE = (1 shl 14);</code>
 +
| Invert output enable
 +
|-
 +
| <code>PL110_CLCD_TIMING2_IPC = (1 shl 13);</code>
 +
| Invert panel clock
 +
|-
 +
| <code>PL110_CLCD_TIMING2_IHS = (1 shl 12);</code>
 +
| Invert horizontal synchron
 +
|-
 +
| <code>PL110_CLCD_TIMING2_IVS = (1 shl 11);</code>
 +
| Invert vertical synchronization
 +
|-
 +
| <code>PL110_CLCD_TIMING2_ACB = ($1F shl 6);</code>
 +
| AC bias pin frequency
 +
|-
 +
| <code>PL110_CLCD_TIMING2_CLKSEL = (1 shl 5);</code>
 +
| This bit drives the CLCDCLKSEL signal which is used as the select signal for the external LCD clock multiplexor
 +
|-
 +
| <code>PL110_CLCD_TIMING2_PCD_LO = ($1F shl 0);</code>
 +
| Lower five bits of Panel Clock Divisor
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 CLCD timing3''' <code> PL110_CLCD_TIMING3_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_TIMING3_LEE = (1 shl 16);</code>
 +
| LCD Line end enable: 0 = CLLE disabled (held LOW)/1 = CLLE signal active
 +
|-
 +
| <code>PL110_CLCD_TIMING3_LED = ($3F shl 0);</code>
 +
| Line-end signal delay from the rising-edge of the last panel clock
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 CLCD control''' <code> PL110_CLCD_CONTROL_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/I913915.html
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDEN = (1 shl 0);</code>
 +
| &nbsp;
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP1 = (0 shl 1);</code>
 +
| LCD bits per pixel: 000 = 1 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP2 = (1 shl 1);</code>
 +
| LCD bits per pixel: 001 = 2 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP4 = (2 shl 1);</code>
 +
| LCD bits per pixel: 010 = 4 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP8 = (3 shl 1);</code>
 +
| LCD bits per pixel: 011 = 8 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP16 = (4 shl 1);</code>
 +
| LCD bits per pixel: 100 = 16 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP16_565 = (6 shl 1);</code>
 +
| LCD bits per pixel: 110 = 16 bpp 565 (PL111 only)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP16_444 = (7 shl 1);</code>
 +
| LCD bits per pixel: 111 = 16 bpp 444 (PL111 only)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBPP24 = (5 shl 1);</code>
 +
| LCD bits per pixel: 101 = 24 bpp
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDBW = (1 shl 4);</code>
 +
| STN LCD is monochrome (black and white) (0 = STN LCD is color/1 = STN LCD is monochrome)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDTFT = (1 shl 5);</code>
 +
| LCD is TFT (0 = LCD is an STN display, use gray scaler/1 = LCD is TFT, do not use gray scaler)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDMONO8 = (1 shl 6);</code>
 +
| Monochrome LCD has an 8-bit interface (0 = mono LCD uses 4-bit interface/1 = mono LCD uses 8-bit interface)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDDUAL = (1 shl 7);</code>
 +
| LCD interface is dual panel STN (0 = single panel LCD is in use/1 = dual panel LCD is in use)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_BGR = (1 shl 8);</code>
 +
| RGB of BGR format selection (0 = RGB normal output/1 = BGR red and blue swapped.)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_BEBO = (1 shl 9);</code>
 +
| Big-endian byte order (0 = little-endian byte order/1 = big-endian byte order)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_BEPO = (1 shl 10);</code>
 +
| Big-endian pixel ordering within a byte (0 = little-endian pixel ordering within a byte/1= big-endian pixel ordering within a byte)
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDPWR = (1 shl 11);</code>
 +
| LCD power enable
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDVCOMP_VSYNC = (0 shl 12);</code>
 +
| Generate interrupt at: 00 = start of vertical synchronization
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDVCOMP_BPORCH = (1 shl 12);</code>
 +
| Generate interrupt at: 01 = start of back porch
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDVCOMP_VIDEO = (2 shl 12);</code>
 +
| Generate interrupt at: 10 = start of active video
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LCDVCOMP_FPORCH = (3 shl 12);</code>
 +
| Generate interrupt at: 11 = start of front porch
 +
|-
 +
| <code>PL110_CLCD_CONTROL_LDMAFIFOTIME = (1 shl 15);</code>
 +
| Unknown
 +
|-
 +
| <code>PL110_CLCD_CONTROL_WATERMARK = (1 shl 16);</code>
 +
| LCD DMA FIFO Watermark level
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 control''' <code> PL110_CONTROL_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_CONTROL_VGA = PL110_CLCD_CONTROL_LCDTFT or PL110_CLCD_CONTROL_LCDVCOMP_BPORCH;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>PL110_CONTROL_SVGA = PL110_CLCD_CONTROL_LCDTFT or PL110_CLCD_CONTROL_LCDVCOMP_BPORCH;</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 timing0''' <code> PL110_TIMING0_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_TIMING0_VGA = $3F1F3F9C;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>PL110_TIMING0_SVGA = $1313A4C4;</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 timing1''' <code> PL110_TIMING1_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_TIMING1_VGA = $090B61DF;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>PL110_TIMING1_SVGA = $0505F657;</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br /> 
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL110 timing2''' <code> PL110_TIMING2_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>PL110_TIMING2_VGA = $067F1800;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
| <code>PL110_TIMING2_SVGA = $071F1800;</code>
 
| &nbsp;
 
| &nbsp;
 
|-
 
|-

Revision as of 01:31, 31 May 2017

Return to Unit Reference


Description

Ultibo Platform interface unit for QEMU VersatilePB

To be documented

Constants


[Expand]
QEMUVPB specific constants QEMUVPB_*


[Expand]
QEMUVPB page table QEMUVPB_PAGE_TABLE_*


[Expand]
QEMUVPB vector table QEMUVPB_VECTOR_TABLE_*


[Expand]
QEMUVPB CPU count QEMUVPB_CPU_*


[Expand]
QEMUVPB SWI QEMUVPB_SWI_*


[Expand]
QEMUVPB kernel name QEMUVPB_KERNEL_*


[Expand]
PL110 specific constants PL110_*


[Expand]
PL110 mode PL110_MODE_*


[Expand]
PL110 register offset PL110_CLCD_*


[Expand]
PL110 CLCD timing0 PL110_CLCD_TIMING0_*


[Expand]
PL110 CLCD timing1 PL110_CLCD_TIMING1_*


[Expand]
PL110 CLCD timing2 PL110_CLCD_TIMING2_*


[Expand]
PL110 CLCD timing3 PL110_CLCD_TIMING3_*


[Expand]
PL110 CLCD control PL110_CLCD_CONTROL_*


[Expand]
PL110 control PL110_CONTROL_*


[Expand]
PL110 timing0 PL110_TIMING0_*


[Expand]
PL110 timing1 PL110_TIMING1_*


[Expand]
PL110 timing2 PL110_TIMING2_*


Type definitions


PL110 CLCD registers

[Expand]

PPL110CLCDRegisters = ^TPL110CLCDRegisters;

TPL110CLCDRegisters = record

PL110 framebuffer

[Expand]

PPL110Framebuffer = ^TPL110Framebuffer;

TPL110Framebuffer = record


Public variables


QEMUVPB specific Ultibo variables

QEMUVPBInitialized:Boolean;

Clock variables

ClockGetLast:LongWord; Value of 24MHz Counter on last ClockGetCount or ClockGetTotal call
ClockGetBase:Int64; Base value for 64-bit clock, incremented each time the 24MHz Counter rolls over (Only accurate if ClockGetCount/ClockGetTotal is called at least once per 178 seconds)
ClockGetLock:THandle = INVALID_HANDLE_VALUE; Lock handle for creating 64-bit clock from a 32-bit register
ClockGetTimer:THandle = INVALID_HANDLE_VALUE; Timer handle for ensuring clock is read periodically to maintain accurracy

Timer variables

Timer0Registers:PSP804TimerRegisters; Use Timer0 for Clock
Timer2Registers:PSP804TimerRegisters; Use Timer2 for Scheduler

Interrupt variables

PrimaryInterruptRegisters:PPL190InterruptRegisters;
SecondaryInterruptRegisters:PVersatilePBInterruptRegisters;
InterruptEntries:array[0..(VERSATILEPB_IRQ_COUNT - 1)] of TInterruptEntry;

System call

SystemCallEntries:array[0..QEMUVPB_SWI_COUNT - 1] of TSystemCallEntry;

IRQ/FIQ

IRQEnabled:array[0..1] of LongWord; 2 groups of IRQs to Enable/Disable (See: TPL190InterruptRegisters)
FIQEnabled:LongWord; The single IRQ number to Enable as FIQ instead (See: TPL190InterruptRegisters)


Function declarations


Initialization functions

[Expand] 
procedure QEMUVPBInit;
Description: To be documented


QEMUVPB platform functions

[Expand] 
procedure QEMUVPBBoardInit;
Description: To be documented


[Expand] 
procedure QEMUVPBMemoryInit;
Description: To be documented


[Expand] 
procedure QEMUVPBClockInit;
Description: To be documented


[Expand] 
procedure QEMUVPBPowerInit;
Description: To be documented


[Expand] 
procedure QEMUVPBInterruptInit;
Description: To be documented


[Expand] 
procedure QEMUVPBPeripheralInit;
Description: To be documented


[Expand] 
procedure QEMUVPBFramebufferInit;
Description: To be documented


[Expand] 
procedure QEMUVPBPageTableInit;
Description: Initialize the Hardware Page Tables before enabling the MMU


[Expand] 
function QEMUVPBRequestExIRQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request registration of the supplied handler to the specified IRQ number


[Expand] 
function QEMUVPBReleaseExIRQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request deregistration of the supplied handler from the specified IRQ number


[Expand] 
function QEMUVPBRequestExFIQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request registration of the supplied handler to the specified FIQ number


[Expand] 
function QEMUVPBReleaseExFIQ(CPUID,Number:LongWord; Handler:TInterruptHandler; HandlerEx:TInterruptExHandler; Parameter:Pointer):LongWord;
Description: Request deregistration of the supplied handler from the specified FIQ number


[Expand] 
function QEMUVPBRegisterSystemCallEx(CPUID,Number:LongWord; Handler:TSystemCallHandler; HandlerEx:TSystemCallExHandler):LongWord;
Description: Request registration of the supplied extended handler to the specified System Call number


[Expand] 
function QEMUVPBDeregisterSystemCallEx(CPUID,Number:LongWord; Handler:TSystemCallHandler; HandlerEx:TSystemCallExHandler):LongWord;
Description: Request deregistration of the supplied extended handler from the specified System Call number


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function QEMUVPBGetInterruptEntry(Number:LongWord):TInterruptEntry;
Description: To be documented


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function QEMUVPBGetSystemCallEntry(Number:LongWord):TSystemCallEntry;
Description: Get the system call entry for the specified system call number


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function QEMUVPBSystemRestart(Delay:LongWord):LongWord;
Description: To be documented


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function QEMUVPBSystemShutdown(Delay:LongWord):LongWord;
Description: To be documented


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function QEMUVPBClockGetCount:LongWord;
Description: Gets the current system clock count (32 least significant bits of total)


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function QEMUVPBClockGetTotal:Int64;
Description: Gets the total system clock count


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procedure QEMUVPBClockGetTimer(Data:Pointer);
Description: Timer procedure to ensure ClockGetTotal is called at least once per rollover interval


QEMUVPB thread functions

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procedure QEMUVPBSchedulerInit;
Description: Initialize the scheduler interrupt on the boot CPU


QEMUVPB IRQ functions

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function QEMUVPBDispatchIRQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: Process any pending IRQ requests


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function QEMUVPBHandleIRQ(Number,CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: Call the handler function for an IRQ that was received, or halt if it doesn't exist


QEMUVPB FIQ functions

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function QEMUVPBDispatchFIQ(CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: Process any pending FIQ requests


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function QEMUVPBHandleFIQ(Number,CPUID:LongWord; Thread:TThreadHandle):TThreadHandle;
Description: Call the handler function for an FIQ that was received, or halt if it doesn't exist


QEMUVPB SWI functions

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function QEMUVPBDispatchSWI(CPUID:LongWord; Thread:TThreadHandle; Request:PSystemCallRequest):TThreadHandle;
Description: Process an SWI request


QEMUVPB clock functions

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procedure QEMUVPBClockInterrupt(Parameter:Pointer);
Description: Interrupt handler function for the clock interrupt


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procedure QEMUVPBClockUpdate(Cycles:LongWord; var Last:LongWord);
Description: Setup a clock interrupt to trigger after the specified number of clock cycles


QEMUVPB scheduler functions

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function QEMUVPBSchedulerInterrupt(CPUID:LongWord; Thread:TThreadHandle; Parameter:Pointer):TThreadHandle;
Description: Interrupt handler function for the scheduler interrupt


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procedure QEMUVPBSchedulerUpdate(Cycles:LongWord; var Last:LongWord);
Description: Setup a scheduler interrupt to trigger after the specified number of clock cycles


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procedure QEMUVPBSchedulerSystemCall(Request:PSystemCallRequest);
Description: System Call handler for the scheduler


QEMUVPB framebuffer functions

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function QEMUVPBFramebufferDeviceAllocate(Framebuffer:PFramebufferDevice; Properties:PFramebufferProperties):LongWord;
Description: Implementation of FramebufferDeviceAllocate API for PL110 Framebuffer


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function QEMUVPBFramebufferDeviceRelease(Framebuffer:PFramebufferDevice):LongWord;
Description: Implementation of FramebufferDeviceRelease API for PL110 Framebuffer


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function QEMUVPBFramebufferDeviceBlank(Framebuffer:PFramebufferDevice; Blank:Boolean):LongWord;
Description: Implementation of FramebufferDevicBlank API for PL110 Framebuffer


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function QEMUVPBFramebufferDeviceCommit(Framebuffer:PFramebufferDevice; Address,Size,Flags:LongWord):LongWord;
Description: Implementation of FramebufferDeviceCommit API for PL110 Framebuffer


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function QEMUVPBFramebufferDeviceSetProperties(Framebuffer:PFramebufferDevice; Properties:PFramebufferProperties):LongWord;
Description: Implementation of FramebufferDeviceSetProperties API for PL110 Framebuffer


QEMUVPB helper functions

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procedure QEMUVPBBootBlink; assembler; nostackframe;
Description: Output characters to UART0 without dependency on any other RTL setup


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procedure QEMUVPBBootOutput(Value:LongWord);
Description: Output characters to UART0 without dependency on any other RTL setup


Return to Unit Reference

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