Difference between revisions of "Unit VersatilePB"

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Line 47: Line 47:
 
----
 
----
  
−
''To be documented''
+
 
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB specific constants''' <code> VERSATILEPB_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
| <code>VERSATILEPB_CPU_COUNT = 1;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|Physical memory addresses of VersatilePB peripherals (See: \hw\arm\versatilepb.c and http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Bbajihec.html)
 +
See also: \arch\arm\mach-versatile\include\mach\platform.h
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_PERIPHERALS_BASE = $10000000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_PERIPHERALS_SIZE = $001FFFFF;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|''Peripherals''
 +
|-
 +
| <code>VERSATILEPB_SYS_REGS_BASE = $10000000;</code>
 +
| System Registers
 +
|-
 +
| <code>VERSATILEPB_PCI_CORE_REGS_BASE = $10001000;</code>
 +
| PCI core control
 +
|-
 +
| <code>VERSATILEPB_I2C_REGS_BASE = $10002000;</code>
 +
| I2C control
 +
|-
 +
| <code>VERSATILEPB_SIC_REGS_BASE = $10003000;</code>
 +
| Secondary interrupt controller
 +
|-
 +
| <code>VERSATILEPB_AACI_REGS_BASE = $10004000;</code>
 +
| PL041 Audio
 +
|-
 +
| <code>VERSATILEPB_MMCI0_REGS_BASE = $10005000;</code>
 +
| PL180 MMC interface
 +
|-
 +
| <code>VERSATILEPB_KMI0_REGS_BASE = $10006000;</code>
 +
| PL050 KMI interface
 +
|-
 +
| <code>VERSATILEPB_KMI1_REGS_BASE = $10007000;</code>
 +
| PL050 KMI 2nd interface
 +
|-
 +
| <code>VERSATILEPB_CHAR_LCD_REGS_BASE = $10008000;</code>
 +
| Character LCD
 +
|-
 +
| <code>VERSATILEPB_UART3_REGS_BASE = $10009000;</code>
 +
| PL011 UART 3
 +
|-
 +
| <code>VERSATILEPB_SCI1_REGS_BASE = $1000A000;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_MMCI1_REGS_BASE = $1000B000;</code>
 +
| PL180 MMC Interface
 +
|-
 +
|colspan="2"|''0x1000C000 - 0x1000CFFF = reserved''
 +
|-
 +
| <code>VERSATILEPB_ETH_REGS_BASE = $10010000;</code>
 +
| LAN91C111 Ethernet
 +
|-
 +
| <code>VERSATILEPB_USB_REGS_BASE = $10020000;</code>
 +
| OHCI USB
 +
|-
 +
|colspan="2"|''0x10030000 - 0x100FFFFF = reserved''
 +
|-
 +
| <code>VERSATILEPB_SMC_REGS_BASE = $10100000;</code>
 +
| SMC
 +
|-
 +
| <code>VERSATILEPB_MPMC_REGS_BASE = $10110000;</code>
 +
| MPMC
 +
|-
 +
| <code>VERSATILEPB_CLCD_REGS_BASE = $10120000;</code>
 +
| PL110 CLCD
 +
|-
 +
| <code>VERSATILEPB_DMAC_REGS_BASE = $10130000;</code>
 +
| PL080 DMA controller
 +
|-
 +
| <code>VERSATILEPB_VIC_REGS_BASE = $10140000;</code>
 +
| PL190Vectored interrupt controller
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_AHBM_REGS_BASE = $101D0000;</code>
 +
| AHB monitor
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_REGS_BASE = $101E0000;</code>
 +
| System controller
 +
|-
 +
| <code>VERSATILEPB_WATCHDOG_REGS_BASE = $101E1000;</code>
 +
| Watchdog
 +
|-
 +
| <code>VERSATILEPB_TIMER0_REGS_BASE = $101e2000;</code>
 +
| SP804 Timer 0
 +
|-
 +
| <code>VERSATILEPB_TIMER1_REGS_BASE = $101e2020;</code>
 +
| SP804 Timer 1
 +
|-
 +
| <code>VERSATILEPB_TIMER2_REGS_BASE = $101e3000;</code>
 +
| SP804 Timer 2
 +
|-
 +
| <code>VERSATILEPB_TIMER3_REGS_BASE = $101e3020;</code>
 +
| SP804 Timer 3
 +
|-
 +
| <code>VERSATILEPB_GPIO0_REGS_BASE = $101E4000;</code>
 +
| PL061 GPIO port 0
 +
|-
 +
| <code>VERSATILEPB_GPIO1_REGS_BASE = $101E5000;</code>
 +
| PL061 GPIO port 1
 +
|-
 +
| <code>VERSATILEPB_GPIO2_REGS_BASE = $101E6000;</code>
 +
| PL061 GPIO port 2
 +
|-
 +
| <code>VERSATILEPB_GPIO3_REGS_BASE = $101E7000;</code>
 +
| PL061 GPIO port 3
 +
|-
 +
| <code>VERSATILEPB_RTC_REGS_BASE = $101E8000;</code>
 +
| PL031 Real Time Clock
 +
|-
 +
|colspan="2"|''0x101E9000 - reserved''
 +
|-
 +
| <code>VERSATILEPB_SCI_REGS_BASE = $101F0000;</code>
 +
| Smart card controller
 +
|-
 +
| <code>VERSATILEPB_UART0_REGS_BASE = $101f1000;</code>
 +
| PL011 UART0
 +
|-
 +
| <code>VERSATILEPB_UART1_REGS_BASE = $101f2000;</code>
 +
| PL011 UART1
 +
|-
 +
| <code>VERSATILEPB_UART2_REGS_BASE = $101f3000;</code>
 +
| PL011 UART2
 +
|-
 +
| <code>VERSATILEPB_SSP_REGS_BASE = $101F4000;</code>
 +
| Synchronous Serial Port
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB IRQ''' <code> VERSATILEPB_IRQ_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|IRQ lines of VersatilePB peripherals (See: \hw\arm\versatilepb.c and http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Bbajihec.html)
 +
Interrupt Assignments (Primary)(See: \arch\arm\mach-versatile\include\mach\platform.h)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_WDOG = 0;</code>
 +
| Watchdog timer
 +
|-
 +
| <code>VERSATILEPB_IRQ_SOFT = 1;</code>
 +
| Software interrupt
 +
|-
 +
| <code>VERSATILEPB_IRQ_COMMRX = 2;</code>
 +
| Debug Comm Rx interrupt
 +
|-
 +
| <code>VERSATILEPB_IRQ_COMMTX = 3;</code>
 +
| Debug Comm Tx interrupt
 +
|-
 +
| <code>VERSATILEPB_IRQ_TIMER0_1 = 4;</code>
 +
| Timer 0 and 1
 +
|-
 +
| <code>VERSATILEPB_IRQ_TIMER2_3 = 5;</code>
 +
| Timer 2 and 3
 +
|-
 +
| <code>VERSATILEPB_IRQ_GPIO0 = 6;</code>
 +
| GPIO 0
 +
|-
 +
| <code>VERSATILEPB_IRQ_GPIO1 = 7;</code>
 +
| GPIO 1
 +
|-
 +
| <code>VERSATILEPB_IRQ_GPIO2 = 8;</code>
 +
| GPIO 2
 +
|-
 +
| <code>VERSATILEPB_IRQ_GPIO3 = 9;</code>
 +
| GPIO 3
 +
|-
 +
| <code>VERSATILEPB_IRQ_RTC = 10;</code>
 +
| Real Time Clock
 +
|-
 +
| <code>VERSATILEPB_IRQ_SSP = 11;</code>
 +
| Synchronous Serial Port
 +
|-
 +
| <code>VERSATILEPB_IRQ_UART0 = 12;</code>
 +
| UART 0 on development chip
 +
|-
 +
| <code>VERSATILEPB_IRQ_UART1 = 13;</code>
 +
| UART 1 on development chip
 +
|-
 +
| <code>VERSATILEPB_IRQ_UART2 = 14;</code>
 +
| UART 2 on development chip
 +
|-
 +
| <code>VERSATILEPB_IRQ_SCI = 15;</code>
 +
| Smart Card Interface
 +
|-
 +
| <code>VERSATILEPB_IRQ_CLCD = 16;</code>
 +
| CLCD controller
 +
|-
 +
| <code>VERSATILEPB_IRQ_DMA = 17;</code>
 +
| DMA controller
 +
|-
 +
| <code>VERSATILEPB_IRQ_PWRFAIL = 18;</code>
 +
| Power failure
 +
|-
 +
| <code>VERSATILEPB_IRQ_MBX = 19;</code>
 +
| Graphics processor
 +
|-
 +
| <code>VERSATILEPB_IRQ_GND = 20;</code>
 +
| Reserved
 +
|-
 +
|colspan="2"|''External interrupt signals from logic tiles or secondary controller''
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE21 = 21;</code>
 +
| Disk on Chip
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE22 = 22;</code>
 +
| MCI0A
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE23 = 23;</code>
 +
| MCI1A
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE24 = 24;</code>
 +
| AACI
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE25 = 25;</code>
 +
| Ethernet
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE26 = 26;</code>
 +
| USB
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE27 = 27;</code>
 +
| PCI 0
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE28 = 28;</code>
 +
| PCI 1
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE29 = 29;</code>
 +
| PCI 2
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE30 = 30;</code>
 +
| PCI 3
 +
|-
 +
| <code>VERSATILEPB_IRQ_VICSOURCE31 = 31;</code>
 +
| SIC source
 +
|-
 +
|colspan="2"|''Passthrough interrupt signals from secondary controller''
 +
|-
 +
| <code>VERSATILEPB_IRQ_DOC = VERSATILEPB_IRQ_VICSOURCE21;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_MMCI0A = VERSATILEPB_IRQ_VICSOURCE22;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_MMCI1A = VERSATILEPB_IRQ_VICSOURCE23;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_AACI = VERSATILEPB_IRQ_VICSOURCE24;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_ETH = VERSATILEPB_IRQ_VICSOURCE25;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_USB = VERSATILEPB_IRQ_VICSOURCE26;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_PCI0 = VERSATILEPB_IRQ_VICSOURCE27;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_PCI1 = VERSATILEPB_IRQ_VICSOURCE28;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_PCI2 = VERSATILEPB_IRQ_VICSOURCE29;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_PCI3 = VERSATILEPB_IRQ_VICSOURCE30;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_IRQ_SICSOURCE = VERSATILEPB_IRQ_VICSOURCE31;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|Interrupt Assignments (Secondary)(See: \arch\arm\mach-versatile\include\mach\platform.h)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_SOFTINT = 32;</code>
 +
| SIC IRQ 0 (Soft Interrupt)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_MMCI0B = 33;</code>
 +
| SIC IRQ 1 (Multimedia Card 0B)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_MMCI1B = 34;</code>
 +
| SIC IRQ 2 (Multimedia Card 1B)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_KMI0 = 35;</code>
 +
| SIC IRQ 3 (Keyboard/Mouse port 0)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_KMI1 = 36;</code>
 +
| SIC IRQ 4 (Keyboard/Mouse port 1)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_SCI3 = 37;</code>
 +
| SIC IRQ 5 (Smart Card interface)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_UART3 = 38;</code>
 +
| SIC IRQ 6 (UART 3 empty or data available)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_CHAR_LCD = 39;</code>
 +
| SIC IRQ 7 (Character LCD)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_TOUCH = 40;</code>
 +
| SIC IRQ 8 (Touchscreen)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_KEYPAD = 41;</code>
 +
| SIC IRQ 9 (Key pressed on display keypad)
 +
|-
 +
|colspan="2"|''42 to 52 (SIC IRQ 10 to 20) - Reserved''
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_DOC = 53;</code>
 +
| SIC IRQ 21 (Disk on Chip memory controller)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_MMCI0A = 54;</code>
 +
| SIC IRQ 22 (MMC 0A)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_MMCI1A = 55;</code>
 +
| SIC IRQ 23 (MMC 1A)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_AACI = 56;</code>
 +
| SIC IRQ 24 (Audio Codec)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_ETH = 57;</code>
 +
| SIC IRQ 25 (Ethernet controller)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_USB = 58;</code>
 +
| SIC IRQ 26 (USB controller)
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_PCI0 = 59;</code>
 +
| SIC IRQ 27
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_PCI1 = 60;</code>
 +
| SIC IRQ 28
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_PCI2 = 61;</code>
 +
| SIC IRQ 29
 +
|-
 +
| <code>VERSATILEPB_IRQ_SIC_PCI3 = 62;</code>
 +
| SIC IRQ 30
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB IRQ count''' <code> VERSATILEPB_*_IRQ_COUNT* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|Number of IRQs on the Vectored (Primary) Interrupt Controller (VIC)
 +
|-
 +
| <code>VERSATILEPB_VIC_IRQ_COUNT = 32;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|Number of IRQs on the Secondary Interrupt Controller (SIC)
 +
|-
 +
| <code>VERSATILEPB_SIC_IRQ_COUNT = 32;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|Total number of IRQs available
 +
|-
 +
| <code>VERSATILEPB_IRQ_COUNT = VERSATILEPB_VIC_IRQ_COUNT + VERSATILEPB_SIC_IRQ_COUNT;</code>
 +
| 64
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB FIQ count''' <code> VERSATILEPB_FIQ_COUNT* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|Total number of FIQs available
 +
|-
 +
| <code>VERSATILEPB_FIQ_COUNT = 1;</code>
 +
| style="width: 50%;"|&nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB timer frequency''' <code> VERSATILEPB_TIMER_FREQUENCY* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|Timer frequencies
 +
|-
 +
| <code>VERSATILEPB_TIMER_FREQUENCY = 1000000;</code>
 +
| Default frequency of the VersatilePB Timer when reference is set to TIMCLK (1MHz)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB system register''' <code> VERSATILEPB_SYS_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|System register offsets (See: \arm\mach-versatile\include\mach\platform.h and http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/I1006122.html)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_ID = VERSATILEPB_SYS_REGS_BASE + $00;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_SW = VERSATILEPB_SYS_REGS_BASE + $04;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_LED = VERSATILEPB_SYS_REGS_BASE + $08;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSC0 = VERSATILEPB_SYS_REGS_BASE + $0C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSC1 = VERSATILEPB_SYS_REGS_BASE + $10;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSC2 = VERSATILEPB_SYS_REGS_BASE + $14;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSC3 = VERSATILEPB_SYS_REGS_BASE + $18;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSC4 = VERSATILEPB_SYS_REGS_BASE + $1C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_OSCCLCD = VERSATILEPB_SYS_REGS_BASE + $1c;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_LOCK = VERSATILEPB_SYS_REGS_BASE + $20;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_100HZ = VERSATILEPB_SYS_REGS_BASE + $24;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_CFGDATA1 = VERSATILEPB_SYS_REGS_BASE + $28;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_CFGDATA2 = VERSATILEPB_SYS_REGS_BASE + $2C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_FLAGS = VERSATILEPB_SYS_REGS_BASE + $30;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_FLAGSSET = VERSATILEPB_SYS_REGS_BASE + $30;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_FLAGSCLR = VERSATILEPB_SYS_REGS_BASE + $34;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_NVFLAGS = VERSATILEPB_SYS_REGS_BASE + $38;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_NVFLAGSSET = VERSATILEPB_SYS_REGS_BASE + $38;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_NVFLAGSCLR = VERSATILEPB_SYS_REGS_BASE + $3C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_RESETCTL = VERSATILEPB_SYS_REGS_BASE + $40;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_PCICTL = VERSATILEPB_SYS_REGS_BASE + $44;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_MCI = VERSATILEPB_SYS_REGS_BASE + $48;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_FLASH = VERSATILEPB_SYS_REGS_BASE + $4C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD = VERSATILEPB_SYS_REGS_BASE + $50;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCDSER = VERSATILEPB_SYS_REGS_BASE + $54;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_BOOTCS = VERSATILEPB_SYS_REGS_BASE + $58;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_24MHZ = VERSATILEPB_SYS_REGS_BASE + $5C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_MISC = VERSATILEPB_SYS_REGS_BASE + $60;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_TEST_OSC0 = VERSATILEPB_SYS_REGS_BASE + $80;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_TEST_OSC1 = VERSATILEPB_SYS_REGS_BASE + $84;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_TEST_OSC2 = VERSATILEPB_SYS_REGS_BASE + $88;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_TEST_OSC3 = VERSATILEPB_SYS_REGS_BASE + $8C;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_TEST_OSC4 = VERSATILEPB_SYS_REGS_BASE + $90;</code>
 +
| &nbsp;
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|System register bits (See: \arm\mach-versatile\include\mach\platform.h and http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/I1006122.html)
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD_MODE888 = 0;</code>
 +
| LCD Mode [1:0], controls mapping of video memory to RGB signals 00 = 8:8:8
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD_MODE5551 = 1;</code>
 +
| 01 = 5:5:5:1
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD_MODE565BGR = 2;</code>
 +
| 10 = 5:6:5, red LSB
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD_MODE565RGB = 3;</code>
 +
| 11 = 5:6:5, blue LSB
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYS_CLCD_MODEMASK = 3;</code>
 +
| &nbsp;
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB system control''' <code> VERSATILEPB_SYSCTRL_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|System Control register bits (See: http://infocenter.arm.com/help/topic/com.arm.doc.dui0440b/CACIHEAD.html)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_REFCLK = 0;</code>
 +
| REFCLK is 32.768kHz
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_TIMCLK = 1;</code>
 +
| TIMCLK is 1MHz
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_TIMER0_ENSEL = 15;</code>
 +
| Timer 0 enable/Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_TIMER1_ENSEL = 17;</code>
 +
| Timer 1 enable/Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_TIMER2_ENSEL = 19;</code>
 +
| Timer 2 enable/Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.
 +
|-
 +
| <code>VERSATILEPB_SYSCTRL_TIMER3_ENSEL = 21;</code>
 +
| Timer 3 enable/Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''SP804 timer''' <code> SP804_TIMER_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|SP804 Timer register offsets (See: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0271d/DDI0271.pdf)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>SP804_TIMER_LOAD = $00;</code>
 +
| Timer Load register
 +
|-
 +
| <code>SP804_TIMER_VALUE = $04;</code>
 +
| Timer Value register
 +
|-
 +
| <code>SP804_TIMER_CONTROL = $08;</code>
 +
| Timer control register
 +
|-
 +
| <code>SP804_TIMER_INT_CLEAR = $0c;</code>
 +
| Timer Interrupt clear register
 +
|-
 +
| <code>SP804_TIMER_RAW_INT = $10;</code>
 +
| Timer Raw Interrupt register
 +
|-
 +
| <code>SP804_TIMER_MASKED_INT = $14;</code>
 +
| Timer Masked Interrupt register
 +
|-
 +
| <code>SP804_TIMER_BACKGROUND_LOAD = $18;</code>
 +
| Timer Background Load register
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''SP804 timer control''' <code> SP804_TIMER_CONTROL_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|SP804 Timer register bits (See: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0271d/DDI0271.pdf)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>SP804_TIMER_CONTROL_ONESHOT = (1 shl 0);</code>
 +
| Selects one-shot or wrapping counter mode: (0 = wrapping mode (default)/1 = one-shot mode)
 +
|-
 +
| <code>SP804_TIMER_CONTROL_32BIT = (1 shl 1);</code>
 +
| Selects 16/32 bit counter operation: (0 = 16-bit counter (default)/1 = 32-bit counter)
 +
|-
 +
| <code>SP804_TIMER_CONTROL_PRESCALE1 = (0 shl 2);</code>
 +
| Prescale bits: 00 = 0 stages of prescale, clock is divided by 1 (default)
 +
|-
 +
| <code>SP804_TIMER_CONTROL_PRESCALE16 = (1 shl 2);</code>
 +
| 01 = 4 stages of prescale, clock is divided by 16
 +
|-
 +
| <code>SP804_TIMER_CONTROL_PRESCALE256 = (2 shl 2);</code>
 +
| 10 = 8 stages of prescale, clock is divided by 256
 +
|-
 +
| <code>SP804_TIMER_CONTROL_INT_ENABLED = (1 shl 5);</code>
 +
| Interrupt Enable bit: (0 = Timer module Interrupt disabled/1 = Timer module Interrupt enabled (default))
 +
|-
 +
| <code>SP804_TIMER_CONTROL_PERIODIC = (1 shl 6);</code>
 +
| Mode bit: (0 = Timer module is in free-running mode (default)/1 = Timer module is in periodic mode)
 +
|-
 +
| <code>SP804_TIMER_CONTROL_TIMER_ENABLED = (1 shl 7);</code>
 +
| Enable bit: (0 = Timer module disabled (default)/1 = Timer module enabled)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL190 vectored interrupt controller offsets''' <code> PL190_VIC_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|PL190 Vectored Interrupt Controller register offsets (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0181e/index.html)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL190_VIC_IRQSTATUS = $00;</code>
 +
| IRQ Status Register
 +
|-
 +
| <code>PL190_VIC_FIQSTATUS = $04;</code>
 +
| FIQ Status Register
 +
|-
 +
| <code>PL190_VIC_RAWINTR = $08;</code>
 +
| Raw Interrupt Status Register
 +
|-
 +
| <code>PL190_VIC_INTSELECT = $0c;</code>
 +
| Interrupt Select Register (1 = FIQ, 0 = IRQ)
 +
|-
 +
| <code>PL190_VIC_INTENABLE = $10;</code>
 +
| Interrupt Enable Register
 +
|-
 +
| <code>PL190_VIC_INTENCLEAR = $14;</code>
 +
| Interrupt Enable Clear Register
 +
|-
 +
| <code>PL190_VIC_SOFTINT = $18;</code>
 +
| Software Interrupt Register
 +
|-
 +
| <code>PL190_VIC_SOFTINTCLEAR = $1c;</code>
 +
| Software Interrupt Clear Register
 +
|-
 +
| <code>PL190_VIC_PROTECTION = $20;</code>
 +
| Protection Enable Register
 +
|-
 +
| <code>PL190_VIC_VECTADDR = $30;</code>
 +
| Vector Address Register (PL190 only)
 +
|-
 +
| <code>PL190_VIC_DEFVECTADDR = $34;</code>
 +
| Default Vector Address Register (PL190 only)
 +
|-
 +
| <code>PL190_VIC_VECTADDR0 = $100;</code>
 +
| Vector Address Registers (0 to 15) (0..31 PL192)
 +
|-
 +
| <code>PL190_VIC_VECTCNTL0 = $200;</code>
 +
| Vector Control Registers (0 to 15) (0..31 PL192)
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''PL190 vectored interrupt controller register''' <code> PL190_VIC_VECTCNTL_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|PL190 Vectored Interrupt Controller register bits (See: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0181e/index.html)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>PL190_VIC_VECTCNTL_ENABLE = (1 shl 5);</code>
 +
| Enables vector interrupt (This bit is cleared on reset)
 +
|-
 +
| <code>PL190_VIC_VECTCNTL_INTSOURCE = ($1F shl 0);</code>
 +
| Selects interrupt source 0 to 31
 +
|-
 +
|}
 +
</div></div>
 +
<br />
 +
 
 +
<div class="toccolours mw-collapsible mw-collapsed" style="border: 1; font-family: arial; padding-top: 20px; padding-bottom: 15px;">
 +
<div style="font-size: 14px; padding-left: 12px;">'''VersatilePB secondary interrupt controller''' <code> VERSATILEPB_SIC_* </code></div>
 +
<div class="mw-collapsible-content" style="text-align: left; padding-left: 5px;">
 +
{| class="wikitable" style="font-size: 14px; background: white;"
 +
|-
 +
|colspan="2"|VersatilePB Secondary Interrupt Controller register offsets (See: http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdggia.html)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
| <code>VERSATILEPB_SIC_STATUS = $00;</code>
 +
| Status of interrupt (after mask) (Read)
 +
|-
 +
| <code>VERSATILEPB_SIC_RAWSTAT = $04;</code>
 +
| Status of interrupt (before mask) (Read)
 +
|-
 +
| <code>VERSATILEPB_SIC_ENABLE = $08;</code>
 +
| Interrupt mask / Set bits HIGH to enable the corresponding interrupt signals (Read/Write)
 +
|-
 +
| <code>VERSATILEPB_SIC_ENSET = $08;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SIC_ENCLR = $0C;</code>
 +
| Set bits HIGH to mask the corresponding interrupt signals (Write)
 +
|-
 +
| <code>VERSATILEPB_SIC_SOFTINTSET = $10;</code>
 +
| Set software interrupt (Read/Write)
 +
|-
 +
| <code>VERSATILEPB_SIC_SOFTINTCLR = $14;</code>
 +
| Clear software interrupt (Write)
 +
|-
 +
| <code>VERSATILEPB_SIC_PICENABLE = $20;</code>
 +
| Pass-through mask (allows interrupt to pass directly to the primary interrupt controller)/Set bits HIGH to set the corresponding interrupt pass-through mask bits (Read/Write)
 +
|-
 +
| <code>VERSATILEPB_SIC_PICENSET = $20;</code>
 +
| &nbsp;
 +
|-
 +
| <code>VERSATILEPB_SIC_PICENCLR = $24;</code>
 +
| Set bits HIGH to clear the corresponding interrupt pass-through mask bits (Write)
 +
|-
 +
|colspan="2"|&nbsp;
 +
|-
 +
|colspan="2"|VersatilePB Secondary Interrupt Controller register bits (See: http://infocenter.arm.com/help/topic/com.arm.doc.dui0224i/Cacdggia.html)
 +
|-
 +
| <code>VERSATILEPB_SIC_PIC_MASK = $7FE00000;</code>
 +
| Interrupts on secondary controller from 21 to 30 are routed directly to the VIC on the corresponding number on primary controller
 +
|-
 +
|}
 +
</div></div>
 +
<br />
  
 
=== Type definitions ===
 
=== Type definitions ===

Revision as of 03:48, 26 April 2017

Return to Unit Reference


Description

From the QEMU source the memory map of the VersatilePB is shown as this:

Memory map for Versatile/PB:

  • 0x10000000 System registers
  • 0x10001000 PCI controller config registers
  • 0x10002000 Serial bus interface
  • 0x10003000 Secondary interrupt controller
  • 0x10004000 AACI (audio)
  • 0x10005000 MMCI0
  • 0x10006000 KMI0 (keyboard)
  • 0x10007000 KMI1 (mouse)
  • 0x10008000 Character LCD Interface
  • 0x10009000 UART3
  • 0x1000a000 Smart card 1
  • 0x1000b000 MMCI1
  • 0x10010000 Ethernet
  • 0x10020000 USB
  • 0x10100000 SSMC
  • 0x10110000 MPMC
  • 0x10120000 CLCD Controller
  • 0x10130000 DMA Controller
  • 0x10140000 Vectored interrupt controller
  • 0x101d0000 AHB Monitor Interface
  • 0x101e0000 System Controller
  • 0x101e1000 Watchdog Interface
  • 0x101e2000 Timer 0/1
  • 0x101e3000 Timer 2/3
  • 0x101e4000 GPIO port 0
  • 0x101e5000 GPIO port 1
  • 0x101e6000 GPIO port 2
  • 0x101e7000 GPIO port 3
  • 0x101e8000 RTC
  • 0x101f0000 Smart card 0
  • 0x101f1000 UART0
  • 0x101f2000 UART1
  • 0x101f3000 UART2
  • 0x101f4000 SSPI
  • 0x34000000 NOR Flash

Constants


[Expand]
VersatilePB specific constants VERSATILEPB_*


[Expand]
VersatilePB IRQ VERSATILEPB_IRQ_*


[Expand]
VersatilePB IRQ count VERSATILEPB_*_IRQ_COUNT*


[Expand]
VersatilePB FIQ count VERSATILEPB_FIQ_COUNT*


[Expand]
VersatilePB timer frequency VERSATILEPB_TIMER_FREQUENCY*


[Expand]
VersatilePB system register VERSATILEPB_SYS_*


[Expand]
VersatilePB system control VERSATILEPB_SYSCTRL_*


[Expand]
SP804 timer SP804_TIMER_*


[Expand]
SP804 timer control SP804_TIMER_CONTROL_*


[Expand]
PL190 vectored interrupt controller offsets PL190_VIC_*


[Expand]
PL190 vectored interrupt controller register PL190_VIC_VECTCNTL_*


[Expand]
VersatilePB secondary interrupt controller VERSATILEPB_SIC_*


Type definitions

To be documented

Public variables

To be documented

Function declarations

To be documented


Return to Unit Reference

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