fpga for ultitb

The place to share and discuss your Ultibo projects.
develone
Posts: 303
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Sat Dec 22, 2018 12:25 pm

Hello All,
pik33 asked What is in the picture? It looks like wavelet compressed something: )


In a 256 x 256 image of lena has 3 sub bands. RGB. The first step of JPEG 2000 is to perform DWT The picture is 3 levels of lifting step on the red sub band.
1 level reduces the image to 128 X 128 at the same quality if you include the other pixels. The 2nd level reduces to 64 X 64 and the 3rd level is 32 X 32 in the
lower right hand corner. The next step would be EBCOT (Embedded Block Coding with Optimized Truncation). https://github.com/develone/Ultibo_Proj ... r/jpeg2000
is the complete openjpeg. This work is just learning FPGA in hopes of combining with Ultibo. https://github.com/develone/Ultibo_Proj ... er/progcat.
The RPi3B+ is complete Development tool in the palm of your hand. The combination of the FPGA with Ultibo provides the logic level to control any number of devices.
Let me if you have any questions
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develone
Posts: 303
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Sun Jan 06, 2019 9:34 pm

One thing to keep in mind when working with SOC is if the cpu has been formally verified. Since ZipCPU just updated .https://github.com/develone/zipcpu
I have been updating and testing https://github.com/develone/catzip. He recently tweeted the item below I wanted to share with ultibo forum.
Zip CPU


@zipcpu
27 Dec 2018
More
A common question among new readers of this blog seems to be, "What is formal verification"?
Here's a quick chart that outlines several of the major differences
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Gavinmc42
Posts: 1595
Joined: Sun Jun 05, 2016 12:38 pm
Location: Brisbane, Australia

Re: fpga for ultitb

Postby Gavinmc42 » Mon Jan 07, 2019 6:00 am

Turns out FPGA's can be low power too, must have been a long time since I checked.
This one looks interesting, apparently 5.3K LUTs is enough for a RISC-V micro too.
http://www.latticesemi.com/en/Products/ ... imaxHM01B0
It can do vision recog :o

This FPGA is the UP5K used on the UPDuino's
It is supported by Icestudio.
https://github.com/FPGAwars
develone
Posts: 303
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Fri Feb 15, 2019 3:24 pm

Hello All,
This would be a great addition to Ultibo to combine the Lattice ECP5 with RPi3B+.
I recently changed from using arachne-pnr to nextpnr-ice40. There is a great presentation by David S
https://ftp.osuosl.org/pub/fosdem/2019/AW1.125/trellis_and_nextpnr.mp4 by David Shah. This is the tool
that lets you place & route for the Lattice ECP5 FPGA which provides FPGAs a Up to 85K LUTs Up to 3.2 Gbps
SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G, 156 18 x 18 Multipliers for DSP. With Yosys & Nextpnr
a complete open source tool set allow developing application. There are a few development boards TinyFPGA EX
https://www.crowdsupply.com/tinyfpga/tinyfpga-ex Let me if I can provide additional informaition
develone
Posts: 303
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Sun Mar 10, 2019 10:53 pm

Hello All,
Now the verilator simulator works for the catzip repository.

cputest & hello work okay in simulator. in hw jpeg and cputest & hello work okay.

git clone https://github.com/develone/catzip.git

cd catzip

Running the top make creates several bin files which can be installed
in the FPGA.
./rtl/catzip/catzip.bin
./rtl/basic/blinky.bin
./rtl/basic/pmodtest.bin not tested
./rtl/basic/clktest.bin
./rtl/basic/dimmer.bin
./rtl/pptest/hellopp.bin
./rtl/pptest/linepp.bin not tested
Test the parallel interface writing the Gettysburg address on the RPi3B
./rtl/pptest/speechpp.bin
./rtl/uart/helloworld.bin
./rtl/uart/speechfifo.bin not working correctly
./rtl/leddigits/leddigits.bin
./rtl/switch_leds/switch_leds.bin

make requires icestorm, arachne-pnr, yosys, and verilator.

arachne-pnr 5d830d https://github.com/develone/arachne-pnr.git

icestorm 8cac6c https://github.com/develone/icestorm.git

yosys e27569 https://github.com/develone/yosys.git

verilator c8e437 http://git.veripool.org/git/verilator

gtkwave v3.3.79

Simulationg steps
make datestamp
make autodata
cd rtl/catzip
make cpudefs.h
make design.h

make verilated
Create the software that communicates with the FPGA from RPi3B+
cd ../../sw/host
make
Create the libcatzip.a that are required by hello & jpeg
cd ../zlib
make
Create the C programs that execute on ZipCPU cputest, hello, and jpeg
cd ../board
make
Create arm-main_tb verilator simulation
cd ../sim/verilated
make

cputest & hello work okay in simulator. in hw jpeg and cputest & hello work okay.

In on shell execute sim/verilated ./arm-main_tb -d to create the file trace.vcd
In a 2nd shell execute ./jpeg.sh or cputest_hello.sh
This is my largest vcd file ever created requres gtkwave -g trace.vcd
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