fpga for ultitb

The place to share and discuss your Ultibo projects.
Posts: 283
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Sat Dec 22, 2018 12:25 pm

Hello All,
pik33 asked What is in the picture? It looks like wavelet compressed something: )

In a 256 x 256 image of lena has 3 sub bands. RGB. The first step of JPEG 2000 is to perform DWT The picture is 3 levels of lifting step on the red sub band.
1 level reduces the image to 128 X 128 at the same quality if you include the other pixels. The 2nd level reduces to 64 X 64 and the 3rd level is 32 X 32 in the
lower right hand corner. The next step would be EBCOT (Embedded Block Coding with Optimized Truncation). https://github.com/develone/Ultibo_Proj ... r/jpeg2000
is the complete openjpeg. This work is just learning FPGA in hopes of combining with Ultibo. https://github.com/develone/Ultibo_Proj ... er/progcat.
The RPi3B+ is complete Development tool in the palm of your hand. The combination of the FPGA with Ultibo provides the logic level to control any number of devices.
Let me if you have any questions
red.png (92.79 KiB) Viewed 147 times
Posts: 283
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Sun Jan 06, 2019 9:34 pm

One thing to keep in mind when working with SOC is if the cpu has been formally verified. Since ZipCPU just updated .https://github.com/develone/zipcpu
I have been updating and testing https://github.com/develone/catzip. He recently tweeted the item below I wanted to share with ultibo forum.

27 Dec 2018
A common question among new readers of this blog seems to be, "What is formal verification"?
Here's a quick chart that outlines several of the major differences
formal.png (257.47 KiB) Viewed 62 times
Posts: 1436
Joined: Sun Jun 05, 2016 12:38 pm
Location: Brisbane, Australia

Re: fpga for ultitb

Postby Gavinmc42 » Mon Jan 07, 2019 6:00 am

Turns out FPGA's can be low power too, must have been a long time since I checked.
This one looks interesting, apparently 5.3K LUTs is enough for a RISC-V micro too.
http://www.latticesemi.com/en/Products/ ... imaxHM01B0
It can do vision recog :o

This FPGA is the UP5K used on the UPDuino's
It is supported by Icestudio.

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