fpga for ultitb

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develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jun 21, 2018 8:26 pm

It appears that Dave is making progess on the new catboard.

https://hackaday.io/project/7982-cat-board


He is the author of skidl
https://github.com/xesscorp/skidl
develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jun 21, 2018 10:35 pm

develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Fri Jun 22, 2018 3:36 pm

This skidl appears to be a good pcb tool. I was able to this on my ubuntu 16.04
https://github.com/develone/raspbian-pi-gen/blob/master/catboard_kicad/skidized/skid.png

this is kind of the same as logic using net list to design the parts.
This is the last post by Dave on hackaday.
These are the steps that I used
https://github.com/develone/raspbian-pi-gen/blob/master/catboard_kicad/skidized/kicad5.txt
develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jul 12, 2018 7:42 pm

this taking 57 Verilog files about 1K lines and converts it to C.

I just was able to get the simulator built and starts to running using Verilator. Verilator converts Verilog into C and which is suppose to be faster than other simulators.
these are the steps that I used.

07/12/18
cd catziptestbuild/

git clone https://github.com/develone/catzip.git

cd catzip

. ./myenv.sh sets VERILATOR_ROOT & PATH

make datestamp

modify catzip/auto-data/bkram.txt by applying the patchbkram

-#define block_ram @$(VERILATOR_PREFIX)__DOT__@$(PREFIX)i__DOT__mem
+#define block_ram VVAR(_bkrami__DOT__mem)

cd auto-data

patch < patchbkram

patching file bkram.txt

cd ../

make autodata
Creates catzip/sim/verilated/main_tb.cpp with
change made in catzip/auto-data/bkram.txt.


cd rtl/catzip/

make
// Timing estimate: 16.76 ns (59.68 MHz)
// Checking 25.00 ns (40.00 MHz) clock constraint: PASSED.

Creates catzip.bin used to program HX8K FPGA
Creates cpudefs.h design.h used by catzip/sim/verilated/

cd ../../sim/verilated

patch < patchtestb

patching file testb.h

make

-rwxr-xr-x 1 pi pi 1336392 Jul 12 17:40 arm-main_tb

./arm-main_tb
Listening on port 8363
Listening on port 8364

pi@mypi3-4:~ $ cd catzip/sw/host/

pi@mypi3-4:~/catzip/sw/host $ ./arm-wbregs version
00000610 ( VERSION) : [....] 20180712
Accepted CMD connection
POLL = 1
RCVD: 6 bytes
< A611R
> A00000611R20180712
POLL = 1
RCVD: 0 bytes
< [CLOSED]
pi@mypi3-4:~/catzip/sw/host $ ./arm-wbregs gpio 0x00070000
00000608 ( GPIO)-> 00070000

Accepted CMD connection
POLL = 1
RCVD: 11 bytes
< A609W70000
> A00000609K00000000
POLL = 1
RCVD: 0 bytes
< [CLOSED]
This lets learn Verilog with out the Hardware.
This also works with https://github.com/develone/wbuart32 and provides VCD files.
Let me know if you have any questions.
develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Wed Jul 18, 2018 8:02 pm

Just was able to get the dspfilters repo
https://github.com/develone/dspfilters
to build and run on the RPi.
This was done with the authors Dan Gisselquist help.
His blog is
http://zipcpu.com/dsp/2017/10/16/boxcar.html


I have verilator installed using apt-get and a new version from
http://git.veripool.org/git/verilator ver commit f0ed4346b2e13a. This was built but not installed.
I also have zipcpu built https://github.com/develone/zipcpu.git ver commit ab82a886305
git

cd dspfilters

Before trying to build I run

Code: Select all

#!/bin/bash
export VERILATOR_ROOT=~/verilator
echo $VERILATOR_ROOT
export PATH=~/verilator/bin:~/zipcpu/sw/install/cross-tools/bin:$PATH
echo $PATH

to set the PATH & VERILATOR_ROOT.

make
The test benches will be in bench/cpp folder.

This is the set of filters
boxcar_tb
delayw_tb
fastfir_tb
genericfir_tb
lfsr_fib_tb
lfsr_gal_tb
lfsr_tb
shalfband_tb
slowfil_tb
slowsymf_tb

These are the Verilog files that are being simulated found in the rtl folder.
boxcar.v fastfir.v iiravg.v lfsr.v shalfband.v smplfir.v
delayw.v firtap.v lfsr_fib.v Makefile slowfil.v
dspswitch.v genericfir.v lfsr_gal.v slowsymf.v
Verilator converts the Verilog to C for the simulation.
These are the VCD files created by running the tb.
boxcar.vcd delayw.vcd lfsr_fib.vcd lfsr_gal.vcd lfsr.vcd trace.vcd
The runs were also captured, in the file, https://gist.github.com/develone/368def ... esults-txt
If you have any questions let me know I am glad to help.
develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Mon Aug 06, 2018 4:25 pm

This work is thanks Dan Gisselquist, Clifford Wolf, Dave Vandenbout, Chris Felton and others.

Getting closer on the CATBOARD and working on ICOBOARD.
The simulator is now working for ICOBOARD, Once the SDRAM is included it should be working
The ICOBOARD has an SRAM 128KB and the CATBOARD has SDRAM 4M X 4 banks X 16 words
Two programs cputests & helloword were compiled using the the compiler for the ZiPCPU.
*http://git.veripool.org/git/verilator
** https://github.com/develone/ forks
- RPi3B+
- Software versions as 08/06/18
- MyHDL 160719dd **
- yosys e275692e **
- icestorm 45822021 **
- arachne-pnr 5d830dd9 **
- icozip 9dcbacfe **
- autofpga 2f443503 **
- zipcpu ab82a886 **
- verllator f0ed4346 *

In 1st shell pull the forked software from github

git clone https://github.com/develone/icozip.git

cd icozip

make Creates several bin files that can be load on an icoboard gamma ver,

icozip/rtl/icozip/icozip.bin
icozip/rtl/basic/clktest.bin
icozip/rtl/basic/blinky.bin
icozip/rtl/basic/pmodtest.bin
icozip/rtl/basic/dimmer.bin
icozip/rtl/uart/helloworld.bin
icozip/rtl/uart/speechfifo.bin

icozip/sim/verilated/arm-main_tb Creates the verilated simulation of the FPGA




Creates utilities

icozip/sw/host/arm-dbgscope
icozip/sw/host/arm-dumpflash
icozip/sw/host/arm-flashid
icozip/sw/host/arm-netpport
icozip/sw/host/arm-spixscope
icozip/icozip/sw/host/arm-sramscope
icozip/sw/host/arm-wbregs
icozip/sw/host/arm-zipdbg
icozip/sw/host/arm-zipload
icozip/sw/host/arm-zipstate

In 2nd shell Start the simululator
icozip/sim/verilated $ ./arm-main_tb
Listening on port 8363
Listening on port 8364

In a 3rd shell
./arm-wbregs version
00a00010 ( VERSION) : [....] 20180806

./arm-zipload ../board/hello
./arm-wbregs cpu 0x0f

In 2nd shell
Hello, World!
.

./arm-zipload ../board/cputest
./arm-wbregs cpu 0x0f

In 2nd shell
https://gist.github.com/develone/61051014227ac28e9517579f10f0531b


zip-objdump -d ../board/cputest

https://gist.github.com/develone/d6923fcdd20f316825e0180f772cfd8e#file-dis_cputest-txt


zip-objdump -d ../board/hello
https://gist.github.com/develone/d6923fcdd20f316825e0180f772cfd8e#file-dis_hello.txt


./arm-zipstate
0x00000600: HALTED
develone
Posts: 272
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Wed Aug 15, 2018 2:39 pm

Hello All,
This tinyfpga is the same fpga as my catboard but this one is low power. ZipCPU has the SOC working for the tinyfpga

https://github.com/develone/tinyzip.git this is a fork of https://github.com/ZipCPU/tinyzip

The BX is selling for $38.
I am working on https://github.com/develone/sdram_tests.git with MyHdL
sdram_tests/sdram_noled/sdram/sdram_test_rxtx/sdram_test.py which has sdram controller and echo using the UART.
Attachments
tinyfpga_a.png
tinyfpga_a.png (68.67 KiB) Viewed 115 times
tinyfpga.png
tinyfpga.png (118.75 KiB) Viewed 115 times

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