fpga for ultitb

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develone
Posts: 267
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jun 21, 2018 8:26 pm

It appears that Dave is making progess on the new catboard.

https://hackaday.io/project/7982-cat-board


He is the author of skidl
https://github.com/xesscorp/skidl
develone
Posts: 267
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jun 21, 2018 10:35 pm

develone
Posts: 267
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Fri Jun 22, 2018 3:36 pm

This skidl appears to be a good pcb tool. I was able to this on my ubuntu 16.04
https://github.com/develone/raspbian-pi-gen/blob/master/catboard_kicad/skidized/skid.png

this is kind of the same as logic using net list to design the parts.
This is the last post by Dave on hackaday.
These are the steps that I used
https://github.com/develone/raspbian-pi-gen/blob/master/catboard_kicad/skidized/kicad5.txt
develone
Posts: 267
Joined: Wed Dec 28, 2016 7:40 pm
Location: El Paso Tx USA

Re: fpga for ultitb

Postby develone » Thu Jul 12, 2018 7:42 pm

this taking 57 Verilog files about 1K lines and converts it to C.

I just was able to get the simulator built and starts to running using Verilator. Verilator converts Verilog into C and which is suppose to be faster than other simulators.
these are the steps that I used.

07/12/18
cd catziptestbuild/

git clone https://github.com/develone/catzip.git

cd catzip

. ./myenv.sh sets VERILATOR_ROOT & PATH

make datestamp

modify catzip/auto-data/bkram.txt by applying the patchbkram

-#define block_ram @$(VERILATOR_PREFIX)__DOT__@$(PREFIX)i__DOT__mem
+#define block_ram VVAR(_bkrami__DOT__mem)

cd auto-data

patch < patchbkram

patching file bkram.txt

cd ../

make autodata
Creates catzip/sim/verilated/main_tb.cpp with
change made in catzip/auto-data/bkram.txt.


cd rtl/catzip/

make
// Timing estimate: 16.76 ns (59.68 MHz)
// Checking 25.00 ns (40.00 MHz) clock constraint: PASSED.

Creates catzip.bin used to program HX8K FPGA
Creates cpudefs.h design.h used by catzip/sim/verilated/

cd ../../sim/verilated

patch < patchtestb

patching file testb.h

make

-rwxr-xr-x 1 pi pi 1336392 Jul 12 17:40 arm-main_tb

./arm-main_tb
Listening on port 8363
Listening on port 8364

pi@mypi3-4:~ $ cd catzip/sw/host/

pi@mypi3-4:~/catzip/sw/host $ ./arm-wbregs version
00000610 ( VERSION) : [....] 20180712
Accepted CMD connection
POLL = 1
RCVD: 6 bytes
< A611R
> A00000611R20180712
POLL = 1
RCVD: 0 bytes
< [CLOSED]
pi@mypi3-4:~/catzip/sw/host $ ./arm-wbregs gpio 0x00070000
00000608 ( GPIO)-> 00070000

Accepted CMD connection
POLL = 1
RCVD: 11 bytes
< A609W70000
> A00000609K00000000
POLL = 1
RCVD: 0 bytes
< [CLOSED]
This lets learn Verilog with out the Hardware.
This also works with https://github.com/develone/wbuart32 and provides VCD files.
Let me know if you have any questions.

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