Propeller CPU connected to Ultibo/pi

General discussion about anything related to Ultibo.
mark
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Location: Indianapolis, US

Re: Propeller CPU connected to Ultibo/pi

Postby mark » Sat Feb 17, 2018 6:37 pm

I think it does:

Code: Select all

function FTDISerialSetModemControl(Serial:PFTDISerialDevice;Value:Word):LongWord;

                                                                                                                                                                                     
 {FTDI Serial set modem control constants (ftdi_sio.h)}                                        {wValue: ControlValue}
 FTDISERIAL_SET_MODEM_CTRL_DTR_ENABLE = 1;                                                     { B0    DTR state (0 = reset / 1 = set)}
 FTDISERIAL_SET_MODEM_CTRL_DTR_HIGH   = (1 or (FTDISERIAL_SET_MODEM_CTRL_DTR_ENABLE  shl 8));  { B1    RTS state (0 = reset / 1 = set)}
 FTDISERIAL_SET_MODEM_CTRL_DTR_LOW    = (0 or (FTDISERIAL_SET_MODEM_CTRL_DTR_ENABLE  shl 8));  { B2..7 Reserved}
 FTDISERIAL_SET_MODEM_CTRL_RTS_ENABLE = 2;                                                     { B8    DTR state enable (0 = ignore / 1 = use DTR state)}
 FTDISERIAL_SET_MODEM_CTRL_RTS_HIGH   = (2 or (FTDISERIAL_SET_MODEM_CTRL_RTS_ENABLE shl 8));   { B9    RTS state enable (0 = ignore / 1 = use RTS state)}
 FTDISERIAL_SET_MODEM_CTRL_RTS_LOW    = (0 or (FTDISERIAL_SET_MODEM_CTRL_RTS_ENABLE shl 8));   { B10..15 Reserved}


pik33 wrote:Now, the question is: does Ultibo support this:

Code: Select all

  // generate reset pulse via dtr and wait 100ms
  EscapeCommFunction(CommHandle, SETDTR);
  DelayMilliseconds(25);
  EscapeCommFunction(CommHandle, CLRDTR);


using FTDI chip?

This is the most important question as DTR signal is used as standard way to reset the Propeller. If it is supported, then we can reset the Propeller and upload anything we want to it via com port on USB and then USB will be sufficient to make the conection. After the loading is done, the propeller can talk to pi via uart which should be sufficient for most tasks.
Last edited by mark on Mon Feb 19, 2018 9:11 am, edited 1 time in total.
pik33
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Re: Propeller CPU connected to Ultibo/pi

Postby pik33 » Sat Feb 17, 2018 6:39 pm

My project is not easily movable from DE2-115 as it uses its resources other than FPGA (SRAM and SDRAM). But then, the Propeller alone should be used on non-Altera boards. I recommend to search the Propeller forum. There are people with different FPGA boards who used P1V so maybe you can find ready made source modified for use with your FPGA flavor.

Here is my source: http://forums.parallax.com/discussion/d ... 8b.src.zip

Here are search results:

http://forums.parallax.com/search?Search=p1v
Last edited by pik33 on Sat Feb 17, 2018 6:51 pm, edited 1 time in total.
pik33
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Re: Propeller CPU connected to Ultibo/pi

Postby pik33 » Sat Feb 17, 2018 6:45 pm

I think it does:


So there is a good chance we can program the Quickstart board from Ultibo program using USB connection. As many precompiled Propeller programs for functions we need can be stored on SD and sent to the Propeller when needed. Also the Propeller can communicate with Ultibo using com port over USB. This can simplify a lot of things.

The OpenSpin compiler is opensource C++ (? - these are cpp files but what is inside looks like pure C) project so this may be translated to Pascal... It was written in Pascal first (!) but then translated to C... I will try to find or request on the forum original Pascal code of it
captbill
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Re: Propeller CPU connected to Ultibo/pi

Postby captbill » Sat Feb 17, 2018 8:04 pm

pik33 wrote:My project is not easily movable from DE2-115 as it uses its resources other than FPGA (SRAM and SDRAM). But then, the Propeller alone should be used on non-Altera boards. I recommend to search the Propeller forum. There are people with different FPGA boards who used P1V so maybe you can find ready made source modified for use with your FPGA flavor.

Here is my source: http://forums.parallax.com/discussion/d ... 8b.src.zip

Here are search results:

http://forums.parallax.com/search?Search=p1v


Hmmm... The Pipistrello and the Pepino have up to 2mb of high speed SRAM. Plus, they utilize the FTD2232h high speed USB interface chip. But most importantly, we have Mr. Magnus Karlsson, FPGA programmer extraordinaire, who seems to do these things for fun. I bet he would have it up and spinning in no time on the Pipistrello.

I think you will search long and hard to find an FPGA development board of the caliber of any of Magnus' offerings anywhere. In fact, there are only two reasonable alternatives to even consider to fill our needs... the Gadget Factory boards and Magnus' offerings (Saanlima.com). Think of the Pipistrello as the highest end board (which will most suit the Propeller, I am thinking), the Pepino as the Pipistrello's little brother, and the Gadget Factory boards as great entry level boards.

http://store.gadgetfactory.net/

http://www.saanlima.com/store/
pik33
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Re: Propeller CPU connected to Ultibo/pi

Postby pik33 » Sat Feb 17, 2018 9:05 pm

captbill
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Re: Propeller CPU connected to Ultibo/pi

Postby captbill » Sat Feb 17, 2018 9:18 pm

pik33 wrote:http://forum.gadgetfactory.net/topic/2083-propeller-1-running-on-pipistrello/


Hahaha... I went to download it only to find out it has been in my projects directory for over two years. Good thing it wasn't a snake!

It compiles beautifully:

Code: Select all

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------------------------------------------+--------------------------------------------------+-------+
Clock Signal                                                           | Clock buffer(FF name)                            | Load  |
-----------------------------------------------------------------------+--------------------------------------------------+-------+
PLL/CLKOUT0                                                            | BUFG                                             | 43    |
clk_pll(Mmux_clk_pll1:O)                                               | BUFG(*)(core/coggen[7].cog_/cog_ctra/pll_fake_35)| 576   |
divide_12                                                              | BUFG                                             | 3957  |
core/coggen[0].cog_/cog_vid_/vclk(core/coggen[0].cog_/cog_vid_/vclk1:O)| BUFG(*)(core/coggen[0].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[1].cog_/cog_vid_/vclk(core/coggen[1].cog_/cog_vid_/vclk1:O)| BUFG(*)(core/coggen[1].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[2].cog_/cog_vid_/vclk(core/coggen[2].cog_/cog_vid_/vclk1:O)| BUFG(*)(core/coggen[2].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[3].cog_/cog_vid_/vclk(core/coggen[3].cog_/cog_vid_/vclk1:O)| BUFG(*)(core/coggen[3].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[4].cog_/cog_vid_/vclk(core/coggen[4].cog_/cog_vid_/vclk1:O)| BUFG(*)(core/coggen[4].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[5].cog_/cog_vid_/vclk(core/coggen[5].cog_/cog_vid_/vclk1:O)| NONE(*)(core/coggen[5].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[6].cog_/cog_vid_/vclk(core/coggen[6].cog_/cog_vid_/vclk1:O)| NONE(*)(core/coggen[6].cog_/cog_vid_/phase_3)    | 112   |
core/coggen[7].cog_/cog_vid_/vclk(core/coggen[7].cog_/cog_vid_/vclk1:O)| NONE(*)(core/coggen[7].cog_/cog_vid_/phase_3)    | 112   |
-----------------------------------------------------------------------+--------------------------------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 9.809ns (Maximum Frequency: 101.951MHz)
   Minimum input arrival time before clock: 8.346ns
   Maximum output required time after clock: 12.325ns
   Maximum combinational path delay: 5.326ns

=========================================================================

Process "Synthesize - XST" completed successfully
captbill
Posts: 70
Joined: Tue Aug 16, 2016 5:47 am

Re: Propeller CPU connected to Ultibo/pi

Postby captbill » Sat Feb 17, 2018 9:42 pm

Here is the full 'map report' from ISE:

Code: Select all

Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o top_map.ncd top.ngd top.pcf
Target Device  : xc6slx45
Target Package : csg324
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Sat Feb 17 16:33:27 2018

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Slice Logic Utilization:
  Number of Slice Registers:                 5,456 out of  54,576    9%
    Number used as Flip Flops:               5,432
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:               24
  Number of Slice LUTs:                      9,844 out of  27,288   36%
    Number used as logic:                    9,723 out of  27,288   35%
      Number using O6 output only:           8,599
      Number using O5 output only:             147
      Number using O5 and O6:                  977
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   6,408    0%
    Number used exclusively as route-thrus:    121
      Number with same-slice register load:     95
      Number with same-slice carry load:        26
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 3,523 out of   6,822   51%
  Number of MUXCYs used:                     1,768 out of  13,644   12%
  Number of LUT Flip Flop pairs used:       11,146
    Number with an unused Flip Flop:         6,091 out of  11,146   54%
    Number with an unused LUT:               1,302 out of  11,146   11%
    Number of fully used LUT-FF pairs:       3,753 out of  11,146   33%
    Number of unique control sets:             245
    Number of slice register sites lost
      to control set restrictions:           1,040 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        46 out of     218   21%
    Number of LOCed IOBs:                       46 out of      46  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                        40 out of     116   34%
  Number of RAMB8BWERs:                          0 out of     232    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       8 out of      16   50%
    Number used as BUFGs:                        8
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       4   25%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                4.21

Peak Memory Usage:  587 MB
Total REAL time to MAP completion:  1 mins 54 secs
Total CPU time to MAP completion:   1 mins 52 secs

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   core/coggen[6].cog_/cog_vid_/vclk is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   core/coggen[7].cog_/cog_vid_/vclk is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   core/coggen[5].cog_/cog_vid_/vclk is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.

Section 3 - Informational
-------------------------
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_LOCWARN    Value: 1
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
   1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE       BLOCK
GND       XST_GND
VCC       XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| clock_50                           | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| dtr                                | IOB              | INPUT     | LVCMOS33             |       |          |      |              |          |          |
| ledg<0>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<1>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<2>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<3>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<4>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<5>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<6>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| ledg<7>                            | IOB              | OUTPUT    | LVCMOS33             |       | 12       | SLOW |              |          |          |
| p16_led                            | IOB              | OUTPUT    | LVCMOS33             |       | 8        | SLOW |              |          |          |
| p17_led                            | IOB              | OUTPUT    | LVCMOS33             |       | 8        | SLOW |              |          |          |
| pin<0>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<1>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<2>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<3>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<4>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<5>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<6>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<7>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<8>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<9>                             | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<10>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<11>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<12>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<13>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<14>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<15>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<16>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<17>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<18>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<19>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<20>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<21>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<22>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<23>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<24>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<25>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<26>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<27>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<28>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              | PULLUP   |          |
| pin<29>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              | PULLUP   |          |
| pin<30>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| pin<31>                            | IOB              | BIDIR     | LVCMOS33             |       | 12       | SLOW |              |          |          |
| rx_led                             | IOB              | OUTPUT    | LVCMOS33             |       | 8        | SLOW |              |          |          |
| tx_led                             | IOB              | OUTPUT    | LVCMOS33             |       | 8        | SLOW |              |          |          |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.

For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.

Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
Gavinmc42
Posts: 1460
Joined: Sun Jun 05, 2016 12:38 pm
Location: Brisbane, Australia

Re: Propeller CPU connected to Ultibo/pi

Postby Gavinmc42 » Sun Feb 18, 2018 8:31 am

Was looking for some MQTT free pascal source and found this.
https://github.com/ZiCog?tab=repositories
Zicog has some Pi to propeller loader code, in C but maybe of some use to those that can figure it out ;)
mark
Posts: 1319
Joined: Mon Oct 03, 2016 2:12 am
Location: Indianapolis, US

Re: Propeller CPU connected to Ultibo/pi

Postby mark » Mon Feb 19, 2018 11:28 am

Piotr, are you going to translate this or should I start it? Mark
pik33 wrote:
I found this pascal unit to communicate with the Propeller including resetting it by DTR pulse. To be translated to Ultibo:

Code: Select all

unit SerialUnit;

interface

uses
  SysUtils, WinTypes, WinProcs, Classes, Forms, Messages, Dialogs, ExtCtrls, Graphics;

  procedure        TalkToHardware(LongCount: integer; Command: byte);
  procedure        GetHardwareVersion;
  procedure        FindAnyHardware;
  function         HardwareFound: boolean;
  procedure        ResetHardware;
  procedure        OpenComm;
  procedure        TLong(x: cardinal);
  procedure        TByte(x: byte);
  procedure        TComm;
  function         RBit(Echo: boolean; Timeout: integer): byte;
  procedure        RComm;
  procedure        CloseComm;
  procedure        HardwareLostError;
  procedure        CommError(Msg: string);
  function         CommString: string;
  procedure        DelayMilliseconds(ms: cardinal);
  function         IterateLFSR: byte;

const
  TxBuffSize         = 256;
  RxBuffSize         = 256;

var
  CommPort           : integer;
  CommOpen           : boolean;
  CommHandle         : THandle;
  CommDCB            : TDCB;

  TxBuffLength       : cardinal;
  TxBuff             : array[0..TxBuffSize-1] of byte;
  RxBuffStart        : cardinal;
  RxBuffEnd          : cardinal;
  RxBuff             : array[0..RxBuffSize-1] of byte;

  LFSR               : byte;

  Version            : byte;
  VersionMode        : boolean;
  AbortMode          : boolean;

  LongCount          : integer;

implementation

uses GlobalUnit, ProgressUnit;

/////////////////////
//  Chip Routines  //
/////////////////////

// Talk to hardware
procedure TalkToHardware(LongCount: integer; Command: byte);
var
  i: integer;
begin
  // find hardware
  VersionMode := False;
  FindAnyHardware;
     //check version here
  // send command
  TLong(Command);
  TComm;
  // if command 1-3, do the following
  if Command > 0 then
  begin
    // update progress form
    ProgressForm.StatusLabel.Caption := 'Loading RAM';
    ProgressForm.StatusLabel.Repaint;
    // send count and longs
    TLong(LongCount);
    for i := 0 to LongCount-1 do TLong(PIntegerArray(@MemoryBuffer)[i]);
    TComm;
    // update progress form
    ProgressForm.StatusLabel.Caption := 'Verifying RAM';
    ProgressForm.StatusLabel.Repaint;
    // receive ram checksum pass/fail
    if RBit(True, 2500) = 1 then CommError('RAM checksum error on');
    // if command 2-3, do the following
    if Command > 1 then
    begin
      // update progress form
      ProgressForm.StatusLabel.Caption := 'Programming EEPROM';
      ProgressForm.StatusLabel.Repaint;
      // receive eeprom program pass/fail
      if RBit(True, 5000) = 1 then CommError('EEPROM programming error on');
      // update progress form
      ProgressForm.StatusLabel.Caption := 'Verifying EEPROM';
      ProgressForm.StatusLabel.Repaint;
      // receive eeprom verify pass/fail
      if RBit(True, 2500) = 1 then CommError('EEPROM verify error on');
    end;
  end;
  CloseComm;
  ProgressForm.Hide;
end;

// Get hardware version
procedure GetHardwareVersion;
begin
  VersionMode := True;
  FindAnyHardware;
  ProgressForm.Hide;
  MessageDlg(('Hardware version ' + IntToStr(Version) + ' found on ' + CommString + '.'), mtInformation, [mbOK], 0);
end;

// Check for hardware on current comm port, then on com9..com1
procedure FindAnyHardware;
var
  i, FirstPort: integer;
begin
  // show progress form
  ProgressForm.Caption := 'Hardware';
  ProgressForm.StatusLabel.Caption := '';
  ProgressForm.Show;
  // check com9..com1 for hardware
  FirstPort := CommPort;
  for i := 10 downto 1 do
  begin
    if i <> 10 then CommPort := i;
    if (i = 10) or (i <> FirstPort) then
    begin
      ProgressForm.StatusLabel.Caption := 'Checking ' + CommString;
      ProgressForm.StatusLabel.Repaint;
      if HardwareFound then Exit;
    end;
  end;
  CommPort := 9;
  CommError('No hardware found on COM1 through');
end;

// Check for hardware on current comm port
function HardwareFound: boolean;
var
  i: integer;
begin
  try
    // in case error, result is false
    Result := False;
    // disallow abort
    AbortMode := False;
    // check hardware
    OpenComm;
    // do reset and send connect string + blanks for echoes
    ResetHardware;
    TByte($F9);
    LFSR := Byte('P');
    for i := 1 to 250 do TByte(IterateLFSR or $FE);
    for i := 1 to 250 + 8 do TByte($F9);
    TComm;
    // receive connect string
    for i := 1 to 250 do if RBit(False, 100) <> IterateLFSR then HardwareLostError;
    // receive version
    for i := 1 to 8 do Version := Version shr 1 and $7F or RBit(False, 50) shl 7;
    // if find hardware mode, send shutdown command and reset hardware to reboot
    if VersionMode then
    begin
      TLong(0);
      TComm;
      ResetHardware;
      CloseComm;
    end;
    // allow abort
    AbortMode := True;
    // connected, result is true
    Result := True;
  except
    // error, result is false, allow abort
    on EAbort do AbortMode := True;
  end;
end;

// Reset hardware
procedure ResetHardware;
begin
  // generate reset pulse via dtr and wait 100ms
  EscapeCommFunction(CommHandle, SETDTR);
  DelayMilliseconds(25);
  EscapeCommFunction(CommHandle, CLRDTR);
  DelayMilliseconds(100-10); //TEST - was 100
  // flush any previously-received bytes and clear any break
  PurgeComm(CommHandle, PURGE_RXCLEAR);
end;

/////////////////////
//  Comm Routines  //
/////////////////////

// Open comm port
procedure OpenComm;
const
  CommTimeouts: TCOMMTIMEOUTS = (
    ReadIntervalTimeout: MAXDWORD;
    ReadTotalTimeoutMultiplier: 0;
    ReadTotalTimeoutConstant: 0;
    WriteTotalTimeoutMultiplier: 0;
    WriteTotalTimeoutConstant: 0);
begin
  CommOpen := False;
  CommHandle := CreateFile(PChar('\\.\' + CommString), GENERIC_READ or GENERIC_WRITE, 0, nil, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, 0);
  if CommHandle = INVALID_HANDLE_VALUE then CommError('Unable to open');
  BuildCommDCB(PChar('115200,n,8,1'), CommDCB);
  CommDCB.Flags := 0;
  SetCommState(CommHandle, CommDCB);
  SetCommTimeouts(CommHandle, CommTimeouts);
  TxBuffLength := 0;
  RxBuffStart := 0;
  RxBuffEnd := 0;
  CommOpen := True;
end;

// Add encoded long (11 bytes) to comm buffer
procedure TLong(x: cardinal);
var
  i: integer;
begin
  for i := 0 to 10 do
  begin
    TByte($92 or -Ord(i=10) and $60 or x and 1 or x and 2 shl 2 or x and 4 shl 4);
    x := x shr 3;
  end;
end;

// Add byte to comm buffer
procedure TByte(x: byte);
begin
  TxBuff[TxBuffLength] := x;
  Inc(TxBuffLength);
  if TxBuffLength = TxBuffSize then TComm;
end;

// Transmit comm buffer
procedure TComm;
var
  BytesWritten: cardinal;
begin
  if not WriteFile(CommHandle, TxBuff, TxBuffLength, BytesWritten, nil) then
    CommError('Unable to write to');
  if BytesWritten <> TxBuffLength then
    CommError('Transmit stall on');
  TxBuffLength := 0;
end;

// Receive comm response via echoed byte
function RBit(Echo: boolean; Timeout: integer): byte;
var
  Ticks: cardinal;
begin
  Ticks := GetTickCount;
  while GetTickCount - Ticks < Timeout do
  begin
    if Echo then
    begin
      TByte($F9);
      TComm;
      DelayMilliseconds(25);
    end;
    if RxBuffStart = RxBuffEnd then RComm;
    if RxBuffStart <> RxBuffEnd then
    begin
      Result := RxBuff[RxBuffStart] - $FE;
      Inc(RxBuffStart);
      if Result and $FE = 0 then Exit;
      HardwareLostError;
    end;
  end;
  HardwareLostError;
end;

// Receive any data into comm buffer
procedure RComm;
begin
  RxBuffStart := 0;
  RxBuffEnd := 0;
  if not ReadFile(CommHandle, RxBuff, RxBuffSize, RxBuffEnd, nil) then
    CommError('Unable to read from');
end;

// Hardware lost error
procedure HardwareLostError;
begin
  CommError('Hardware lost on');
end;

// Comm error
procedure CommError(Msg: string);
begin
  if CommOpen then CloseComm;
  if AbortMode then
  begin
    ProgressForm.Hide;
    MessageDlg(Msg + ' ' + CommString + '.', mtError, [mbOK], 0);
  end;
  Abort;
end;

// Close comm port
procedure CloseComm;
begin
  CloseHandle(CommHandle);
  CommOpen := False;
end;

// Return comm port string
function CommString: string;
begin
  Result := 'COM' + IntToStr(CommPort);
end;


/////////////////////
//  Miscellaneous  //
/////////////////////

// Delay milliseconds
procedure DelayMilliseconds(ms: cardinal);
var
  Ticks: cardinal;
begin
  Ticks := GetTickCount;
  while GetTickCount - Ticks < ms do;
end;

// Iterate LFSR
function IterateLFSR: byte;
begin
  Result := LFSR and $01;
  LFSR := LFSR shl 1 and $FE or (LFSR shr 7 xor LFSR shr 5 xor LFSR shr 4 xor LFSR shr 1) and 1;
end;

end.

 
pik33
Posts: 829
Joined: Fri Sep 30, 2016 6:30 pm
Location: Poland
Contact:

Re: Propeller CPU connected to Ultibo/pi

Postby pik33 » Mon Feb 19, 2018 1:12 pm

If you want it fast, do it. I have a lot of work with the semester which is now starting. Prepare lectures, update instructions, etc - no time available to play until Thursday.

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