Search found 27 matches

by rvanspaa
Thu Aug 01, 2019 12:12 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Ultibo wrote:That at least confirms that the try/finally is more costly than the spinlock (as suspected).


Indeed, which leads me to ask if the try-finally is really needed? Also, is spinlock needed for a single CPU machine like the RPi?
by rvanspaa
Tue Jul 30, 2019 8:03 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Hi, Just one last addition. This falls in the "neither column". 000000E5 - 0261845C - Configuration:- Neither try-finally nor spinlock enabled 000000E6 - 0261845C - Pin # = 43 000000E7 - 0261845C - Actual requested speed = 914285 interrupts/sec. 000000E8 - 0261845C - Run duration = 14.545 ...
by rvanspaa
Tue Jul 30, 2019 5:15 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Hi,

Ultibo wrote:Ok, we'll wait to see the updated results when you resolve that.


I've compiled the results of some tests into a little table (see attached).
by rvanspaa
Sun Jul 14, 2019 11:43 pm
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Hi, Just thought I would show you some testing runs. Note that when the interrupt gets overloaded, the number increases dramatically (see last entry). I suspect this may have something to do with the interrupt not being cleared before the next interrupt is generated, but that's just a guess. BTW, I ...
by rvanspaa
Sun Jul 14, 2019 3:05 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Hi,

I found the cause of the problem. I had defined the "speed" parameter as "word" rather than longword, so by definition the upper limit on speed was 65535. :oops:
Once I replaced if with longword, I started getting much better numbers. :D
by rvanspaa
Sun Jul 14, 2019 12:54 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

That's lucky in a way because I think the spinlock would likely be a mandatory part of the handler in avoid to prevent a race with other CPUs. I would have thought the try/finally would potentially be more expensive since it has to save the entire state of the CPU, but you'd have to test it to find...
by rvanspaa
Sat Jul 13, 2019 7:11 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

The difference will be between BCM2708GPIOInterruptHandler and BCM2708ARMTimerInterruptHandler , everything else in the path will be the same. While BCM2708GPIOInterruptHandler is not a lot more complex than BCM2708ARMTimerInterruptHandler it does contain some things that could add a little overhea...
by rvanspaa
Thu Jul 11, 2019 3:56 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

I had noticed that comment in the source but I also noticed that it said: with a very small assembler code fast interrupt handler which would likely make a significant difference overall. Ultibo isn't really able to provide highly optimized ultra fast implementations of all of these things because ...
by rvanspaa
Thu Jul 11, 2019 3:18 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Remember that the GPIO is a device with its own clock and its own behavior so the results can be very different from a timer device. As long as you are using GPIO_EVENT_FLAG_INTERRUPT then there is no reason the scheduler should be involved, since the scheduler interrupt rate is 2000 per second the...
by rvanspaa
Thu Jul 11, 2019 12:29 am
Forum: Discussion
Topic: fiq design
Replies: 80
Views: 13392

Re: fiq design

Hi, I modified your code a little (see comments in attached), and am processing about 1.2 million interrupts/second on an RPi B+, using a recent version of Ultibo. That's a very interesting result especially given it is a RPi B+, thanks for the information. I'm not sure if you are in a position to t...

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